JPH06310759A - Image pickup device - Google Patents
Image pickup deviceInfo
- Publication number
- JPH06310759A JPH06310759A JP12337993A JP12337993A JPH06310759A JP H06310759 A JPH06310759 A JP H06310759A JP 12337993 A JP12337993 A JP 12337993A JP 12337993 A JP12337993 A JP 12337993A JP H06310759 A JPH06310759 A JP H06310759A
- Authority
- JP
- Japan
- Prior art keywords
- array
- image
- common electrode
- clip terminal
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000003384 imaging method Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000013021 overheating Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の利用分野】この発明は、ＬＥＤヘッドや、イメ
ージセンサ等の画像装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image device such as an LED head and an image sensor.
【０００２】[0002]
【従来技術】発明者は、画像アレイをガラス基板にフリ
ップチップ接続し、アレイ裏面の共通電極にはリードフ
レームを接続した画像装置を提案した（特開平４−３５
６，９７８号公報）。ここでのリードフレームは、画像
アレイを搭載したのと同じ主面に他端が接続される。2. Description of the Related Art The inventor has proposed an image device in which an image array is flip-chip connected to a glass substrate and a lead frame is connected to a common electrode on the back surface of the array (Japanese Patent Laid-Open No. 4-35).
6,978). The lead frame here has the other end connected to the same main surface on which the image array is mounted.
【０００３】発明者はその後、フリップチップ接続時に
画像アレイが損傷するという問題に直面した。フリップ
チップ接続では、画像アレイをダイマウントした後、共
通電極の側から加圧して、リフロー炉等でフリップチッ
プ接続用のバンプを溶着する。溶着に必要な圧力は、ア
レイ当たりのバンプの数を６４〜１２８として、数Ｋｇ
程度となる。工程を単純化するため、多数の画像アレイ
を同時に加圧するので、特定のアレイに局所的に圧力が
加わり易い。例えば４０個の画像アレイを均一に加圧す
るのは困難である。これが画像アレイの損傷の原因であ
った。The inventor then faced the problem of image array damage during flip chip bonding. In the flip-chip connection, after the image array is die-mounted, pressure is applied from the common electrode side and a bump for flip-chip connection is welded in a reflow furnace or the like. The pressure required for welding is several Kg when the number of bumps per array is 64 to 128.
It will be about. In order to simplify the process, many image arrays are pressed at the same time, which makes it easy to locally apply pressure to a particular array. For example, it is difficult to uniformly press 40 image arrays. This was the cause of the image array damage.
【０００４】[0004]
【発明の課題】この発明の課題は、1) 画像アレイのフ
リップチップ接続を容易にし、特にフリップチップ接続
時のアレイの損傷を防止し、2) 画像アレイを共通電極
を介して放熱し、3) 画像アレイをクリップ端子で静電
シールドし、4) 画像アレイの共通電極への配線抵抗を
小さくする、ことにある。An object of the present invention is to 1) facilitate flip-chip connection of an image array, particularly to prevent damage to the array during flip-chip connection, and 2) radiate the image array through a common electrode, 4) The image array is electrostatically shielded by the clip terminal, and 4) the wiring resistance to the common electrode of the image array is reduced.
【０００５】[0005]
【発明の構成】この発明は、受発光素子を集積化した画
像アレイを、透明基板の一方の主面にフリップチップ接
続した画像装置において、前記画像アレイのフリップチ
ップ接続部と反対側の主面に共通電極を設けると共に、
前記基板を挟むように配置したクリップ端子の一端を前
記共通電極に接続し、かつその他端を、透明基板からみ
て前記主面と反対側に設けた他の配線パターンに接続し
たことを特徴とする。ここで画像アレイには、例えばＬ
ＥＤアレイや、ＭＯＳＣＣＤアレイ、ＭＯＳ光センサア
レイ等を用いる。クリップ端子の他端は、透明基板と背
中合わせに配置した他の基板、例えばプリント基板、に
設けた配線パターン接続しても良く、あるいは透明基板
の反対側の主面に設けた配線パターンに接続しても良
い。According to the present invention, in an image device in which an image array in which light-receiving and emitting elements are integrated is flip-chip connected to one main surface of a transparent substrate, the main surface of the image array opposite to the flip-chip connection portion is provided. With a common electrode on
One end of the clip terminal arranged so as to sandwich the substrate is connected to the common electrode, and the other end is connected to another wiring pattern provided on the side opposite to the main surface when viewed from the transparent substrate. . Here, in the image array, for example, L
An ED array, a MOS CCD array, a MOS photosensor array, etc. are used. The other end of the clip terminal may be connected to a wiring pattern provided on another substrate arranged back to back with the transparent substrate, for example, a printed circuit board, or to a wiring pattern provided on the main surface on the opposite side of the transparent substrate. May be.
【０００６】[0006]
【発明の作用】この発明では、クリップ端子を透明基板
を挟み込むように配置し、クリップ端子からの圧力を画
像アレイの共通電極に加える。そしてこの圧力と熱や超
音波振動等で、画像アレイをフリップチップ接続する。
クリップ端子からの圧力は、端子の厚さや材質，形状等
が一定なので一定となり、画像アレイに無理な力が加わ
り損傷することがない。用いたクリップ端子は、画像ア
レイの共通電極への電気的接続の他に、静電シールドや
放熱板の役割を兼ね、低抵抗で共通電極へ配線でき、面
積が広いので感光体ドラム等からの電磁ノイズに対する
静電シールドとして作用し、かつ共通電極を冷却して画
像アレイの過熱を防止する。According to the present invention, the clip terminals are arranged so as to sandwich the transparent substrate, and the pressure from the clip terminals is applied to the common electrode of the image array. Then, the image array is flip-chip connected by the pressure, heat, ultrasonic vibration, and the like.
The pressure from the clip terminal is constant because the thickness, material, shape, etc. of the terminal are constant, and no excessive force is applied to the image array to prevent damage. The clip terminal used not only electrically connects to the common electrode of the image array, but also serves as an electrostatic shield and a heat sink, and can be wired to the common electrode with low resistance. It acts as an electrostatic shield against electromagnetic noise and cools the common electrode to prevent overheating of the image array.
【０００７】[0007]
【実施例】図１〜図４に、ＬＥＤヘッドを例に実施例を
示す。図１において、２はガラス等の透明基板で、４は
プリント基板等の他の基板であり、ガラス基板２と背中
合わせに密着して配置する。６はガラス基板２の一方の
主面に設けたデータバス、８はＬＥＤアレイで、９は金
等の共通電極、１０は半田等のバンプ、１２はデータバ
ス６側に設けた金等のバンプである。プリント基板４に
は切り欠き部１４を設け、ＬＥＤアレイ８からの光を外
へ導くようにする。１６はスイッチングＩＣで、ＬＥＤ
アレイ８をダイナミックドライブするためのスイッチン
グ回路を内蔵している。１８は基板４に設けた配線パタ
ーンである。２０はクリップ端子で、画像アレイ８の共
通電極９と、基板４の配線パターン１８とを接続する。
クリップ端子２０にはリン青銅等のバネ性のある材料を
用い、基板２，４を挟み込むように配置し、図の矢印の
ような加圧力を配線パターン１８と共通電極９とに加え
る。この加圧力をフリップチップ接続時の圧力として用
いると共に、基板２，４の固定にも用いる。EXAMPLES FIGS. 1 to 4 show an example of an LED head. In FIG. 1, reference numeral 2 is a transparent substrate such as glass, and 4 is another substrate such as a printed circuit board, which are arranged back to back and in close contact with the glass substrate 2. 6 is a data bus provided on one main surface of the glass substrate 2, 8 is an LED array, 9 is a common electrode such as gold, 10 is a bump such as solder, and 12 is a bump such as gold provided on the data bus 6 side. Is. The printed board 4 is provided with a notch 14 so that the light from the LED array 8 is guided to the outside. 16 is a switching IC, which is an LED
A switching circuit for dynamically driving the array 8 is built in. Reference numeral 18 is a wiring pattern provided on the substrate 4. A clip terminal 20 connects the common electrode 9 of the image array 8 and the wiring pattern 18 of the substrate 4.
A material having a spring property, such as phosphor bronze, is used for the clip terminal 20 and is arranged so as to sandwich the substrates 2 and 4, and a pressing force as indicated by an arrow in the drawing is applied to the wiring pattern 18 and the common electrode 9. This pressure is used as the pressure for flip-chip connection and also for fixing the substrates 2 and 4.
【０００８】図２に、透明基板２のＬＥＤアレイ８側の
主面を示す。透明基板２の両端には、ＬＥＤアレイ８に
画像信号を供給するための駆動ＩＣ２２を設ける。駆動
ＩＣ２２には、画像信号を一時的に記憶するためのシフ
トレジスタと、ＬＥＤアレイ８を定電流駆動するための
定電流回路とを内蔵させる。そして駆動ＩＣ２２にデー
タバス６を図のように接続し、ＬＥＤアレイ８毎にジグ
ザグにデータバス６を折り返させる。またクリップ端子
２０は図に示すように、ＬＥＤアレイ８の裏面のほぼ全
面を被覆している。FIG. 2 shows the main surface of the transparent substrate 2 on the LED array 8 side. Driving ICs 22 for supplying image signals to the LED array 8 are provided at both ends of the transparent substrate 2. The drive IC 22 has a built-in shift register for temporarily storing an image signal and a constant current circuit for driving the LED array 8 with a constant current. Then, the data bus 6 is connected to the drive IC 22 as shown in the figure, and the data bus 6 is folded back zigzag for each LED array 8. Further, as shown in the figure, the clip terminal 20 covers almost the entire back surface of the LED array 8.
【０００９】駆動ＩＣ２２は定電流回路を内蔵している
ため、最も過熱し易いＩＣである。そこでクリップ端子
２４で、駆動ＩＣ２２を基板４の配線パターン１８に接
続する。クリップ端子２４は先端が駆動ＩＣ２２の近傍
に現れるように配置し、図示しない配線パターンを介し
て駆動ＩＣ２２に接続する。そしてクリップ端子２４に
より、駆動ＩＣ２２の熱をプリント基板４の側に逃が
す。好ましくは駆動ＩＣ２２の端面とクリップ端子２４
の先端との間隔Ｄを０．５〜３ｍｍとする。このように
すれば、駆動ＩＣ２２を多数のクリップ端子２４により
放熱し、過熱を防止することができる。Since the drive IC 22 has a built-in constant current circuit, it is the IC that is most easily overheated. Therefore, the drive IC 22 is connected to the wiring pattern 18 of the substrate 4 by the clip terminal 24. The clip terminal 24 is arranged so that its tip appears near the drive IC 22, and is connected to the drive IC 22 via a wiring pattern (not shown). Then, the heat of the drive IC 22 is released to the printed circuit board 4 side by the clip terminal 24. Preferably, the end surface of the drive IC 22 and the clip terminal 24
The distance D from the tip of is 0.5 to 3 mm. In this way, the driving IC 22 can be radiated by the large number of clip terminals 24 to prevent overheating.
【００１０】図３に、プリント基板４のスイッチングＩ
Ｃ１６側の配置を示す。鎖線で示した領域が配線パター
ン１８で、クリップ端子２０，２４は配線パターン１８
を介してスイッチングＩＣ１６等に接続する。FIG. 3 shows the switching I of the printed circuit board 4.
The arrangement on the C16 side is shown. The area shown by the chain line is the wiring pattern 18, and the clip terminals 20 and 24 are the wiring pattern 18.
To the switching IC 16 or the like.
【００１１】図４に、フリップチップ接続の工程を示
す。クリップ端子２０，２４は例えば半田付けで接続
し、事前に半田メッキを施すと共に、半田付け部にクリ
ーム半田を塗布しておく。これと並行して、ダイマウン
タでＬＥＤアレイ８をダイマウントし、基板２に仮止め
しておく。次にクリップ端子２０，２４をセットする。
クリップ端子２０からの圧力は、その幅や厚さ，材質，
形状が一定であれば、一定となる。そして均一なクリッ
プ端子２０を製造することはきわめて容易で、各ＬＥＤ
アレイ８には均一な圧力が加わり、接続時にＬＥＤアレ
イ８が損傷することがない。クリップ端子２０，２４を
セットすることにより、基板２，４は仮止めされ、同時
にＬＥＤアレイ８はフリップチップ位置に固定される。
この状態で基板２，４を半田リフロー炉等をくぐらせ
る。するとクリップ端子２０，２４のクリーム半田が溶
融し、クリップ端子２０，２４の半田付けが行われる。
これによって基板２，４が一体に固定される。これと同
時にクリップ端子２０からの加圧力とリフロー炉の熱
で、バンプ１０，１２が溶着し、フリップチップ接続が
完成する。FIG. 4 shows a flip-chip connection process. The clip terminals 20 and 24 are connected, for example, by soldering, and solder plating is performed in advance and cream solder is applied to the soldering portion. In parallel with this, the LED array 8 is die-mounted with a die mounter and temporarily fixed to the substrate 2. Next, the clip terminals 20 and 24 are set.
The pressure from the clip terminal 20 depends on its width, thickness, material,
If the shape is constant, it will be constant. And it is very easy to manufacture a uniform clip terminal 20,
A uniform pressure is applied to the array 8 and the LED array 8 is not damaged during connection. By setting the clip terminals 20 and 24, the substrates 2 and 4 are temporarily fixed, and at the same time, the LED array 8 is fixed to the flip chip position.
In this state, the substrates 2 and 4 are passed through a solder reflow furnace or the like. Then, the cream solder of the clip terminals 20 and 24 is melted, and the clip terminals 20 and 24 are soldered.
As a result, the substrates 2 and 4 are fixed together. At the same time, the bumps 10 and 12 are welded by the pressure applied from the clip terminal 20 and the heat of the reflow furnace, and the flip chip connection is completed.
【００１２】フリップチップ接続後のＬＥＤヘッドで
は、クリップ端子２０はＬＥＤアレイ８に対する静電シ
ールドとして働く。これはクリップ端子２０がＬＥＤア
レイ８の裏面の大部分を被覆するからである。またクリ
ップ端子２０は面積が広く、共通電極９をプリント基板
４の配線パターン１８に低抵抗で接続することができ
る。さらにクリップ端子２０は、ＬＥＤアレイ８の放熱
板として作用し、その過熱を防止することができる。駆
動ＩＣ２２には多数のクリップ端子２４をその近傍で接
続したので、クリップ端子２４を介して放熱させ、過熱
を防止することができる。In the LED head after flip chip connection, the clip terminal 20 functions as an electrostatic shield for the LED array 8. This is because the clip terminal 20 covers most of the back surface of the LED array 8. Further, the clip terminal 20 has a large area, and the common electrode 9 can be connected to the wiring pattern 18 of the printed board 4 with low resistance. Further, the clip terminal 20 acts as a heat dissipation plate of the LED array 8 and can prevent its overheating. Since a large number of clip terminals 24 are connected to the drive IC 22 in the vicinity thereof, heat can be released through the clip terminals 24 to prevent overheating.
【００１３】[0013]
【発明の効果】この発明では、以下の効果が得られる。 1) 画像アレイのフリップチップ接続を容易にし、フリ
ップチップ接続時の画像アレイの損傷を防止する。 2) 画像アレイを共通電極からクリップ端子を介して放
熱し、画像アレイの温度上昇を防止する。 3) 画像アレイをクリップ端子で静電シールドし、誤動
作を防止する。 4) 画像アレイの共通電極への配線抵抗を小さくし、印
画品質を向上させる。According to the present invention, the following effects can be obtained. 1) Flip chip connection of the image array is facilitated and damage to the image array during flip chip connection is prevented. 2) The image array is radiated from the common electrode via the clip terminal to prevent the temperature rise of the image array. 3) The image array is electrostatically shielded by the clip terminal to prevent malfunction. 4) Reduce wiring resistance to the common electrode of the image array to improve printing quality.
【図１】 実施例の画像装置の要部断面図FIG. 1 is a cross-sectional view of a main part of an image device according to an embodiment.
【図２】 実施例の画像装置での、透明基板の配置を示
す平面図FIG. 2 is a plan view showing the arrangement of transparent substrates in the image device of the embodiment.
【図３】 実施例の画像装置での、プリント基板の配置
を示す平面図FIG. 3 is a plan view showing the arrangement of printed circuit boards in the image device of the embodiment.
【図４】 実施例の画像装置での、フリップチップ接続
工程を示す工程図FIG. 4 is a process diagram showing a flip-chip connection process in the image device of the embodiment.
２ ガラス基板 ４ プリント基板 ６ データバス ８ ＬＥＤアレイ ９ 共通電極 １０ バンプ １２ バンプ １６ スイッチングＩＣ １８ 配線パターン ２０ クリップ端子 ２２ 駆動ＩＣ ２４ クリップ端子 2 glass substrate 4 printed circuit board 6 data bus 8 LED array 9 common electrode 10 bump 12 bump 16 switching IC 18 wiring pattern 20 clip terminal 22 drive IC 24 clip terminal
Claims (1)
透明基板の一方の主面にフリップチップ接続した画像装
置において、 前記画像アレイのフリップチップ接続部と反対側の主面
に共通電極を設けると共に、 前記基板を挟むように配置したクリップ端子の、一端を
前記共通電極に接続し、かつその他端を、透明基板から
みて前記主面と反対側に設けた他の配線パターンに接続
したことを特徴とする、画像装置。1. An image array in which light receiving and emitting elements are integrated,
In an image device flip-chip connected to one main surface of a transparent substrate, a common electrode is provided on the main surface of the image array opposite to the flip-chip connection portion, and one end of a clip terminal arranged to sandwich the substrate. Is connected to the common electrode, and the other end is connected to another wiring pattern provided on the side opposite to the main surface when viewed from the transparent substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12337993A JPH06310759A (en) | 1993-04-26 | 1993-04-26 | Image pickup device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12337993A JPH06310759A (en) | 1993-04-26 | 1993-04-26 | Image pickup device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06310759A true JPH06310759A (en) | 1994-11-04 |
Family
ID=14859127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12337993A Pending JPH06310759A (en) | 1993-04-26 | 1993-04-26 | Image pickup device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06310759A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002100785A (en) * | 2000-07-18 | 2002-04-05 | Infineon Technologies Ag | Surface-mountable optoelectronic module and optoelectronic coupling unit with optoelectronic module |
| KR100419611B1 (en) * | 2001-05-24 | 2004-02-25 | 삼성전기주식회사 | A Light Emitting Diode, a Lighting Emitting Device Using the Same and a Fabrication Process therefor |
| JP2004287215A (en) * | 2003-03-24 | 2004-10-14 | Fuji Photo Film Co Ltd | Transmission type optical modulation apparatus and method for packaging the same |
| JP2004325939A (en) * | 2003-04-25 | 2004-11-18 | Seiko Epson Corp | Optical communication module, optical communication system and its manufacture method |
| US7065275B2 (en) | 2003-06-18 | 2006-06-20 | Seiko Epson Corporation | Optic communications module, method for manufacturing the same, optic communications device, and electronic equipment |
| WO2006089510A2 (en) * | 2005-02-24 | 2006-08-31 | Wolfram Henning | Optical semiconductor component and associated contacting device |
| US7693360B2 (en) | 2002-06-24 | 2010-04-06 | Nec Corporation | Optoelectronic hybrid integrated module and light input/output apparatus having the same as component |
-
1993
- 1993-04-26 JP JP12337993A patent/JPH06310759A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002100785A (en) * | 2000-07-18 | 2002-04-05 | Infineon Technologies Ag | Surface-mountable optoelectronic module and optoelectronic coupling unit with optoelectronic module |
| US6550982B2 (en) | 2000-07-18 | 2003-04-22 | Infineon Technologies Ag | Optoelectronic surface-mountable module and optoelectronic coupling unit |
| EP1174745A3 (en) * | 2000-07-18 | 2004-05-26 | Infineon Technologies AG | Optoelectronic surface- mountable module |
| KR100419611B1 (en) * | 2001-05-24 | 2004-02-25 | 삼성전기주식회사 | A Light Emitting Diode, a Lighting Emitting Device Using the Same and a Fabrication Process therefor |
| US7693360B2 (en) | 2002-06-24 | 2010-04-06 | Nec Corporation | Optoelectronic hybrid integrated module and light input/output apparatus having the same as component |
| JP2004287215A (en) * | 2003-03-24 | 2004-10-14 | Fuji Photo Film Co Ltd | Transmission type optical modulation apparatus and method for packaging the same |
| JP2004325939A (en) * | 2003-04-25 | 2004-11-18 | Seiko Epson Corp | Optical communication module, optical communication system and its manufacture method |
| US7065275B2 (en) | 2003-06-18 | 2006-06-20 | Seiko Epson Corporation | Optic communications module, method for manufacturing the same, optic communications device, and electronic equipment |
| WO2006089510A2 (en) * | 2005-02-24 | 2006-08-31 | Wolfram Henning | Optical semiconductor component and associated contacting device |
| WO2006089510A3 (en) * | 2005-02-24 | 2007-01-11 | Wolfram Henning | Optical semiconductor component and associated contacting device |
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