JPH06302968A - Multilayer interconnection ceramic board - Google Patents
Multilayer interconnection ceramic boardInfo
- Publication number
- JPH06302968A JPH06302968A JP11538193A JP11538193A JPH06302968A JP H06302968 A JPH06302968 A JP H06302968A JP 11538193 A JP11538193 A JP 11538193A JP 11538193 A JP11538193 A JP 11538193A JP H06302968 A JPH06302968 A JP H06302968A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- palladium
- silver
- wiring
- surface wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、セラミックス多層配線
基板に関し、特に低温焼成セラミックスを使用したセラ
ミックス多層配線基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic multilayer wiring board, and more particularly to a ceramic multilayer wiring board using low temperature fired ceramics.
【０００２】[0002]
【従来の技術】近年における電子機器は、小型化、軽量
化、高密度化、及び高信頼性化が要求され、これに応じ
て半導体チップは、高集積密度化、高速化の方向へめざ
ましく発展してきている。2. Description of the Related Art In recent years, electronic devices are required to be smaller, lighter, higher in density and higher in reliability, and accordingly, semiconductor chips have been remarkably developed in the direction of higher integration density and higher speed. I'm doing it.
【０００３】これに伴って、基板用セラミックスに対し
ても従来以上の特性が求められ、従来多用されているア
ルミナセラミックスの持つ欠点、すなわち焼結に１５０
０〜１６００°Ｃの高温を必要とするため、同時焼成さ
れる導体材料としてはタングステン、モリブデンなどの
比抵抗の比較的大きな金属しか利用できず、電気信号が
遅延するという欠点を克服するため、近年においては、
９５０°Ｃ以下の低温で焼成できる低温焼成セラミック
スが開発され、該低温焼成セラミックスを複数枚積層し
たセラミックス多層配線基板が利用されつつある。Along with this, the ceramics for substrates are required to have better characteristics than the conventional ones, and the disadvantage of the alumina ceramics, which has been widely used, is 150
Since a high temperature of 0 to 1600 ° C. is required, only metal having a relatively large specific resistance such as tungsten and molybdenum can be used as the conductor material to be co-fired, and in order to overcome the drawback of delaying an electric signal, In recent years,
Low-temperature fired ceramics that can be fired at a low temperature of 950 ° C. or less have been developed, and ceramic multilayer wiring boards in which a plurality of such low-temperature fired ceramics are laminated are being used.
【０００４】この低温焼成セラミックスを用いたセラミ
ックス多層配線基板の場合には、その焼成温度が低いた
めに導体材料として各種の比抵抗の小さい金属の使用が
可能となり、例えば内部配線導体としては銀、銀系の導
体、銅或いは金が、表面配線導体としては銅、銀−パラ
ジウム、銀−白金、或いは金等が用いられている。In the case of a ceramic multilayer wiring board using this low-temperature fired ceramics, since the firing temperature is low, it is possible to use various metals having a low specific resistance as a conductor material. A silver-based conductor, copper or gold is used, and as the surface wiring conductor, copper, silver-palladium, silver-platinum, gold or the like is used.
【０００５】[0005]
【発明が解決しようとする課題】ここで、上記内部配線
導体として、例えば銀を用いていたセラミックス多層配
線基板においては、通常表面配線導体としては銀のマイ
グレーションを防止する観点から、パラジウムを含む銀
−パラジウム導体が用いられ、該内部配線導体と表面配
線導体とを導通させるヴィアに充填するヴィア導体とし
ては、その何れかの導体材料を使用していた。In a ceramic multilayer wiring board in which silver is used as the internal wiring conductor, silver containing palladium is usually used as the surface wiring conductor from the viewpoint of preventing migration of silver. -A palladium conductor is used, and any one of the conductor materials is used as a via conductor to be filled in a via that electrically connects the internal wiring conductor and the surface wiring conductor.
【０００６】そのため、内部配線とヴィア、或いは表面
配線とヴィアの接続部のいずれかで、銀導体と銀−パラ
ジウム導体とを接続することとなり、この異種の導体材
料の接続部付近での銀原子とパラジウム原子の加熱時に
おける移動速度の違いから、銀側導体中に空洞が生じ、
導通不良が生じることがあった。このことは、特に上記
表面配線導体を焼き付けた後、抵抗や金導体の焼成のた
めの再加熱を行うと顕著に現れ、導通不良となる基板の
数が増えていた。For this reason, the silver conductor and the silver-palladium conductor are connected to each other by the connection portion between the internal wiring and the via, or the surface wiring and the via, and the silver atom near the connection portion of the different kinds of conductive materials is connected. Due to the difference in the moving speed of the copper and palladium atoms during heating, a cavity was created in the silver-side conductor,
Poor continuity sometimes occurred. This remarkably appears particularly when the surface wiring conductor is baked and then reheated for firing the resistance and the gold conductor, and the number of substrates having conduction failure increases.
【０００７】本発明は、上述した従来技術が有する課題
に鑑み成されたものであって、その目的は、内部配線と
ヴィア、及び表面配線とヴィアの接続が確実なものとな
るセラミックス多層配線基板を提供することにある。The present invention has been made in view of the above-mentioned problems of the prior art, and its purpose is to ensure a reliable connection between internal wiring and via, and surface wiring and via. To provide.
【０００８】[0008]
【課題を解決するための手段】本発明は、上記目的を達
成すべく、低温焼成セラミックスを複数枚積層して形成
したセラミックス多層配線基板において、表面配線導体
として銀−パラジウム導体を用い、該表面配線導体と接
するヴィア導体には、上記表面配線導体のパラジウム比
率の１／５〜１／２のパラジウムを含む銀−パラジウム
導体を用い、さらにヴィア導体と接する内部配線導体に
は、前記ヴィア導体のパラジウム比率の１／５以上のパ
ラジウムを含む銀−パラジウム導体を用いたセラミック
ス多層配線基板とした。In order to achieve the above object, the present invention uses a silver-palladium conductor as a surface wiring conductor in a ceramic multilayer wiring substrate formed by laminating a plurality of low temperature fired ceramics, A silver-palladium conductor containing 1/5 to 1/2 of the palladium ratio of the surface wiring conductor is used as the via conductor in contact with the wiring conductor, and an internal wiring conductor in contact with the via conductor is used as the via conductor. A ceramic multilayer wiring board using a silver-palladium conductor containing palladium at 1/5 or more of the palladium ratio.
【０００９】上記した本発明にかかるセラミックス多層
配線基板によれば、表面配線導体とヴィア導体の接する
部分、及びヴィア導体と内部配線導体の接する部分でパ
ラジウム比率が急激に変化していないため、該導体中の
金属原子の移動が少なくなり、接続部付近における空洞
が無くなることから内部配線とヴィア、及び表面配線と
ヴィアの接続が確実なものとなる。According to the above-mentioned ceramic multilayer wiring board according to the present invention, the palladium ratio does not change abruptly at the contact portion between the surface wiring conductor and the via conductor and the contact portion between the via conductor and the internal wiring conductor. The movement of metal atoms in the conductor is reduced, and voids in the vicinity of the connection portion are eliminated, so that the connection between the internal wiring and the via and between the surface wiring and the via becomes reliable.
【００１０】ここで、上記表面配線導体としては、その
パラジウム比率は特には限定されないが、好ましくはパ
ラジウム比率が１０〜３０ｗｔ％の銀−パラジウム導体
を用いる。これは、パラジウム比率が１０ｗｔ％に満た
ない場合は、銀のマイグレーションを抑えきれない心配
があるためであり、また逆にパラジウム比率が３０ｗｔ
％を越えると、導体材料としての比抵抗値が高くなり、
電気信号の伝送損失が増すためである。Here, as the surface wiring conductor, the palladium ratio is not particularly limited, but a silver-palladium conductor having a palladium ratio of 10 to 30 wt% is preferably used. This is because if the palladium ratio is less than 10 wt%, there is a concern that the migration of silver cannot be suppressed, and conversely, the palladium ratio is 30 wt%.
When it exceeds%, the specific resistance value as a conductor material increases,
This is because the transmission loss of electric signals increases.
【００１１】また、上記表面配線導体と接するヴィア導
体としては、上述したように表面配線導体のパラジウム
比率の１／５〜１／２のパラジウムを含む銀−パラジウ
ム導体を用いる。例えば、表面配線導体としてパラジウ
ム比率が２０ｗｔ％のものを用いた場合には、ヴィア導
体としてはパラジウム比率が４〜１０ｗｔ％の範囲内に
ある銀−パラジウム導体を用いる。これは、パラジウム
比率が１／５に満たない場合には表面配線導体との接続
が悪く、導通不良が生じる場合があるためであり、また
逆に１／２を越える場合は、内部配線のシート抵抗を下
げるのに不都合となるためである。As the via conductor in contact with the surface wiring conductor, the silver-palladium conductor containing palladium in the ratio of 1/5 to 1/2 of the palladium ratio of the surface wiring conductor is used as described above. For example, when a surface wiring conductor having a palladium ratio of 20 wt% is used, a silver-palladium conductor having a palladium ratio of 4 to 10 wt% is used as the via conductor. This is because if the palladium ratio is less than 1/5, the connection with the surface wiring conductor may be poor and conduction failure may occur. This is because it becomes inconvenient to reduce the resistance.
【００１２】さらに、前記ヴィア導体と接する内部配線
導体には、ヴィア導体のパラジウム比率の１／５以上の
パラジウムを含む銀−パラジウム導体を用いる。すなわ
ち、ヴィア導体のパラジウム比率が５ｗｔ％である場合
には、内部配線導体としてはパラジウム比率が１ｗｔ％
以上の銀−パラジウム導体を用いる。これは、パラジウ
ム比率が１／５に満たない場合には、上記表面配線導体
の場合と同じく該内部配線導体とヴィア導体との接続が
不完全なものとなり、導通不良が生じる場合があるため
である。なお、この内部配線導体におけるパラジウム比
率の上限は特には限定されないが、シート抵抗を考慮し
た場合にはそのパラジウム比率は５ｗｔ％以下であるこ
とが好ましい。Further, a silver-palladium conductor containing palladium at 1/5 or more of the palladium ratio of the via conductor is used as the internal wiring conductor in contact with the via conductor. That is, when the palladium ratio of the via conductor is 5 wt%, the palladium ratio of the internal wiring conductor is 1 wt%.
The above silver-palladium conductor is used. This is because, if the palladium ratio is less than 1/5, the internal wiring conductor and the via conductor may be incompletely connected to each other as in the case of the surface wiring conductor, and a conduction failure may occur. is there. The upper limit of the palladium ratio in this internal wiring conductor is not particularly limited, but in consideration of the sheet resistance, the palladium ratio is preferably 5 wt% or less.
【００１３】[0013]
【実施例】以下、本発明の実施例を比較例と共に挙げ、
本発明を詳細に説明する。EXAMPLES Examples of the present invention will be given below together with comparative examples.
The present invention will be described in detail.
【００１４】−導体ペーストの原材料− 銀は、三井金属鉱業（株）社製の粒径が約１μｍの銀粉
末を用いた。またパラジウムは、住友金属鉱山（株）社
製の粒径約０．５μｍのパラジウム粉末を用いた。無機
結合剤としてのガラスは、８５０°Ｃの焼成で結晶を析
出するような組成のものを、表面配線導体、ヴィア導
体、及び内部配線導体としての用途に応じて適量加え
た。また、有機ビヒクルは、導体ペーストがスクリーン
印刷に適した粘度になるように、通常ペーストに使用さ
れるものを適量加えた。なお、表面配線導体として使用
する導体ペースト中には、はんだ濡れ性及び接着強度改
善のために酸化物粉末を添加した。-Raw Material of Conductor Paste- As silver, silver powder having a particle size of about 1 μm manufactured by Mitsui Mining & Smelting Co., Ltd. was used. As the palladium, palladium powder having a particle size of about 0.5 μm manufactured by Sumitomo Metal Mining Co., Ltd. was used. As the glass as an inorganic binder, a glass having a composition that precipitates crystals by firing at 850 ° C. was added in an appropriate amount according to the use as a surface wiring conductor, a via conductor, and an internal wiring conductor. Further, as the organic vehicle, an appropriate amount of the one usually used in the paste was added so that the conductive paste had a viscosity suitable for screen printing. In addition, oxide powder was added to the conductor paste used as the surface wiring conductor to improve solder wettability and adhesive strength.
【００１５】−導体ペーストの調製− 表１及び表２に示すパラジウム比率となる導体ペースト
を、上記原材料を混合した後、三本ロールミルを通過さ
せることにより調製した。-Preparation of Conductor Paste-A conductor paste having a palladium ratio shown in Tables 1 and 2 was prepared by mixing the above raw materials and then passing through a three-roll mill.
【００１６】−セラミックス多層配線基板の製造− セラミックスグリーンシートは、アルミナ粉末とホウケ
イ酸亜鉛ガラスとを各々５０ｗｔ％ずつ混合したもの
に、有機バインダーとしてアクリル樹脂を加えてスラリ
ー化した後、ドクターブレード法などにより厚さ約０．
２ｍｍのシート状に成形した。このセラミックスグリー
ンシートに、ＮＣパンチング装置により孔径０．１５ｍ
ｍのヴィア用貫通孔を開け、該貫通孔に上記調製したヴ
ィア用導体ペーストを印刷により充填し、さらにその上
面に内部配線用の導体ペーストにより配線パターンを印
刷した。得られたセラミックスグリーンシートを複数枚
積層して熱圧着した後、４００°Ｃで脱バインダーし、
８５０°Ｃで焼成した。こうして形成したセラミックス
多層基板に、表面配線用の導体ペーストを印刷し、８５
０°Ｃで表面配線導体を焼付け、セラミックス多層配線
基板を作製した。さらに、このセラミックス多層配線基
板を、抵抗及び金の焼成を想定して、８５０°Ｃで３回
再焼成した。-Manufacture of Ceramics Multilayer Wiring Board- A ceramics green sheet is prepared by adding 50 wt% each of alumina powder and zinc borosilicate glass to an acrylic resin as an organic binder to form a slurry, and then using a doctor blade method. The thickness is about 0.
It was formed into a 2 mm sheet. This ceramic green sheet has a hole diameter of 0.15 m with an NC punching device.
m through holes for vias were opened, the through holes were filled with the above-prepared via conductor paste by printing, and a wiring pattern was printed on the upper surface of the via conductor paste for internal wiring. After laminating a plurality of obtained ceramic green sheets and thermocompression bonding, debinding at 400 ° C,
It was baked at 850 ° C. On the ceramic multilayer substrate thus formed, a conductor paste for surface wiring is printed,
The surface wiring conductor was baked at 0 ° C to produce a ceramic multilayer wiring board. Furthermore, this ceramic multilayer wiring board was re-fired three times at 850 ° C. assuming resistance and firing of gold.
【００１７】−セラミックス多層配線基板の評価− セラミックス多層配線基板の評価は、図１に示すような
配線パターンの基板を上記方法により作製し、テスター
にて導通を調べた。１基板の表裏にはそれぞれ９６ヵ所
の接続部があり、各実施例及び比較例毎に５０基板作製
し、それぞれ合計９，６００カ所の導通を調べた。ま
た、シート抵抗は、内部に０．２×２ｍｍの配線を形成
し、ヴィア導体で表面に引き出した試料を作製し、４端
子法で測定した。-Evaluation of Ceramics Multilayer Wiring Board- To evaluate the ceramics multilayer wiring board, a board having a wiring pattern as shown in FIG. 1 was prepared by the above method, and conduction was examined by a tester. There were 96 connecting portions on the front and back of each substrate, and 50 substrates were prepared for each of the examples and comparative examples, and a total of 9,600 conductive portions were examined. Further, the sheet resistance was measured by a four-terminal method by forming a wiring having a size of 0.2 × 2 mm inside and drawing a sample on the surface with a via conductor.
【００１８】−評価結果の説明− 本実施例及び比較例の評価結果を、表１及び表２に要約
した。-Explanation of Evaluation Results- The evaluation results of this example and comparative examples are summarized in Tables 1 and 2.
【００１９】[0019]
【表１】 [Table 1]
【表２】 [Table 2]
【００２０】表１では、内部配線導体のパラジウム比率
を２ｗｔ％に固定し、ヴィア導体のパラジウム比率を変
化させた時の結果である（但し、比較例１は従来例であ
り、内部配線導体のパラジウム比率は０ｗｔ％であ
る）。ヴィア導体のパラジウム比率が、表面配線導体の
パラジウム比率の１／５以上では、再焼成後においても
導通不良が発生していない。表２は、ヴィア導体のパラ
ジウム比率に対して内部配線導体のパラジウム比率を変
化させた時の結果である。やはり、内部配線導体のパラ
ジウム比率が、ヴィア導体のパラジウム比率の１／５以
上では、再焼成後においても導通不良が発生していな
い。また、表２から、内部配線のシート抵抗はパラジウ
ム比率が高くなるにつれて大きくなり、実用的な１０ｍ
Ω／□以下にシート抵抗にするには、内部配線導体のパ
ラジウム比率を５ｗｔ％以下とすることが良い。Table 1 shows the results when the palladium ratio of the internal wiring conductor was fixed to 2 wt% and the palladium ratio of the via conductor was changed (however, Comparative Example 1 is a conventional example, and the palladium ratio of the internal wiring conductor is Palladium ratio is 0 wt%). When the palladium ratio of the via conductor is ⅕ or more of the palladium ratio of the surface wiring conductor, no conduction failure occurs even after re-firing. Table 2 shows the results when the palladium ratio of the internal wiring conductor was changed with respect to the palladium ratio of the via conductor. After all, when the palladium ratio of the internal wiring conductor is ⅕ or more of the palladium ratio of the via conductor, the conduction failure does not occur even after the re-firing. Further, from Table 2, the sheet resistance of the internal wiring becomes larger as the palladium ratio becomes higher, and it is practically 10 m.
In order to reduce the sheet resistance to Ω / □ or less, it is preferable that the palladium ratio of the internal wiring conductor be 5 wt% or less.
【００２１】[0021]
【発明の効果】以上、説明した本発明にかかるセラミッ
クス多層配線基板によれば、内部配線とヴィア、及び表
面配線とヴィアの接続が確実なものとなり、導通不良の
生じにくいセラミックス多層配線基板を提供することが
できる。As described above, according to the ceramic multilayer wiring board according to the present invention described above, the internal wiring and the via and the surface wiring and the via are surely connected to each other, and a ceramic multilayer wiring board in which conduction failure is less likely to occur is provided. can do.
【図１】図１は、実施例及び比較例において作製したセ
ラミックス多層配線基板の縦断面の模式図であり、端子
ＡＢ間及び端子ＣＤ間の導通をテスターにて調べる。こ
れが１基板に表裏それぞれ９６ヵ所ある。FIG. 1 is a schematic view of a vertical cross section of a ceramic multilayer wiring board manufactured in Examples and Comparative Examples, in which continuity between terminals AB and terminals CD is examined with a tester. There are 96 front and back surfaces on one substrate.
Claims (1)
形成したセラミックス多層配線基板において、表面配線
導体として銀−パラジウム導体を用い、該表面配線導体
と接するヴィア導体には、上記表面配線導体のパラジウ
ム比率の１／５〜１／２のパラジウムを含む銀−パラジ
ウム導体を用い、さらにヴィア導体と接する内部配線導
体には、前記ヴィア導体のパラジウム比率の１／５以上
のパラジウムを含む銀−パラジウム導体を用いたことを
特徴とするセラミックス多層配線基板。1. A ceramic multilayer wiring substrate formed by laminating a plurality of low temperature fired ceramics, wherein a silver-palladium conductor is used as a surface wiring conductor, and the via conductor in contact with the surface wiring conductor is palladium of the surface wiring conductor. A silver-palladium conductor containing 1/5 to 1/2 of the ratio of palladium is used, and the internal wiring conductor in contact with the via conductor is a silver-palladium conductor containing palladium at 1/5 or more of the palladium ratio of the via conductor. A ceramic multilayer wiring board characterized by using.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11538193A JPH06302968A (en) | 1993-04-19 | 1993-04-19 | Multilayer interconnection ceramic board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11538193A JPH06302968A (en) | 1993-04-19 | 1993-04-19 | Multilayer interconnection ceramic board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06302968A true JPH06302968A (en) | 1994-10-28 |
Family
ID=14661128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11538193A Pending JPH06302968A (en) | 1993-04-19 | 1993-04-19 | Multilayer interconnection ceramic board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06302968A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000060613A1 (en) * | 1999-03-30 | 2000-10-12 | Matsushita Electric Industrial Co., Ltd. | Conductive paste, ceramic multilayer substrate, and method for manufacturing ceramic multilayer substrate |
| US6629367B2 (en) * | 2000-12-06 | 2003-10-07 | Motorola, Inc. | Electrically isolated via in a multilayer ceramic package |
| JP2006351671A (en) * | 2005-06-14 | 2006-12-28 | Alps Electric Co Ltd | Wiring board |
| JP2016004973A (en) * | 2014-06-19 | 2016-01-12 | 京セラ株式会社 | Wiring board, package and electronic apparatus |
-
1993
- 1993-04-19 JP JP11538193A patent/JPH06302968A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000060613A1 (en) * | 1999-03-30 | 2000-10-12 | Matsushita Electric Industrial Co., Ltd. | Conductive paste, ceramic multilayer substrate, and method for manufacturing ceramic multilayer substrate |
| US6629367B2 (en) * | 2000-12-06 | 2003-10-07 | Motorola, Inc. | Electrically isolated via in a multilayer ceramic package |
| JP2006351671A (en) * | 2005-06-14 | 2006-12-28 | Alps Electric Co Ltd | Wiring board |
| JP4613103B2 (en) * | 2005-06-14 | 2011-01-12 | アルプス電気株式会社 | Wiring board |
| JP2016004973A (en) * | 2014-06-19 | 2016-01-12 | 京セラ株式会社 | Wiring board, package and electronic apparatus |
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