JPH06291644A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPH06291644A JPH06291644A JP5080386A JP8038693A JPH06291644A JP H06291644 A JPH06291644 A JP H06291644A JP 5080386 A JP5080386 A JP 5080386A JP 8038693 A JP8038693 A JP 8038693A JP H06291644 A JPH06291644 A JP H06291644A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- voltage
- frequency divider
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims abstract description 14
- 238000010586 diagram Methods 0.000 description 6
- 230000035945 sensitivity Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、発振周波数に相応して
収束速度を変えるようにしたＰＬＬ（フェーズロックド
ループ）回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) circuit adapted to change a convergence speed according to an oscillation frequency.
【０００２】[0002]
【従来の技術】クリアビジョン（ＥＤＴＶ）等で、放送
されたカラーテレビ信号の水平同期信号に位相同期する
クロック信号を得るため、例えば、図４に示すＰＬＬ回
路（ブロック図）が使用される。３１は基準信号として
入力した、放送されたカラーテレビ信号の水平同期信号
４０とＶＣＯ（電圧制御発振器）３３が発振し出力する
クロック信号４１を分周器３４で分周して得られる帰還
信号（水平同期信号）４２とを位相比較し、両信号の位
相差に応じた信号を発生する位相比較器である。３２は
前記位相比較器３１から位相差に応じた信号が供給さ
れ、該信号に基づき直流電圧を生成する低域フィルタ
（ＬＰＦ）である。３３は、前記直流電圧に基づき、発
振周波数と位相を制御し、所望のクロック信号４１を生
成し出力する電圧制御発振（ＶＣＯ）器である。３４は
前記クロック信号４１を所定の比率（分周比）で分周
し、帰還信号４２を生成するカウンタ（分周器）であ
る。しかし、クリアビジョン（ＥＤＴＶ）等での利用に
おいては、入力する映像信号により、例えば、非標準の
映像信号を信号処理する場合、発振周波数を切り換える
必要があったが、上記した従来のＰＬＬ回路では、それ
ぞれ異なる周波数の出力信号を有するＰＬＬ回路が複数
個必要であった。2. Description of the Related Art In a clear vision (EDTV) or the like, for example, a PLL circuit (block diagram) shown in FIG. 4 is used in order to obtain a clock signal which is phase-synchronized with a horizontal synchronizing signal of a broadcast color television signal. Reference numeral 31 denotes a horizontal sync signal 40 of a broadcast color television signal input as a reference signal and a clock signal 41 oscillated and output by a VCO (voltage controlled oscillator) 33, which is obtained by frequency division by a frequency divider 34. (Horizontal synchronization signal) 42, and a phase comparator for generating a signal corresponding to the phase difference between the two signals. A low-pass filter (LPF) 32 is supplied with a signal corresponding to the phase difference from the phase comparator 31 and generates a DC voltage based on the signal. A voltage controlled oscillator (VCO) 33 controls the oscillation frequency and phase based on the DC voltage to generate and output a desired clock signal 41. Reference numeral 34 is a counter (frequency divider) that divides the clock signal 41 at a predetermined ratio (frequency division ratio) to generate a feedback signal 42. However, when used in clear vision (EDTV) or the like, it is necessary to switch the oscillation frequency when the non-standard video signal is processed by the input video signal. However, in the conventional PLL circuit described above, A plurality of PLL circuits having output signals of different frequencies are required.
【０００３】[0003]
【発明が解決しようとする課題】本発明は上記問題点に
鑑みなされたもので、複数の発振周波数を備えるととも
に、それぞれの発振周波数において、最適の収束特性と
周波数安定性を備えたＰＬＬ回路を提供することを目的
とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems and provides a PLL circuit having a plurality of oscillation frequencies and having optimum convergence characteristics and frequency stability at each oscillation frequency. The purpose is to provide.
【０００４】[0004]
【課題を解決するための手段】上記目的を達成するため
に、入力する信号間の位相差を検出し該位相差に応じた
信号を出力する位相比較部と、前記位相比較部が出力す
る信号を入力し直流電圧に変換するとともに制御信号に
基づき伝達特性を変化させる低域フィルタと、前記低域
フィルタに縦続接続するとともに前記直流電圧により制
御され所定の周波数の信号を発生し該信号を出力する電
圧制御発振部と、前記電圧制御発振部の出力信号を分周
する第一の分周器と、前記第一の分周器の出力を分周す
るとともに前記位相比較部に帰還接続する第二の分周器
とからなる。In order to achieve the above object, a phase comparator for detecting a phase difference between input signals and outputting a signal corresponding to the phase difference, and a signal output by the phase comparator. Is input and converted into a DC voltage, and a low-pass filter that changes the transfer characteristic based on a control signal; and a low-pass filter that is cascade-connected to the low-pass filter and that generates a signal of a predetermined frequency controlled by the DC voltage and outputs the signal. A voltage controlled oscillator, a first frequency divider that divides the output signal of the voltage controlled oscillator, and a frequency divider that divides the output of the first frequency divider and feeds back to the phase comparator. It consists of two frequency dividers.
【０００５】[0005]
【作用】以上のように構成したので、周波数選択信号の
指示に基づき電圧制御発振部の発振周波数を変えるとと
もに、第一の分周器ならびに第二の分周器は所定の周波
数の信号を得るように、予め記憶している分周比が設定
され。また、前記指示に基づく出力信号の周波数（発振
周波数）に応じ、第一の分周器で分周され所定の周波数
に生成された制御信号を低域フィルタに供給する。前記
低域フィルタは、遮断周波数を始めとし伝達特性を変化
させる。その結果ＰＬＬ回路はループ感度を変化させ、
周波数ロックの収束時間を短くする。With the above configuration, the oscillation frequency of the voltage controlled oscillator is changed based on the instruction of the frequency selection signal, and the first frequency divider and the second frequency divider obtain a signal of a predetermined frequency. Thus, the frequency division ratio stored in advance is set. Further, the control signal generated by the first frequency divider at a predetermined frequency according to the frequency (oscillation frequency) of the output signal based on the instruction is supplied to the low-pass filter. The low-pass filter changes the transfer characteristic including the cutoff frequency. As a result, the PLL circuit changes the loop sensitivity,
Shorten the convergence time of frequency lock.
【０００６】[0006]
【実施例】以下、本発明によるＰＬＬ回路について、図
を用いて詳細に説明する。図１は、本発明によるＰＬＬ
回路の実施例ブロック図である。１は入力信号１０と帰
還信号１２間の位相差を検出し、該位相差に応じた信号
を出力する位相比較器である。２は、前記位相差に応じ
た信号を入力し、直流電圧に変換し出力するとともに、
第一の分周器で分周された所定の周波数（クロック）信
号に基づき伝達特性を変化させる、例えば、スイッチト
キャパシタフィルタでなる低域フィルタ（ＬＰＦ）であ
る。３は、前記低域フィルタ２に縦続接続するととも
に、低域フィルタ２が供給する直流電圧により制御され
るとともに、周波数選択信号１５に基づき所定の出力
（クロック）信号１１を発生する電圧制御発振器（ＶＣ
Ｏ）である。４は、前記電圧制御発振部３の出力信号を
分周するとともに、該分周出力信号を前記低域フィルタ
２および第二の分周器５とに供給し、周波数選択信号１
５に基づき分周比を変化させる第一の分周器である。５
は、前記第一の分周器出力信号を入力して分周し、所定
の周波数の帰還信号１２を生成するとともに、周波数選
択信号１５に基づき分周比を変化させる第二の分周器で
ある。DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a PLL according to the present invention.
It is an example block diagram of a circuit. Reference numeral 1 is a phase comparator which detects a phase difference between the input signal 10 and the feedback signal 12 and outputs a signal corresponding to the phase difference. 2 inputs a signal corresponding to the phase difference, converts it into a DC voltage and outputs it, and
It is a low pass filter (LPF) which is a switched capacitor filter, for example, which changes the transfer characteristic based on a predetermined frequency (clock) signal divided by the first frequency divider. 3 is a voltage-controlled oscillator (3) that is connected in cascade to the low-pass filter 2 and is controlled by a DC voltage supplied from the low-pass filter 2 and that generates a predetermined output (clock) signal 11 based on a frequency selection signal 15. VC
O). Reference numeral 4 divides the output signal of the voltage controlled oscillator 3 and supplies the divided output signal to the low-pass filter 2 and the second frequency divider 5 for frequency selection signal 1
It is a first frequency divider that changes the frequency division ratio based on 5. 5
Is a second frequency divider that inputs the first frequency divider output signal and divides the frequency to generate a feedback signal 12 having a predetermined frequency, and changes the frequency division ratio based on the frequency selection signal 15. is there.
【０００７】図２は、本発明によるＰＬＬ回路の制御信
号に基づき特性を変化させる低域フィルタの実施例であ
る。２０は位相比較器１の位相差に応じた出力２１を入
力するとともに、電気容量がＣであり、制御信号２３に
より内部スイッチを切り換えるスイッチトキャパシタで
ある。２６は、前記スイッチトキャパシタの等価抵抗に
より、伝達特性を変化させ、直流電圧出力２２を供給す
る低域フィルタを構成したスイッチトキャパシタフィル
タである。尚、スイッチトキャパシタの等価抵抗値ｒ
は、制御信号２３の周波数をｆ、キャパシタンスをＣと
すると、ｒ＝１／（ｆ×Ｃ）である。FIG. 2 shows an embodiment of a low-pass filter whose characteristics are changed based on the control signal of the PLL circuit according to the present invention. Reference numeral 20 is a switched capacitor which receives an output 21 corresponding to the phase difference of the phase comparator 1, has an electric capacity of C, and switches an internal switch by a control signal 23. Reference numeral 26 is a switched capacitor filter that constitutes a low-pass filter that changes the transfer characteristic by the equivalent resistance of the switched capacitor and supplies the DC voltage output 22. The equivalent resistance value r of the switched capacitor
Is r = 1 / (f × C) where f is the frequency of the control signal 23 and C is the capacitance.
【０００８】本発明によるＰＬＬ回路の動作を説明す
る。図３は、本発明によるＰＬＬ回路において、第一の
分周器で分周したクロック信号出力に応じたＰＬＬ回路
の各部の特性の変化を示す図である。図（イ）は、分周
したクロック信号出力に対するスイッチトキャパシタの
等価抵抗値を示すグラフである。２８は出力（クロッ
ク）信号１１を第一の分周器で分周したクロック信号の
周波数を高くするほど等価抵抗値が小さくなる反比例の
特性を表す線である。例えば、前記クロック信号の周波
数が高くなると、Ａ点は反比例の特性を表す線２８の上
を右下に進み、スイッチトキャパシタ２０の等価抵抗値
は小さくなることを示す。図（ロ）は、上記スイッチト
キャパシタ２０の等価抵抗値変化に起因した収束速度の
特性を示すグラフである。２９はクロック信号の周波数
を変えた結果、上記したように、スイッチトキャパシタ
２０の等価抵抗値が変化し、それに対し、低域フィルタ
の伝達特性が変化した結果得られる比例の特性を表す線
である。例えば、クロック信号の周波数が高くなると、
Ｂ点は比例の特性を表す線２９の上を右上に進み、ＰＬ
Ｌ感度が大きくなることを示す。従って、スイッチトキ
ャパシタに供給される制御信号周波数（第一の分周器で
分周したクロック信号の周波数）を高くすると、収束速
度が大きくなり、その結果、ＰＬＬロックに要する収束
時間が短くなるように動作する。尚、制御信号に基づき
電圧制御発振器３が発振周波数を変え、該発振周波数を
制御信号に基づき所定の分周比が与えられたプログラマ
ブルな第一の分周器４で分周して低域フィルタ２に供給
するとともに、制御信号に基づき所定の分周比が与えら
れたプログラマブルな第二の分周器５で分周して位相比
較器１に帰還することにより、複数の発振周波数１１を
発生するＰＬＬ回路であっても良い。The operation of the PLL circuit according to the present invention will be described. FIG. 3 is a diagram showing changes in the characteristics of each part of the PLL circuit according to the clock signal output divided by the first frequency divider in the PLL circuit according to the present invention. FIG. 4A is a graph showing the equivalent resistance value of the switched capacitor with respect to the divided clock signal output. Reference numeral 28 is a line representing an inverse proportional characteristic in which the equivalent resistance value becomes smaller as the frequency of the clock signal obtained by dividing the output (clock) signal 11 by the first frequency divider becomes higher. For example, as the frequency of the clock signal increases, the point A advances to the lower right on the line 28 representing the inversely proportional characteristic, and the equivalent resistance value of the switched capacitor 20 decreases. FIG. 6B is a graph showing the characteristic of the convergence speed due to the change in the equivalent resistance value of the switched capacitor 20. Reference numeral 29 is a line representing a proportional characteristic obtained as a result of a change in the equivalent resistance value of the switched capacitor 20 and a change in the transfer characteristic of the low-pass filter as a result of changing the frequency of the clock signal as described above. . For example, if the frequency of the clock signal increases,
Point B moves to the upper right on the line 29 showing the proportional characteristic, and PL
It shows that the L sensitivity increases. Therefore, if the frequency of the control signal supplied to the switched capacitor (the frequency of the clock signal divided by the first divider) is increased, the convergence speed is increased, and as a result, the convergence time required for the PLL lock is shortened. To work. The voltage controlled oscillator 3 changes the oscillation frequency based on the control signal, and the oscillation frequency is divided by the programmable first frequency divider 4 to which a predetermined frequency division ratio is given based on the control signal to perform the low pass filter. A plurality of oscillating frequencies 11 are generated by feeding the signal to the second frequency divider 2 and dividing the frequency by the programmable second frequency divider 5 to which a predetermined frequency dividing ratio is given based on the control signal and feeding it back to the phase comparator 1. It may be a PLL circuit that operates.
【０００９】[0009]
【発明の効果】以上説明したように、本発明は複数の発
振周波数を備えるとともに、それぞれの発振周波数にお
いて、所望の収束特性と周波数安定性を得られるＰＬＬ
回路を提供する。従って、クリアビジョンなどで、入力
する各種の、例えば、非標準あるいは標準の水平同期信
号に位相同期するクロック信号を、所望の収束特性と周
波数安定性にて供給することができる。また、電圧制御
発振部の発振周波数に応じ、分周比を変えることによ
り、所定の周波数の帰還信号を生成することができる。As described above, the present invention has a plurality of oscillation frequencies, and at each oscillation frequency, a PLL capable of obtaining desired convergence characteristics and frequency stability.
Provide the circuit. Therefore, in clear vision or the like, it is possible to supply various input clock signals, for example, a clock signal that is phase-locked with a non-standard or standard horizontal synchronization signal with desired convergence characteristics and frequency stability. Also, by changing the frequency division ratio according to the oscillation frequency of the voltage controlled oscillator, it is possible to generate a feedback signal of a predetermined frequency.
【図１】本発明によるＰＬＬ回路の実施例ブロック図で
ある。FIG. 1 is a block diagram of an embodiment of a PLL circuit according to the present invention.
【図２】本発明によるＰＬＬ回路の制御信号に基づき特
性を変化させる低域フィルタの実施例である。FIG. 2 is an embodiment of a low-pass filter whose characteristics are changed based on a control signal of a PLL circuit according to the present invention.
【図３】本発明によるＰＬＬ回路において、第一の分周
器で分周したクロック信号出力に応じたＰＬＬ回路の各
部の特性の変化を示す図である。FIG. 3 is a diagram showing changes in characteristics of each part of the PLL circuit according to the clock signal output divided by the first divider in the PLL circuit according to the present invention.
【図４】従来のＰＬＬ回路の実施例ブロック図である。FIG. 4 is a block diagram of an embodiment of a conventional PLL circuit.
１ 位相比較器 ２ 低域フィルタ ３ 電圧制御発振器 ４ 第一の分周器 ５ 第二の分周器 １０ 入力信号 １１ 出力（クロック）信号 １２ 帰還信号 １５ 周波数選択信号 ２０ スイッチトキャパシタ ２１ 位相差に応じた出力 ２２ 直流電圧出力 ２３ 制御信号 ２６ スイッチトキャパシタフィルタ（低域フィルタ） ２８ 反比例の特性を表す線 ２９ 比例の特性を表す線 ３１ 位相比較器 ３２ 低域フィルタ ３３ 電圧制御発振器 ３４ 分周器 ４０ 入力信号 ４１ 出力（クロック）信号 ４２ 帰還信号 1 phase comparator 2 low-pass filter 3 voltage controlled oscillator 4 first frequency divider 5 second frequency divider 10 input signal 11 output (clock) signal 12 feedback signal 15 frequency selection signal 20 switched capacitor 21 depending on phase difference Output 22 DC voltage output 23 Control signal 26 Switched capacitor filter (low-pass filter) 28 Line showing inverse proportional characteristics 29 Line showing proportional characteristics 31 Phase comparator 32 Low-pass filter 33 Voltage controlled oscillator 34 Divider 40 Input Signal 41 Output (clock) signal 42 Feedback signal
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 9182−5Ｊ Ｈ０３Ｌ 7/10 Ｃ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location 9182-5J H03L 7/10 C
Claims (3)
差に応じた信号を出力する位相比較部と、前記位相比較
部が出力する信号を入力し直流電圧に変換するとともに
制御信号に基づき伝達特性を変化させる低域フィルタ
と、前記低域フィルタに縦続接続するとともに前記直流
電圧により制御され所定の周波数の信号を発生し該信号
を出力する電圧制御発振部と、前記電圧制御発振部の出
力信号を分周する第一の分周器と、前記第一の分周器の
出力を分周するとともに前記位相比較部に帰還接続する
第二の分周器とからなるＰＬＬ回路において、 前記第一の分周器の出力に基づき遮断周波数等を変える
低域フィルタの特性に依存して収束速度を変えることを
特徴とするＰＬＬ回路。1. A phase comparison unit that detects a phase difference between input signals and outputs a signal corresponding to the phase difference, and a signal output by the phase comparison unit that is input and converted into a DC voltage and used as a control signal. A low-pass filter for changing the transfer characteristic based on the voltage, a voltage-controlled oscillator connected in series with the low-pass filter, generating a signal of a predetermined frequency controlled by the DC voltage, and outputting the signal, and the voltage-controlled oscillator. In a PLL circuit comprising a first frequency divider that divides the output signal of, and a second frequency divider that divides the output of the first frequency divider and that is feedback-connected to the phase comparison unit, A PLL circuit characterized in that the convergence speed is changed depending on the characteristics of a low-pass filter that changes the cutoff frequency based on the output of the first frequency divider.
差に応じた信号を出力する位相比較部と、前記位相比較
部が出力する信号を入力し直流電圧に変換するとともに
制御信号に基づき伝達特性を変化させる低域フィルタ
と、前記低域フィルタに縦続接続するとともに前記直流
電圧により制御され所定の周波数の信号を発生し該信号
を出力する電圧制御発振部と、前記電圧制御発振部の出
力信号を分周する第一の分周器と、前記第一の分周器の
出力を分周するとともに前記位相比較部に帰還接続する
第二の分周器とからなるＰＬＬ回路において、 制御信号に基づき発振周波数を変える電圧制御発振部
と、制御信号に基づき分周比を変えるプログラマブルな
第一の分周器と、制御信号に基づき分周比を変えるプロ
グラマブルな第二の分周器とでなるＰＬＬ回路。2. A phase comparison unit that detects a phase difference between input signals and outputs a signal corresponding to the phase difference, and a signal output from the phase comparison unit that is input and converted into a DC voltage and used as a control signal. A low-pass filter for changing the transfer characteristic based on the voltage, a voltage-controlled oscillator connected in series with the low-pass filter, generating a signal of a predetermined frequency controlled by the DC voltage, and outputting the signal, and the voltage-controlled oscillator. In a PLL circuit comprising a first frequency divider that divides the output signal of, and a second frequency divider that divides the output of the first frequency divider and that is feedback-connected to the phase comparison unit, A voltage-controlled oscillator that changes the oscillation frequency based on a control signal, a programmable first frequency divider that changes the frequency division ratio based on the control signal, and a programmable second frequency divider that changes the frequency division ratio based on the control signal. And with PLL circuit that.
シタフィルタでなる請求項１記載のＰＬＬ回路。3. The PLL circuit according to claim 1, wherein the low-pass filter is a switched capacitor filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5080386A JPH06291644A (en) | 1993-04-07 | 1993-04-07 | Pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5080386A JPH06291644A (en) | 1993-04-07 | 1993-04-07 | Pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06291644A true JPH06291644A (en) | 1994-10-18 |
Family
ID=13716856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5080386A Pending JPH06291644A (en) | 1993-04-07 | 1993-04-07 | Pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06291644A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001026230A1 (en) * | 1999-10-01 | 2001-04-12 | Ericsson Inc. | Pll loop filter with switched-capacitor resistor |
| FR2834831A1 (en) * | 2002-01-11 | 2003-07-18 | Zarlink Semiconductor Inc | ANALOGUE PHASE LOCKING LOOP WITH SWITCHED CAPACITY RE-SAMPLING FILTER |
| CN107306125A (en) * | 2016-04-21 | 2017-10-31 | 佳能株式会社 | Signal generating circuit and signal creating method |
| CN110031123A (en) * | 2018-01-04 | 2019-07-19 | 联发科技股份有限公司 | Heat sensor integrated circuit and resistor for heat sensor |
-
1993
- 1993-04-07 JP JP5080386A patent/JPH06291644A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001026230A1 (en) * | 1999-10-01 | 2001-04-12 | Ericsson Inc. | Pll loop filter with switched-capacitor resistor |
| JP2003517755A (en) * | 1999-10-01 | 2003-05-27 | エリクソン インコーポレイテッド | PLL loop filter using switched capacitor resistor |
| FR2834831A1 (en) * | 2002-01-11 | 2003-07-18 | Zarlink Semiconductor Inc | ANALOGUE PHASE LOCKING LOOP WITH SWITCHED CAPACITY RE-SAMPLING FILTER |
| CN107306125A (en) * | 2016-04-21 | 2017-10-31 | 佳能株式会社 | Signal generating circuit and signal creating method |
| CN110031123A (en) * | 2018-01-04 | 2019-07-19 | 联发科技股份有限公司 | Heat sensor integrated circuit and resistor for heat sensor |
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