JPH06244307A - Manufacture of low temperature firing multilayered ceramic circuit board - Google Patents
Manufacture of low temperature firing multilayered ceramic circuit boardInfo
- Publication number
- JPH06244307A JPH06244307A JP50A JP5141493A JPH06244307A JP H06244307 A JPH06244307 A JP H06244307A JP 50 A JP50 A JP 50A JP 5141493 A JP5141493 A JP 5141493A JP H06244307 A JPH06244307 A JP H06244307A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- circuit board
- low temperature
- ceramic circuit
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、低温焼成多層セラミッ
ク回路基板の製造方法に関し、特に半導体ベアチップ実
装用の凹部を有し、配線導体にＣｕを用いた低温焼成多
層セラミック回路基板に、半導体ベアチップを実装する
ためのＡｕ電極を容易に形成させることができる低温焼
成多層セラミック回路基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a low temperature fired multilayer ceramic circuit board, and more particularly to a low temperature fired multilayer ceramic circuit board having a recess for mounting a semiconductor bare chip and using Cu for a wiring conductor. The present invention relates to a method for manufacturing a low temperature fired multilayer ceramic circuit board capable of easily forming an Au electrode for mounting.
【０００２】[0002]
【従来の技術】Ａｕ導体は、高信頼性を要する配線導体
又は端子電極として従来より多用されている。特に、Ａ
ｕ導体は、半導体ベアチップをワイヤ−ボンディング実
装するときのＡｕワイヤ−電極や半導体ベアチップをフ
リップチップ実装するときのバンプ電極などに用いられ
ている。2. Description of the Related Art Au conductors have been widely used as wiring conductors or terminal electrodes which require high reliability. In particular, A
The u conductor is used as an Au wire electrode when the semiconductor bare chip is wire-bonded and a bump electrode when the semiconductor bare chip is flip-chip mounted.
【０００３】ところで、ASICやMPUなどに代表されるLSI
（大規模集積回路）の多ピン化・高速化に伴い、そのLS
Iベアチップを多層セラミック回路基板に形成した凹部
に実装し、Ａｕワイヤ−により凹部に設けた電極パッド
に接続し、続いて、凹部内を封止樹脂で充填するか、も
しくは凹部上面をガラス等によって気密封止する方法で
作製された、高性能で、しかも信頼性が高い多層セラミ
ック回路基板が開発されている。By the way, LSI represented by ASIC, MPU, etc.
With the increase in pin count and speed of (large-scale integrated circuits), its LS
I The bare chip is mounted in the recess formed on the multilayer ceramic circuit board, and the Au wire is used to connect to the electrode pad provided in the recess. Then, the inside of the recess is filled with sealing resin, or the upper surface of the recess is made of glass or the like. A high-performance and highly reliable multilayer ceramic circuit board manufactured by a hermetically sealing method has been developed.
【０００４】それら多層セラミック回路基板の製造方法
の１つとして、低温焼成材料を用いたセラミックグリ−
ンシ−トに、該シ−ト層間の接続を図るためのバイアホ
−ル及び半導体ベアチップ実装用の凹部を形成するため
の開口部をパンチング等により形成した後、半導体ベア
チップ実装用電極パッド部のみＡｕ導体ペ−ストを印刷
し、それ以外の配線導体部にはＣｕ導体ペ−ストを印刷
することにより所定の配線パタ−ンを形成し、それらグ
リ−ンシ−トを積層、プレス、焼成することにより、半
導体ベアチップ実装用凹部を有する低温焼成多層セラミ
ック回路基板を製造する方法が知られている。As one of the manufacturing methods for those multilayer ceramic circuit boards, ceramic green using a low temperature firing material is used.
After forming a via hole for connecting the sheet layers and an opening for forming a recess for mounting a semiconductor bare chip in the sheet by punching or the like, only the electrode pad for mounting the semiconductor bare chip is Au. A conductor pattern is printed, and a Cu conductor paste is printed on the other wiring conductor portions to form a predetermined wiring pattern, and the green sheets are laminated, pressed and fired. A method for manufacturing a low temperature fired multilayer ceramic circuit board having a recess for mounting a semiconductor bare chip is known.
【０００５】[0005]
【発明が解決しようとする課題】ところで、多層セラミ
ック回路基板に使用する配線導体としては、基板配線密
度の高集積化による配線パタ−ンの微細化及び信号の高
速化などの要求を満足させるようにするため、導体抵抗
が低いＣｕを使用することが好ましい。これに対して、
半導体ベアチップを実装するための電極パッドとして
は、前記したように、接続信頼性やボンディング歩留り
等を考慮するとＡｕ導体で形成する必要がある。また、
基板材料には、配線導体にＣｕ及びＡｕを使用すること
から、これらの導体の融点以下（Ｃｕの融点：1084℃、
Ａｕの融点：1063℃）で焼成可能な低温焼成基板材料
（例えばアルミナ−ガラスなど）を用いる必要がある。By the way, as a wiring conductor used for a multilayer ceramic circuit board, it is necessary to satisfy the demands such as miniaturization of wiring pattern and high speed of signal due to high integration of board wiring density. Therefore, it is preferable to use Cu having a low conductor resistance. On the contrary,
As described above, the electrode pad for mounting the semiconductor bare chip needs to be formed of an Au conductor in consideration of connection reliability, bonding yield, and the like. Also,
Since Cu and Au are used for the wiring material as the substrate material, the melting point of these conductors or lower (Cu melting point: 1084 ° C.,
It is necessary to use a low temperature firing substrate material (for example, alumina-glass) capable of firing at a melting point of Au: 1063 ° C.
【０００６】従来法では、低温焼成多層セラミック回路
基板に形成した凹部に半導体ベアチップを実装するため
のＡｕ電極を形成するには、前記したとおり、該当する
セラミックグリ−ンシ−ト上にＡｕ導体ペ−スト及びＣ
ｕ導体ペ−ストを各々スクリ−ン印刷にてパタ−ン形成
しなければならず、そのため工程数及びスクリ−ン刷版
の増加が必要となるばかりでなく、スクリ−ン印刷によ
るＡｕペ−ストのロス分を含めた材料費の増加につなが
る等の問題を抱えている。According to the conventional method, in order to form an Au electrode for mounting a semiconductor bare chip in a recess formed in a low temperature fired multilayer ceramic circuit board, as described above, an Au conductor pattern is formed on the corresponding ceramic green sheet. -Strike and C
Each of the u conductor pastes must be patterned by screen printing, which requires not only an increase in the number of steps and the screen printing plate, but also an Au paste by screen printing. There are problems such as an increase in material costs including the loss of strike.
【０００７】本発明は、従来の上記問題点を解消し、よ
り簡易な工程で、しかも低コストで半導体ベアチップ実
装用Ａｕ電極を形成することができる低温焼成多層セラ
ミック回路基板の製造方法を提供することを目的とす
る。The present invention provides a method for manufacturing a low temperature fired multilayer ceramic circuit board which solves the above-mentioned problems of the prior art and which can form an Au electrode for mounting a semiconductor bare chip in a simpler process and at a lower cost. The purpose is to
【０００８】[0008]
【課題を解決するための手段】そして、本発明は、半導
体ベアチップ実装用Ａｕ電極を無電解Ａｕめっきにより
形成することを特徴とし、これにより上記Ａｕ電極をよ
り簡易な工程で、しかも低コストで形成することができ
るものである。即ち、本発明は、「半導体ベアチップ実
装用の凹部を有し、且つ配線導体にＣｕを用いた低温焼
成多層セラミック回路基板において、半導体ベアチップ
と電気的接続を図るための電極パッドを、該基板の凹部
に露出されたＣｕ導体表面に無電解Ａｕめっきを施すこ
とによって形成することを特徴とする低温焼成多層セラ
ミック回路基板の製造方法。」を要旨とする。The present invention is characterized in that a semiconductor bare chip mounting Au electrode is formed by electroless Au plating, whereby the Au electrode can be manufactured in a simpler process and at a lower cost. It can be formed. That is, the present invention provides, in a low temperature fired multilayer ceramic circuit board having a recess for mounting a semiconductor bare chip and using Cu for a wiring conductor, an electrode pad for electrical connection with the semiconductor bare chip is provided on the board. The method for producing a low temperature fired multilayer ceramic circuit board is characterized in that the Cu conductor surface exposed in the recess is formed by electroless Au plating. "
【０００９】以下、本発明を詳細に説明すると、本発明
者等は、低温焼成多層セラミック回路基板に形成した凹
部に、半導体ベアチップを実装するためのＡｕ電極をよ
り簡易な工程で形成する方法について、鋭意研究を重ね
た結果、半導体ベアチップ実装用電極を含めた全ての配
線パタ−ンにＣｕ導体ペ−ストを用いてスクリ−ン印刷
し、焼成後該基板の凹部に露出されたＣｕ導体表面に無
電解Ａｕめっきを施す方法が最適であることを見出し、
本発明を完成させたものである。The present invention will be described in detail below. The present inventors will describe a method of forming an Au electrode for mounting a semiconductor bare chip in a recess formed in a low temperature fired multilayer ceramic circuit board in a simpler process. As a result of intensive studies, a Cu conductor paste was used for screen printing on all wiring patterns including the electrodes for mounting the semiconductor bare chip, and the Cu conductor surface exposed in the recesses of the substrate after firing was printed. Found that the method of applying electroless Au plating to the
The present invention has been completed.
【００１０】即ち、本発明は、具体的には、(1) 低温焼
成材料を用いたセラミックグリ−ンシ−トに、このシ−
ト層間の電気的接続を図るためのバイアホ−ル及び半導
体ベアチップ実装用の凹部を形成するための開口部をパ
ンチング等により形成し、(2) 更に厚膜Ｃｕペ−ストを
用いて所定の配線パタ−ンをスクリ−ン印刷し、(3) そ
れらセラミックグリ−ンシ−トを積層し、プレスし、
(4) 非酸化雰囲気において750〜950℃で焼成し、(5) そ
の後基板の凹部に露出されたＣｕ導体表面に無電解Ａｕ
めっき液を用いてＡｕめっきする、ことを特徴とする低
温焼成多層セラミック回路基板の製造方法である。That is, the present invention specifically provides (1) a ceramic green sheet using a low temperature firing material,
A via hole for electrical connection between the printed circuit board and an opening for forming a recess for mounting a semiconductor bare chip is formed by punching or the like, and (2) predetermined wiring is formed using a thick film Cu paste. Screen-print the pattern, (3) stack those ceramic green sheets, press,
(4) Baking at 750 to 950 ° C. in a non-oxidizing atmosphere, (5) After that, electroless Au is formed on the Cu conductor surface exposed in the recess of the substrate.
A method for producing a low-temperature fired multilayer ceramic circuit board is characterized in that Au plating is performed using a plating solution.
【００１１】本発明において、セラミックグリ−ンシ−
ト及び厚膜Ｃｕペ−ストは、基板焼成時における内部及
び露出されたＣｕ導体の酸化が進まない非酸化雰囲気で
焼成可能な材料にて構成する必要がある。特に、グリ−
ンシ−ト化及びペ−スト化する際に必要な有機バインダ
−には、熱分解可能な材料（例えばアクリル系樹脂等）
を用いるのが好ましい。In the present invention, a ceramic green seal
The thick and thick film Cu paste must be made of a material that can be baked in a non-oxidizing atmosphere in which the oxidation of the Cu conductor exposed inside and the exposed Cu conductor does not proceed. In particular, green
A thermally decomposable material (for example, an acrylic resin) is used as the organic binder necessary for forming the sheet and forming the paste.
Is preferably used.
【００１２】また、半導体ベアチップを実装するための
凹部を有するセラミック多層基板を形成する手段として
は、凹部に対応する凸部を有する金型に各層のグリ−ン
シ−トを順次積層し、熱プレスを行うことにより所定形
状の積層基板を得ることができる。積層された基板を焼
成するには、開放型ベルト焼成炉又は密閉型焼成炉のい
ずれかを用い、酸素濃度が100ｐｐｍ以下に調整された
窒素ガス中で、ピ−ク温度750〜950℃の範囲内に30〜12
0分間保持し、且つ全工程が2〜10時間となるプロファイ
ルで焼成を行う。ここで焼成雰囲気ガス中の酸素濃度が
100ｐｐｍ以上では、Ｃｕ導体の酸化が進み、導体抵抗
の増加や後工程におけるＡｕめっき不良などの問題が生
じる恐れがあるので、好ましくない。As a means for forming a ceramic multilayer substrate having a recess for mounting a semiconductor bare chip, the green sheet of each layer is sequentially laminated on a mold having a protrusion corresponding to the recess, and hot pressing is performed. By performing the above, a laminated substrate having a predetermined shape can be obtained. To fire the laminated substrates, use either an open belt firing furnace or a closed firing furnace, in a nitrogen gas whose oxygen concentration is adjusted to 100 ppm or less, and a peak temperature range of 750 to 950 ° C. Within 30 to 12
Hold for 0 minutes, and perform firing with a profile such that all steps are 2 to 10 hours. Here, the oxygen concentration in the firing atmosphere gas
If it is 100 ppm or more, oxidation of the Cu conductor proceeds, which may cause problems such as an increase in conductor resistance and defective Au plating in a subsequent process, which is not preferable.
【００１３】上記方法によって形成された低温焼成多層
セラミック回路基板において、該基板の凹部に露出され
たＣｕ導体表面に無電解Ａｕめっきを施すことを本発明
の特徴とするものである。即ち、本発明は、基板の凹部
に露出されたＣｕ導体を無電解Ａｕめっき液中に浸漬す
ることにより、Ｃｕ導体表面に容易にＡｕめっきを施す
ことができる。In the low temperature fired multilayer ceramic circuit board formed by the above method, the feature of the present invention is to subject the surface of the Cu conductor exposed in the recess of the board to electroless Au plating. That is, according to the present invention, the Cu conductor exposed in the concave portion of the substrate is immersed in the electroless Au plating solution, whereby the surface of the Cu conductor can be easily plated with Au.
【００１４】Ａｕめっきに用いる無電解Ａｕめっき液と
しては、ＡｕイオンのＣｕとの置換反応によって形成す
るＡｕめっき可能な液であり、該めっき液の水素イオン
濃度はｐＨ＝4〜8の範囲内であることが必要である。こ
の理由として、無電解Ａｕめっき液は、基板表面に露出
されたポ−ラスなＣｕ導体中へ浸透する。従って、上記
ｐＨ範囲外の強酸又は強アルカリ性を示す無電解Ａｕめ
っき液でめっきを行った場合、セラミック配線基板と厚
膜Ｃｕ導体との接着を保持しているガラス成分が侵さ
れ、Ｃｕ導体の接着強度が劣化することとなるので、好
ましくない。The electroless Au plating solution used for Au plating is an Au-platable solution formed by the substitution reaction of Au ions with Cu, and the hydrogen ion concentration of the plating solution is in the range of pH = 4-8. It is necessary to be. The reason for this is that the electroless Au plating solution penetrates into the porous Cu conductor exposed on the substrate surface. Therefore, when plating is performed with an electroless Au plating solution exhibiting strong acid or strong alkalinity outside the above pH range, the glass component holding the adhesion between the ceramic wiring board and the thick film Cu conductor is attacked, and the Cu conductor It is not preferable because the adhesive strength is deteriorated.
【００１５】本発明において、無電解Ａｕめっき液のｐ
Ｈ調整はクエン酸又はアンモニア水によって行うのが好
ましい。また、Ａｕの析出条件、析出速度としては、Ａ
ｕ濃度2〜4ｇ／ｌのめっき液を用い、液温90±5℃で約
0.01μｍ／分で行うのが好ましい。In the present invention, p of electroless Au plating solution is used.
The H adjustment is preferably performed with citric acid or aqueous ammonia. The Au deposition conditions and deposition rates are as follows:
Approximately at a liquid temperature of 90 ± 5 ℃ using a plating solution with a u concentration of 2-4g / l.
It is preferably performed at 0.01 μm / min.
【００１６】[0016]
【実施例】以下、本発明の実施例を挙げ、本発明をより
詳細に説明する。 (1) 基板の製造例 まず、アルミノホウケイ酸塩系ガラスを主成分とし、有
機バインダ−としてアクリル系樹脂を用いたセラミック
グリ−ンシ−ト（日本セメント社製）をドクタ−ブレ−
ド法により作製した。このグリ−ンシ−トを一定の大き
さに裁断し、続いて、このシ−ト層間の接続を図るため
のバイアホ−ル及び半導体ベアチップ実装用の凹部を形
成するための開口部を該グリ−ンシ−トの所定箇所にパ
ンチングによって形成した。EXAMPLES The present invention will be described in more detail below with reference to examples of the present invention. (1) Substrate manufacturing example First, a ceramic green sheet (manufactured by Nippon Cement Co., Ltd.) containing an aluminoborosilicate glass as a main component and an acrylic resin as an organic binder was doctor-blended.
It was manufactured by the de method. This green sheet is cut into a certain size, and subsequently, a via hole for connecting the sheet layers and an opening for forming a recess for mounting a semiconductor bare chip are formed on the green sheet. It was formed by punching at a predetermined position on the sheet.
【００１７】スル−ホ−ル充填用Ｃｕペ−スト（日本セ
メント社製）及び配線用Ｃｕペ−スト（日本セメント社
製）を所定のグリ−ンシ−トにスクリ−ン印刷し、75℃
で10分間乾燥した後、半導体ベアチップ実装用凹部に対
応する凸部を有する金型に各層のグリ−ンシ−トを順次
積層し、熱プレスにより一体化した。得られた積層体を
酸素濃度20〜30ｐｐｍの窒素雰囲気中、ピ−ク温度900
℃で2時間保持し、且つ全工程が6時間のプロファイルで
焼成し、半導体ベアチップ実装用凹部を有する低温焼成
多層セラミック回路基板を得た。A Cu paste for filling a through-hole (manufactured by Nippon Cement Co., Ltd.) and a Cu paste for wiring (manufactured by Nihon Cement Co., Ltd.) are screen-printed on a predetermined green sheet, and the temperature is 75 ° C.
After 10 minutes of drying, the green sheet of each layer was sequentially laminated on a mold having a convex portion corresponding to a semiconductor bare chip mounting concave portion, and integrated by hot pressing. The obtained laminate was placed in a nitrogen atmosphere with an oxygen concentration of 20 to 30 ppm at a peak temperature of 900.
The temperature was maintained at 2 ° C. for 2 hours, and the whole step was fired in a profile of 6 hours to obtain a low temperature fired multilayer ceramic circuit board having a recess for mounting a semiconductor bare chip.
【００１８】次に、この基板を85〜90℃に温調した無電
解Ａｕめっき液（K-24N：高純度化学社製）中に10分間
浸漬・攪拌し、該基板の凹部に露出されたＣｕ導体の表
面に無電解Ａｕめっき膜を形成させた。Ａｕめっき浴の
ｐＨは6.7〜7.0とし、浴中のＡｕ濃度は5ｇ／ｌとし
た。得られた無電解Ａｕめっき膜の膜厚は、約0.1μｍ
であった。Next, this substrate was immersed and stirred for 10 minutes in an electroless Au plating solution (K-24N: manufactured by Kojundo Chemical Co., Ltd.) whose temperature was adjusted to 85 to 90 ° C. to be exposed in the concave portion of the substrate. An electroless Au plating film was formed on the surface of the Cu conductor. The pH of the Au plating bath was 6.7 to 7.0, and the Au concentration in the bath was 5 g / l. The thickness of the obtained electroless Au plating film is about 0.1 μm.
Met.
【００１９】このようにして得られた低温焼成多層セラ
ミック回路基板の構造を図１（本発明の一実施例である
低温焼成多層セラミック回路基板の説明図）に基づいて
説明する。前記の方法で得られた低温焼成多層セラミッ
ク回路基板１は、図１に示すように、半導体ベアチップ
実装用の凹部及びＣｕ導体２からなる配線を有し、しか
も基板１の凹部に露出されたＣｕ導体２の表面に無電解
Ａｕめっき膜３を形成させた構造からなるものである。The structure of the low temperature fired multilayer ceramic circuit board thus obtained will be described with reference to FIG. 1 (an explanatory view of the low temperature fired multilayer ceramic circuit board which is an embodiment of the present invention). As shown in FIG. 1, the low temperature fired multilayer ceramic circuit board 1 obtained by the above method has a recess for mounting a semiconductor bare chip and a wiring made of a Cu conductor 2, and the Cu exposed in the recess of the board 1 is It has a structure in which the electroless Au plating film 3 is formed on the surface of the conductor 2.
【００２０】(2) 半導体ベアチップの実装例 半導体ベアチップの実装例を図２に基づいて説明する。
図２は、図１の無電解Ａｕめっき膜３を形成してなる低
温焼成多層セラミック回路基板１に半導体ベアチップを
実装した回路基板の説明図であって、まず、低温焼成多
層セラミック回路基板１の凹部に半導体ベアチップ４を
ワイヤ−ボンディング法により実装し、次に、封止用ガ
ラス６により気密封止し、図２に示す半導体ベアチップ
４を実装した基板１を得た。なお、図２中の２、３は図
１と同様Ｃｕ導体、無電解Ａｕめっき膜であり、また、
５はＡｕワイヤ−である。(2) Mounting example of semiconductor bare chip A mounting example of a semiconductor bare chip will be described with reference to FIG.
FIG. 2 is an explanatory view of a circuit board in which a semiconductor bare chip is mounted on the low temperature firing multilayer ceramic circuit board 1 formed by forming the electroless Au plating film 3 of FIG. The semiconductor bare chip 4 was mounted in the recess by the wire bonding method, and then hermetically sealed with the sealing glass 6, to obtain the substrate 1 on which the semiconductor bare chip 4 shown in FIG. 2 was mounted. 2, 2 and 3 are the Cu conductor and the electroless Au plating film as in FIG.
5 is an Au wire.
【００２１】[0021]
【発明の効果】本発明は、以上詳記したとおり、半導体
ベアチップと電気的接続を図るための電極パッドとし
て、基板の凹部に露出されたＣｕ導体表面に無電解Ａｕ
めっきを施すことによって形成することを特徴とするも
のであり、この方法の採用により配線導体にＣｕを用い
た低温焼成多層セラミック回路基板の凹部に対して、半
導体ベアチップを実装するためのＡｕ電極を容易に、し
かも低コストで形成することができる効果が生じる。As described in detail above, the present invention serves as an electrode pad for electrically connecting to a semiconductor bare chip, and an electroless Au film is formed on a Cu conductor surface exposed in a recess of a substrate.
It is characterized by being formed by plating, and by adopting this method, an Au electrode for mounting a semiconductor bare chip is provided in a recess of a low temperature firing multilayer ceramic circuit board using Cu as a wiring conductor. There is an effect that it can be formed easily and at low cost.
【図１】本発明の一実施例である低温焼成多層セラミッ
ク回路基板の説明図。FIG. 1 is an explanatory diagram of a low temperature fired multilayer ceramic circuit board that is an embodiment of the present invention.
【図２】図１の基板に半導体ベアチップを実装した回路
基板の説明図。FIG. 2 is an explanatory diagram of a circuit board in which a semiconductor bare chip is mounted on the board of FIG.
【符号の説明】 １ 低温焼成多層セラミック回路基板 ２ Ｃｕ導体 ３ 無電解Ａｕめっき膜 ４ 半導体ベアチップ ５ Ａｕワイヤ− ６ 封止用ガラス[Explanation of reference numerals] 1 low temperature fired multilayer ceramic circuit board 2 Cu conductor 3 electroless Au plating film 4 semiconductor bare chip 5 Au wire-6 sealing glass
───────────────────────────────────────────────────── フロントページの続き (72)発明者 高橋 繁 東京都江東区清澄１−２−23日本セメント 株式会社中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeru Takahashi 1-2-23 Kiyosumi, Koto-ku, Tokyo Nihon Cement Co., Ltd. Central Research Laboratory
Claims (1)
且つ配線導体にＣｕを用いた低温焼成多層セラミック回
路基板において、半導体ベアチップと電気的接続を図る
ための電極パッドを、該基板の凹部に露出されたＣｕ導
体表面に無電解Ａｕめっきを施すことによって形成する
ことを特徴とする低温焼成多層セラミック回路基板の製
造方法。1. A recess for mounting a semiconductor bare chip is provided,
In addition, in a low temperature fired multilayer ceramic circuit board using Cu as a wiring conductor, electrode pads for electrical connection with a semiconductor bare chip are provided by electroless Au plating on the Cu conductor surface exposed in the recess of the board. A method of manufacturing a low-temperature fired multilayer ceramic circuit board, which is characterized by being formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50A JPH06244307A (en) | 1993-02-17 | 1993-02-17 | Manufacture of low temperature firing multilayered ceramic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50A JPH06244307A (en) | 1993-02-17 | 1993-02-17 | Manufacture of low temperature firing multilayered ceramic circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06244307A true JPH06244307A (en) | 1994-09-02 |
Family
ID=12886275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50A Pending JPH06244307A (en) | 1993-02-17 | 1993-02-17 | Manufacture of low temperature firing multilayered ceramic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06244307A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10270589A (en) * | 1997-03-25 | 1998-10-09 | Rohm Co Ltd | Structure of semiconductor device |
| US6094354A (en) * | 1996-12-03 | 2000-07-25 | Nec Corporation | Chip component mounting board, chip component mounting structure, and method of manufacturing chip component mounting board |
| WO2001043167A2 (en) * | 1999-12-13 | 2001-06-14 | Sarnoff Corporation | Low temperature co-fired ceramic-metal packaging technology |
| US7183640B2 (en) | 1999-12-13 | 2007-02-27 | Lamina Ceramics, Inc. | Method and structures for enhanced temperature control of high power components on multilayer LTCC and LTCC-M boards |
-
1993
- 1993-02-17 JP JP50A patent/JPH06244307A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6094354A (en) * | 1996-12-03 | 2000-07-25 | Nec Corporation | Chip component mounting board, chip component mounting structure, and method of manufacturing chip component mounting board |
| JPH10270589A (en) * | 1997-03-25 | 1998-10-09 | Rohm Co Ltd | Structure of semiconductor device |
| WO2001043167A2 (en) * | 1999-12-13 | 2001-06-14 | Sarnoff Corporation | Low temperature co-fired ceramic-metal packaging technology |
| WO2001043167A3 (en) * | 1999-12-13 | 2002-01-24 | Sarnoff Corp | Low temperature co-fired ceramic-metal packaging technology |
| US6455930B1 (en) * | 1999-12-13 | 2002-09-24 | Lamina Ceramics, Inc. | Integrated heat sinking packages using low temperature co-fired ceramic metal circuit board technology |
| US7183640B2 (en) | 1999-12-13 | 2007-02-27 | Lamina Ceramics, Inc. | Method and structures for enhanced temperature control of high power components on multilayer LTCC and LTCC-M boards |
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