JPH06232334A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06232334A JPH06232334A JP1648693A JP1648693A JPH06232334A JP H06232334 A JPH06232334 A JP H06232334A JP 1648693 A JP1648693 A JP 1648693A JP 1648693 A JP1648693 A JP 1648693A JP H06232334 A JPH06232334 A JP H06232334A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- conductor layer
- substrate
- noise
- pass capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置内部に容量発
生領域(パスコンデンサ)を持つ半導体装置に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitance generating region (pass capacitor) inside the semiconductor device.
【0002】[0002]
【従来の技術】現在、製造されている回路基板内では様
々な雑音が発生している。この雑音は回路動作に悪影響
を及ぼし、回路の誤動作を起こす要因となっている。そ
こで回路設計者は、回路設計時に基板内雑音防止対策の
1つとして、半導体装置の近くにパスコンデンサを挿入
した回路を作製する。このパスコンデンサは半導体装置
のグランド電位部と電源電位部との間に挿入されるコン
デンサで、前記コンデンサを使用することで回路基板内
雑音の防止に対して大変有効である。そのため、一般的
によく利用される方法となっている。前記コンデンサの
実装部品のタイプはDPI部品,面実装部品などがあ
り、種類としてはセラミックコンデンサ,タンタルコン
デンサなどがある。2. Description of the Related Art At present, various noises are generated in a circuit board being manufactured. This noise adversely affects the operation of the circuit and causes a malfunction of the circuit. Therefore, the circuit designer creates a circuit in which a pass capacitor is inserted near the semiconductor device as one of the measures for preventing the noise in the substrate when designing the circuit. This pass capacitor is a capacitor inserted between the ground potential part and the power supply potential part of the semiconductor device, and by using the capacitor, it is very effective in preventing noise in the circuit board. Therefore, it is a commonly used method. There are DPI parts, surface mount parts, and the like as the types of parts mounted on the capacitor, and types such as ceramic capacitors and tantalum capacitors.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、前記基
板内雑音防止対策の1つとして、半導体装置の近くにパ
スコンデンサを挿入する手段は、非常に有効な手段で一
般によく使われてはいるが、これは数個の半導体装置に
対して1つのパスコンデンサを接続する手段である。However, as one of the measures for preventing the in-board noise, a means for inserting a pass capacitor near the semiconductor device is a very effective means and is generally used. This is a means for connecting one pass capacitor to several semiconductor devices.
【0004】ここで問題となるのは半導体装置が多数個
になった場合、パスコンデンサが多数個必要になるとい
うことである。そのため、回路動作に関係ない部品が多
くなり、部品コストがかかってしまうことになる。また
パスコンデンサという実装部品が増えるので、基板内に
余分な実装領域が必要になってしまう。そのため基板面
積を大きくする必要性もでてきてしまい、基板コストも
かかってしまうという問題があった。The problem here is that when a large number of semiconductor devices are provided, a large number of pass capacitors are required. Therefore, the number of parts that are not related to the circuit operation increases, and the parts cost increases. Moreover, since the number of mounting components called pass capacitors increases, an extra mounting area is required in the substrate. Therefore, there is a problem in that it is necessary to increase the area of the substrate and the cost of the substrate increases.
【0005】本発明は、このような問題点を解決し、雑
音対策の1つであるパスコンデンサという実装部品の低
減とともに低コスト化を図ることを目的とする。It is an object of the present invention to solve the above problems and to reduce the cost of mounting components such as a pass capacitor, which is one of the measures against noise, and to reduce the cost.
【0006】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するため、セラミック多層基板に半導体素子を実装して
なる半導体装置の外層または内層に導体層を有し、前記
導体層を複数層、相互に重なり合わせ容量発生領域を形
成したことを特徴とする。この半導体装置のグランド電
位と電源電位の導体層で容量発生領域を形成するもので
ある。In order to achieve the above-mentioned object, the present invention has a conductor layer as an outer layer or an inner layer of a semiconductor device in which a semiconductor element is mounted on a ceramic multi-layer substrate, and the conductor layer comprises a plurality of layers. It is characterized in that the capacitance generating regions are formed so as to overlap each other. The capacitance generating region is formed by the conductor layer of the ground potential and the power source potential of this semiconductor device.
【0007】[0007]
【作用】本発明によれば、雑音対策に有効なパスコンデ
ンサをパッケージ内に内蔵した半導体装置を使用するこ
とにより、マザー基板上にパスコンデンサを実装する必
要がなくなり、プリント回路基板作製時にコンデンサ部
品を減らすことができ、部品のコストを削減できる。ま
た、部品の実装面積が縮小でき、マザー基板を小さく作
製できる。According to the present invention, by using a semiconductor device having a pass capacitor effective for noise suppression built in a package, it is not necessary to mount the pass capacitor on a mother board, and a capacitor component is produced when a printed circuit board is manufactured. Can be reduced, and the cost of parts can be reduced. In addition, the mounting area of components can be reduced, and the mother substrate can be made small.
【0008】[0008]
【実施例】図1は本発明の一実施例におけるセラミック
多層基板を本体とする半導体装置の斜視図、図2は図1
の断面図(1)と各層における透視平面図(2)を示す。図1
および図2において、1は半導体素子、2はセラミック
基板、3は内部ベタ領域、4は配線パターン、5はサイ
ド電極、6はセラミック部、7は内部グランド導体層、
8は内部電源導体層である。1 is a perspective view of a semiconductor device having a ceramic multi-layer substrate as a main body in an embodiment of the present invention, and FIG.
A cross-sectional view (1) and a perspective plan view (2) of each layer are shown. Figure 1
In FIG. 2, 1 is a semiconductor element, 2 is a ceramic substrate, 3 is an internal solid region, 4 is a wiring pattern, 5 is a side electrode, 6 is a ceramic part, 7 is an internal ground conductor layer,
Reference numeral 8 is an internal power supply conductor layer.
【0009】上記構成において、セラミック部6を介し
て内部グランド導体層7と内部電源導体層8で容量発生
領域が形成される。In the above structure, the capacitance generating region is formed by the internal ground conductor layer 7 and the internal power supply conductor layer 8 with the ceramic portion 6 interposed therebetween.
【0010】次に本実施例の半導体装置内部に容量発生
領域(パスコンデンサ)を持つ半導体装置の作製について
説明する。セラミック基板2となる基板組成セラミック
粉を無機成分とし、有機バインダとしてポリビニルブチ
ラール、可塑剤としてジ−n−ブチルフタレート、溶剤
としてトルエンとイソプロピルアルコールの混合液(30
対70重量比)を混合しスラリーとした。このスラリーを
ドクターブレード法で有機フィルム上にシート形成し
た。このとき、造膜から乾燥,打ち抜きを行う各工程を
連続的に行うシステムを使用した。このグリーンシート
にコンデンサとすべく、導体ペーストをベタ印刷し、熱
圧着して積層体を形成した。Next, fabrication of a semiconductor device having a capacitance generating region (pass capacitor) inside the semiconductor device of this embodiment will be described. The substrate composition ceramic powder to be the ceramic substrate 2 is used as an inorganic component, polyvinyl butyral as an organic binder, di-n-butyl phthalate as a plasticizer, and a mixed liquid of toluene and isopropyl alcohol as a solvent (30
(70 weight ratio) was mixed to form a slurry. This slurry was formed into a sheet on an organic film by the doctor blade method. At this time, a system was used in which the steps of drying and punching from the film formation were continuously performed. A conductor paste was solid-printed on this green sheet to form a capacitor and thermocompression bonded to form a laminate.
【0011】サイド電極5を作製すべく、前記積層体の
外形に沿って所望の数のスルーホールを形成し、前記ス
ルーホールの内壁に導体層を形成すべく、スクリーン印
刷法で導体ペーストをスルーホール上に積層体の下から
吸引しながら印刷した。半導体素子1のグランド端子と
電源端子が接続するパッドは内部グランド導体層7と内
部電源導体層8に接続された任意のスルーホールに接続
されるようにスクリーン印刷法で導体印刷した。In order to form the side electrode 5, a desired number of through holes are formed along the outer shape of the laminated body, and a conductor paste is passed through by a screen printing method to form a conductor layer on the inner wall of the through hole. Printing was performed on the holes while sucking from below the laminate. Conductor printing was carried out by the screen printing method so that the pad connecting the ground terminal and the power supply terminal of the semiconductor element 1 was connected to an arbitrary through hole connected to the internal ground conductor layer 7 and the internal power supply conductor layer 8.
【0012】導体ペーストは、CuO粉末(平均粒径3μ
m)に接着強度を得るためのガラスフリット(日本電気硝
子社製 LS−0803ガラス粉末,平均粒径3μm)を2.5w
t%加えたものを無機成分とし、有機バインダであるエ
チルセルロースをターピネオールに溶かしたビヒクルを
加えて、3段ロールにより適度な粘度になるように混合
したものを用いた。The conductor paste is CuO powder (average particle size 3 μm).
2.5 w of glass frit (LS-0803 glass powder manufactured by Nippon Electric Glass Co., Ltd., average particle size 3 μm) for obtaining adhesive strength
A vehicle prepared by dissolving ethyl cellulose, which is an organic binder, in terpineol was added to the mixture containing t% as an inorganic component, and the mixture was mixed by a three-stage roll so as to have an appropriate viscosity.
【0013】このようにして印刷の終わった積層体を空
気中、600℃の温度で脱バインダを行った。その後、前
記積層体を水素ガス100%雰囲気中で300℃−5時間で還
元した。このときのCu層をX線回折により分析したと
ころ、100%Cuであることを確認した。最後に純窒素中
900℃のメッシュベルト炉で焼成した。The thus printed laminate was debindered in air at a temperature of 600 ° C. Then, the laminated body was reduced in an atmosphere of 100% hydrogen gas at 300 ° C. for 5 hours. When the Cu layer at this time was analyzed by X-ray diffraction, it was confirmed to be 100% Cu. Finally in pure nitrogen
It was baked in a mesh belt furnace at 900 ° C.
【0014】次に焼成した基板のスルーホール上にレー
ザーカッターでスクライブラインを入れ、スルーホール
を分割した。Next, a scribe line was put on the through hole of the fired substrate with a laser cutter to divide the through hole.
【0015】セラミック基板2の面積は20mm×20mmと
し、サイド電極5のスルーホール径は0.8mmとした。内
部グランド導体層7と内部電源導体層8の内部ベタ領域
3の面積は17mm×17mm、基板誘電率7.9、基板層間厚み
0.1mmとした。The area of the ceramic substrate 2 was 20 mm × 20 mm, and the through hole diameter of the side electrode 5 was 0.8 mm. The area of the inner solid area 3 of the inner ground conductor layer 7 and the inner power conductor layer 8 is 17 mm × 17 mm, the board permittivity is 7.9, and the board interlayer thickness is
It was set to 0.1 mm.
【0016】その結果、内部グランド導体層7と内部電
源導体層8の間に約20pFの容量を持たせることができ
た。これによって、20pFの容量を持つパスコンデンサ内
蔵の半導体装置を作製し、前記半導体装置により回路基
板内で発生する雑音に対処できる。As a result, a capacitance of about 20 pF could be provided between the internal ground conductor layer 7 and the internal power supply conductor layer 8. As a result, a semiconductor device with a built-in pass capacitor having a capacitance of 20 pF can be manufactured, and the semiconductor device can cope with noise generated in the circuit board.
【0017】[0017]
【発明の効果】以上説明したように本発明の半導体装置
は、パスコンデンサを半導体装置内に持たせることで、
雑音対策に有効である。また、半導体装置を使用する際
に、マザー基板上に必要であったパスコンデンサをなく
すことが可能になり、マザー基板上のコンデンサの部品
数を削減することができ、部品数が減ることでマザー基
板上での部品配置が容易になる。As described above, in the semiconductor device of the present invention, by providing the pass capacitor in the semiconductor device,
Effective for noise suppression. In addition, when using a semiconductor device, it is possible to eliminate the pass capacitor that was required on the mother board, and it is possible to reduce the number of capacitor parts on the mother board. The parts can be easily placed on the board.
【図1】本発明の一実施例におけるセラミック多層基板
を本体とする半導体装置の斜視図である。FIG. 1 is a perspective view of a semiconductor device having a ceramic multilayer substrate as a main body in an embodiment of the present invention.
【図2】図1の断面図(1)と各層における透視平面図(2)
である。FIG. 2 is a cross-sectional view (1) of FIG. 1 and a perspective plan view (2) of each layer.
Is.
1…半導体素子、 2…セラミック基板、 3…内部ベ
タ領域、 4…配線パターン、 5…サイド電極、 6
…セラミック部、 7…内部グランド導体層、8…内部
電源導体層。DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Ceramic substrate, 3 ... Internal solid region, 4 ... Wiring pattern, 5 ... Side electrode, 6
... ceramic part, 7 ... internal ground conductor layer, 8 ... internal power supply conductor layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 箱谷 靖彦 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 板垣 峰広 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 三浦 和裕 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiko Hakotani 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Kazuhiro Miura 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.
Claims (2)
してなる半導体装置の外層または内層に導体層を有し、
前記導体層を複数層、相互に重なり合わせ容量発生領域
を形成したことを特徴とする半導体装置。1. A semiconductor device in which a semiconductor element is mounted on a ceramic multilayer substrate has a conductor layer as an outer layer or an inner layer,
A semiconductor device, wherein a plurality of conductor layers are overlapped with each other to form a capacitance generation region.
発生領域を形成することを特徴とする請求項1記載の半
導体装置。2. The semiconductor device according to claim 1, wherein the capacitance generation region is formed by a conductor layer having a ground potential and a power supply potential.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5016486A JP2973261B2 (en) | 1993-02-03 | 1993-02-03 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5016486A JP2973261B2 (en) | 1993-02-03 | 1993-02-03 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06232334A true JPH06232334A (en) | 1994-08-19 |
JP2973261B2 JP2973261B2 (en) | 1999-11-08 |
Family
ID=11917618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5016486A Expired - Fee Related JP2973261B2 (en) | 1993-02-03 | 1993-02-03 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2973261B2 (en) |
-
1993
- 1993-02-03 JP JP5016486A patent/JP2973261B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2973261B2 (en) | 1999-11-08 |
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