JP2973261B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2973261B2 JP2973261B2 JP5016486A JP1648693A JP2973261B2 JP 2973261 B2 JP2973261 B2 JP 2973261B2 JP 5016486 A JP5016486 A JP 5016486A JP 1648693 A JP1648693 A JP 1648693A JP 2973261 B2 JP2973261 B2 JP 2973261B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- layer
- ceramic
- conductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置内部に容量発
生領域(パスコンデンサ)を持つ半導体装置に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitance generating area (pass capacitor) inside the semiconductor device.
【０００２】[0002]
【従来の技術】現在、製造されている回路基板内では様
々な雑音が発生している。この雑音は回路動作に悪影響
を及ぼし、回路の誤動作を起こす要因となっている。そ
こで回路設計者は、回路設計時に基板内雑音防止対策の
１つとして、半導体装置の近くにパスコンデンサを挿入
した回路を作製する。このパスコンデンサは半導体装置
のグランド電位部と電源電位部との間に挿入されるコン
デンサで、前記コンデンサを使用することで回路基板内
雑音の防止に対して大変有効である。そのため、一般的
によく利用される方法となっている。前記コンデンサの
実装部品のタイプはＤＰＩ部品，面実装部品などがあ
り、種類としてはセラミックコンデンサ，タンタルコン
デンサなどがある。2. Description of the Related Art At present, various noises are generated in a manufactured circuit board. This noise has an adverse effect on the circuit operation and causes a malfunction of the circuit. Therefore, a circuit designer prepares a circuit in which a pass capacitor is inserted near a semiconductor device as one of measures for preventing noise in a substrate when designing a circuit. This pass capacitor is a capacitor inserted between the ground potential portion and the power supply potential portion of the semiconductor device. The use of the capacitor is very effective in preventing noise in the circuit board. Therefore, it is a commonly used method. The types of components mounted on the capacitor include DPI components and surface mounted components, and the types include ceramic capacitors and tantalum capacitors.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、前記基
板内雑音防止対策の１つとして、半導体装置の近くにパ
スコンデンサを挿入する手段は、非常に有効な手段で一
般によく使われてはいるが、これは数個の半導体装置に
対して１つのパスコンデンサを接続する手段である。However, as one of the measures for preventing noise in the substrate, means for inserting a pass capacitor near the semiconductor device is a very effective means and is generally and often used. This is means for connecting one pass capacitor to several semiconductor devices.
【０００４】ここで問題となるのは半導体装置が多数個
になった場合、パスコンデンサが多数個必要になるとい
うことである。そのため、回路動作に関係ない部品が多
くなり、部品コストがかかってしまうことになる。また
パスコンデンサという実装部品が増えるので、基板内に
余分な実装領域が必要になってしまう。そのため基板面
積を大きくする必要性もでてきてしまい、基板コストも
かかってしまうという問題があった。The problem here is that when a large number of semiconductor devices are used, a large number of pass capacitors are required. For this reason, the number of components that are not related to the circuit operation increases, and the component cost increases. In addition, since the number of mounting components called pass capacitors increases, an extra mounting area is required in the substrate. Therefore, it is necessary to increase the substrate area, and there is a problem that the substrate cost is increased.
【０００５】本発明は、このような問題点を解決し、雑
音対策の１つであるパスコンデンサという実装部品の低
減とともに低コスト化を図ることを目的とする。An object of the present invention is to solve such a problem and to reduce the number of mounted components called pass capacitors, which is one of measures against noise, and to reduce the cost.
【０００６】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するために、マザー基板に実装するための半導体装置で
あって、外層または内層に導体層を有し、前記導体層と
セラミック基板とを複数層、相互に重なり合わせて、前
記導体層間に容量発生領域が設けられたセラミック多層
基板と、前記セラミック多層基板に実装された半導体素
子と、前記セラミック多層基板の端部に設けられた複数
のサイド電極とを備え、前記各々の導体層は前記任意の
サイド電極に接続され、前記半導体装置の表面には、前
記半導体素子と前記任意のサイド電極とを電気的に接続
するための配線パターンがあることを特徴とするもので
ある。SUMMARY OF THE INVENTION The present invention, in order to achieve the above object, a semiconductor device for mounting on a mother board
There has a conductor layer on the outer or inner layer, and the conductive layer
Multiple layers and the ceramic substrate, while overlapping each other, before
Ceramic multilayer with a capacitance generating area between the conductor layers
A substrate, and a semiconductor element mounted on the ceramic multilayer substrate.
And a plurality provided at an end of the ceramic multilayer substrate.
Side electrodes, wherein each of the conductive layers is the arbitrary
Connected to a side electrode, the front surface of the semiconductor device
The semiconductor element is electrically connected to the arbitrary side electrode.
There is a wiring pattern for performing the operation.
【０００７】[0007]
【作用】本発明によれば、雑音対策に有効なパスコンデ
ンサをパッケージ内に内蔵した半導体装置を使用するこ
とにより、マザー基板上にパスコンデンサを実装する必
要がなくなり、プリント回路基板作製時にコンデンサ部
品を減らすことができ、部品のコストを削減できる。ま
た、部品の実装面積が縮小でき、マザー基板を小さく作
製できる。According to the present invention, it is not necessary to mount a pass capacitor on a motherboard by using a semiconductor device in which a pass capacitor effective for noise suppression is incorporated in a package. And the cost of parts can be reduced. Further, the mounting area of the components can be reduced, and the mother board can be made smaller.
【０００８】[0008]
【実施例】図１は本発明の一実施例におけるセラミック
多層基板を本体とする半導体装置の斜視図、図２は図１
の断面図(1)と各層における透視平面図(2)を示す。図１
および図２において、１は半導体素子、２はセラミック
基板、３は内部ベタ領域、４は配線パターン、５はサイ
ド電極、６はセラミック部、７は内部グランド導体層、
８は内部電源導体層である。FIG. 1 is a perspective view of a semiconductor device having a ceramic multilayer substrate as a main body according to an embodiment of the present invention, and FIG.
FIG. 1 shows a cross-sectional view (1) and a perspective plan view (2) of each layer. FIG.
2, 1 is a semiconductor element, 2 is a ceramic substrate, 3 is an internal solid region, 4 is a wiring pattern, 5 is a side electrode, 6 is a ceramic portion, 7 is an internal ground conductor layer,
8 is an internal power supply conductor layer.
【０００９】上記構成において、セラミック部６を介し
て内部グランド導体層７と内部電源導体層８で容量発生
領域が形成される。In the above configuration, a capacitance generating region is formed by the internal ground conductor layer 7 and the internal power supply conductor layer 8 via the ceramic portion 6.
【００１０】次に本実施例の半導体装置内部に容量発生
領域(パスコンデンサ)を持つ半導体装置の作製について
説明する。セラミック基板２となる基板組成セラミック
粉を無機成分とし、有機バインダとしてポリビニルブチ
ラール、可塑剤としてジ−ｎ−ブチルフタレート、溶剤
としてトルエンとイソプロピルアルコールの混合液(30
対70重量比)を混合しスラリーとした。このスラリーを
ドクターブレード法で有機フィルム上にシート形成し
た。このとき、造膜から乾燥，打ち抜きを行う各工程を
連続的に行うシステムを使用した。このグリーンシート
にコンデンサとすべく、導体ペーストをベタ印刷し、熱
圧着して積層体を形成した。Next, the fabrication of a semiconductor device having a capacitance generating region (pass capacitor) inside the semiconductor device of this embodiment will be described. Substrate composition to be the ceramic substrate 2 Ceramic powder was used as an inorganic component, polyvinyl butyral as an organic binder, di-n-butyl phthalate as a plasticizer, and a mixed solution of toluene and isopropyl alcohol (30
(Weight ratio to 70 weight ratio) to obtain a slurry. This slurry was formed into a sheet on an organic film by a doctor blade method. At this time, a system for continuously performing each step of drying and punching from the film formation was used. In order to form a capacitor on the green sheet, a conductive paste was solid-printed and thermocompression bonded to form a laminate.
【００１１】サイド電極５を作製すべく、前記積層体の
外形に沿って所望の数のスルーホールを形成し、前記ス
ルーホールの内壁に導体層を形成すべく、スクリーン印
刷法で導体ペーストをスルーホール上に積層体の下から
吸引しながら印刷した。半導体素子１のグランド端子と
電源端子が接続するパッドは内部グランド導体層７と内
部電源導体層８に接続された任意のスルーホールに接続
されるようにスクリーン印刷法で導体印刷した。In order to form the side electrode 5, a desired number of through holes are formed along the outer shape of the laminate, and a conductive paste is formed by screen printing to form a conductive layer on the inner wall of the through hole. Printing was performed on the hole while sucking the laminate from below. Conductive printing was performed by a screen printing method so that the pad connecting the ground terminal and the power supply terminal of the semiconductor element 1 was connected to an arbitrary through hole connected to the internal ground conductor layer 7 and the internal power supply conductor layer 8.
【００１２】導体ペーストは、ＣuＯ粉末(平均粒径３μ
m)に接着強度を得るためのガラスフリット(日本電気硝
子社製 ＬＳ−0803ガラス粉末，平均粒径３μm)を2.5w
t％加えたものを無機成分とし、有機バインダであるエ
チルセルロースをターピネオールに溶かしたビヒクルを
加えて、３段ロールにより適度な粘度になるように混合
したものを用いた。The conductor paste is made of CuO powder (average particle size 3 μm).
m) 2.5 watts of glass frit (LS-0803 glass powder manufactured by Nippon Electric Glass Co., Ltd., average particle size 3 μm) for obtaining adhesive strength
What added t% was made into an inorganic component, the vehicle which melt | dissolved ethyl cellulose which is an organic binder in terpineol was added, and what mixed so that it might become moderate viscosity with a three-stage roll was used.
【００１３】このようにして印刷の終わった積層体を空
気中、600℃の温度で脱バインダを行った。その後、前
記積層体を水素ガス100％雰囲気中で300℃−５時間で還
元した。このときのＣu層をＸ線回折により分析したと
ころ、100％Ｃuであることを確認した。最後に純窒素中
900℃のメッシュベルト炉で焼成した。The thus printed laminate was subjected to binder removal at a temperature of 600 ° C. in air. Thereafter, the laminate was reduced at 300 ° C. for 5 hours in a 100% hydrogen gas atmosphere. When the Cu layer at this time was analyzed by X-ray diffraction, it was confirmed that the Cu layer was 100% Cu. Finally in pure nitrogen
It was fired in a mesh belt furnace at 900 ° C.
【００１４】次に焼成した基板のスルーホール上にレー
ザーカッターでスクライブラインを入れ、スルーホール
を分割した。Next, a scribe line was formed on the through-hole of the fired substrate with a laser cutter to divide the through-hole.
【００１５】セラミック基板２の面積は20mm×20mmと
し、サイド電極５のスルーホール径は0.8mmとした。内
部グランド導体層７と内部電源導体層８の内部ベタ領域
３の面積は17mm×17mm、基板誘電率7.9、基板層間厚み
0.1mmとした。The area of the ceramic substrate 2 was 20 mm × 20 mm, and the through-hole diameter of the side electrode 5 was 0.8 mm. The area of the internal solid region 3 of the internal ground conductor layer 7 and the internal power supply conductor layer 8 is 17 mm × 17 mm, the dielectric constant of the substrate is 7.9, and the thickness between the substrates is
0.1 mm.
【００１６】その結果、内部グランド導体層７と内部電
源導体層８の間に約20pFの容量を持たせることができ
た。これによって、20pFの容量を持つパスコンデンサ内
蔵の半導体装置を作製し、前記半導体装置により回路基
板内で発生する雑音に対処できる。As a result, a capacitance of about 20 pF could be provided between the internal ground conductor layer 7 and the internal power supply conductor layer 8. Thus, a semiconductor device having a built-in pass capacitor having a capacitance of 20 pF can be manufactured, and noise generated in the circuit board by the semiconductor device can be dealt with.
【００１７】[0017]
【発明の効果】以上説明したように本発明の半導体装置
は、パスコンデンサを半導体装置内に持たせることで、
雑音対策に有効である。また、半導体装置を使用する際
に、マザー基板上に必要であったパスコンデンサをなく
すことが可能になり、マザー基板上のコンデンサの部品
数を削減することができ、部品数が減ることでマザー基
板上での部品配置が容易になる。As described above, the semiconductor device of the present invention has a pass capacitor in the semiconductor device.
It is effective for noise suppression. In addition, when a semiconductor device is used, it is possible to eliminate a pass capacitor required on the motherboard, thereby reducing the number of components of the capacitor on the motherboard. Components can be easily arranged on the board.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の一実施例におけるセラミック多層基板
を本体とする半導体装置の斜視図である。FIG. 1 is a perspective view of a semiconductor device having a ceramic multilayer substrate as a main body according to an embodiment of the present invention.
【図２】図１の断面図(1)と各層における透視平面図(2)
である。FIG. 2 is a sectional view (1) of FIG. 1 and a perspective plan view (2) of each layer.
It is.
１…半導体素子、 ２…セラミック基板、 ３…内部ベ
タ領域、 ４…配線パターン、 ５…サイド電極、 ６
…セラミック部、 ７…内部グランド導体層、８…内部
電源導体層。DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Ceramic substrate, 3 ... Internal solid area, 4 ... Wiring pattern, 5 ... Side electrode, 6
... ceramic part, 7 ... internal ground conductor layer, 8 ... internal power supply conductor layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 箱谷 靖彦 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (72)発明者 板垣 峰広 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (72)発明者 三浦 和裕 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 平３−225859（ＪＰ，Ａ) 特開 昭63−107128（ＪＰ，Ａ) 実開 昭62−91455（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 25/00 H01L 23/12 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yasuhiko Hakotani 1006 Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. Inside (72) Inventor Kazuhiro Miura 1006 Kadoma, Kazuma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-3-225859 (JP, A) JP-A-63-107128 (JP, A) Actual opening 62-91455 (JP, U) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 25/00 H01L 23/12
Claims (2)
であって、外層または内層に導体層を有し、前記導体層
とセラミック基板とを複数層、相互に重なり合わせて、
前記導体層間に容量発生領域が設けられたセラミック多
層基板と、前記セラミック多層基板に実装された半導体
素子と、前記セラミック多層基板の端部に設けられた複
数のサイド電極とを備え、前記各々の導体層は前記任意
のサイド電極に接続され、前記半導体装置の表面には、
前記半導体素子と前記任意のサイド電極とを電気的に接
続するための配線パターンがあることを特徴とする半導
体装置。1. A semiconductor device for mounting on a mother board.
Having a conductor layer in an outer layer or an inner layer, wherein the conductor layer
And a ceramic substrate with multiple layers overlapping each other ,
A ceramic multi- layer having a capacitance generating region between the conductor layers
Layer substrate and semiconductor mounted on the ceramic multilayer substrate
An element and a plurality of elements provided at an end of the ceramic multilayer substrate.
A number of side electrodes, wherein each of the conductive layers is
Of the semiconductor device,
Electrically connecting the semiconductor element to the arbitrary side electrode;
A semiconductor device having a wiring pattern for connection .
サイド電極は、前記セラミック多層基板のスルーホール
の内壁に導体層を形成してなる請求項１記載の半導体装
置。2. The method according to claim 1, wherein the ceramic multilayer substrate is provided at an end thereof.
Side electrodes are through holes in the ceramic multilayer substrate.
2. The semiconductor device according to claim 1, wherein a conductor layer is formed on an inner wall of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5016486A JP2973261B2 (en) | 1993-02-03 | 1993-02-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5016486A JP2973261B2 (en) | 1993-02-03 | 1993-02-03 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06232334A JPH06232334A (en) | 1994-08-19 |
| JP2973261B2 true JP2973261B2 (en) | 1999-11-08 |
Family
ID=11917618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5016486A Expired - Fee Related JP2973261B2 (en) | 1993-02-03 | 1993-02-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2973261B2 (en) |
-
1993
- 1993-02-03 JP JP5016486A patent/JP2973261B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06232334A (en) | 1994-08-19 |
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