WO2020241239A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2020241239A1
WO2020241239A1 PCT/JP2020/018954 JP2020018954W WO2020241239A1 WO 2020241239 A1 WO2020241239 A1 WO 2020241239A1 JP 2020018954 W JP2020018954 W JP 2020018954W WO 2020241239 A1 WO2020241239 A1 WO 2020241239A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
pair
metal member
metal
pores
Prior art date
Application number
PCT/JP2020/018954
Other languages
French (fr)
Japanese (ja)
Inventor
明寛 木村
開人 井上
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to DE212020000458.7U priority Critical patent/DE212020000458U1/en
Publication of WO2020241239A1 publication Critical patent/WO2020241239A1/en

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    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Definitions

  • the present disclosure relates to a semiconductor device equipped with a semiconductor element.
  • Patent Document 1 discloses an example of a semiconductor device equipped with a semiconductor element.
  • the semiconductor device described in Patent Document 1 includes a semiconductor element, a support member, a heat diffusion plate, and a sealing member.
  • the semiconductor element is bonded to the heat diffusion plate by soldering.
  • the support member includes a conductive pattern, a metal plate and an insulating resin.
  • an insulating resin for example, ceramics
  • a metal plate for example, a metal such as aluminum or copper or an alloy thereof
  • a conductive pattern for example, a metal such as aluminum or copper or a metal thereof
  • the alloy is formed.
  • the heat diffusion plate is, for example, a plate-shaped member made of copper or a copper alloy.
  • the heat diffusion plate is joined to the conductive pattern of the support member by soldering.
  • the sealing member covers the semiconductor element, a part of the support member, the heat diffusion plate, and each solder.
  • Heat is generated from the semiconductor element when the semiconductor device is energized.
  • thermal stress is applied to the solder that joins the heat diffusion plate and the support member, for example, due to the difference in thermal expansion of the constituent members. This thermal stress may cause cohesive failure of the solder, and is a cause of product failure such as poor joining and poor continuity.
  • the present disclosure has been conceived in view of the above circumstances, and an object thereof is to provide a semiconductor device having improved reliability by relaxing thermal stress at the time of heat generation of a semiconductor element. ..
  • the semiconductor device of the present disclosure has a first main surface and a first back surface separated from the support member in the thickness direction, and the first back surface faces the support member and is joined to the support member.
  • a sealing member for covering the semiconductor element is provided, and the metal member is a porous body in which a plurality of pores are formed.
  • the thermal stress at the time of heat generation of the semiconductor element can be relaxed. Therefore, the reliability of the semiconductor device can be improved.
  • FIG. 3 is a cross-sectional view taken along the line VIII-VIII of FIG.
  • the semiconductor device A1 includes a plurality of semiconductor elements 10, a support member 2, a plurality of metal members 30, a plurality of first bonding layers 41, a plurality of second bonding layers 42, a pair of input terminals 51, a pair of output terminals 52, and a plurality of.
  • the control terminal 53, the plurality of detection terminals 54, the plurality of connecting members 6, and the sealing member 7 are provided.
  • FIG. 1 is a perspective view showing the semiconductor device A1.
  • FIG. 2 is a plan view showing the semiconductor device A1.
  • FIG. 3 is a plan view of FIG. 2 showing the sealing member 7 as an imaginary line (dashed-dotted line).
  • FIG. 4 is a bottom view showing the semiconductor device A1.
  • FIG. 5 is a side view (right side view) showing the semiconductor device A1.
  • FIG. 6 is a side view (left side view) showing the semiconductor device A1.
  • FIG. 7 is a front view showing the semiconductor device A1.
  • FIG. 8 is a cross-sectional view taken along the line VIII-VIII of FIG.
  • FIG. 9 is a cross-sectional view taken along the line IX-IX of FIG.
  • FIG. 10 is a cross-sectional view taken along the line XX of FIG.
  • FIG. 10 is a cross-sectional view taken along the line XX of FIG.
  • FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG.
  • FIG. 12 is a partially enlarged view of a part of FIG.
  • FIG. 13 is a cross-sectional view taken along the line XIII-XIII of FIG.
  • FIG. 14 is a schematic cross-sectional view of the metal member 30.
  • the three directions orthogonal to each other are defined as the x direction, the y direction, and the z direction.
  • the z direction is the thickness direction of the semiconductor device A1.
  • the x direction is the left-right direction in the plan view (see FIG. 2) of the semiconductor device A1.
  • the y direction is the vertical direction in the plan view (see FIG. 2) of the semiconductor device A1.
  • one in the x direction is defined as the x1 direction
  • the other in the x direction is defined as the x2 direction.
  • one in the y direction is the y1 direction
  • the other in the y direction is the y2 direction
  • one in the z direction is the z1 direction
  • the other in the z direction is the z2 direction.
  • the z1 direction may be referred to as the lower side, and the z2 direction may be referred to as the upper side.
  • the x direction corresponds to the "first direction” described in the claims, and the y direction corresponds to the "second direction” described in the claims.
  • the semiconductor device A1 is, for example, a power conversion device (power module) used for a drive source of a motor, an inverter device of various electric products, a DC / DC converter of various electric products, and the like.
  • the semiconductor device A1 constitutes, for example, a half-bridge type switching circuit.
  • Each of the plurality of semiconductor elements 10 is, for example, a MOSFET.
  • the semiconductor element 10 is not limited to a MOSFET, and may be a switching element such as a field effect transistor including a MISFET (Metal-Insulator-Semiconductor FET) or a bipolar transistor including an IGBT.
  • each semiconductor element 10 may be not only a switching element but also an IC chip such as an LSI, a diode, a capacitor, or the like.
  • each semiconductor element 10 shows a case where it is an n-channel type MOSFET, but it may be a p-channel type.
  • Each semiconductor element 10 is configured by using a semiconductor material mainly composed of SiC (silicon carbide).
  • the semiconductor material is not limited to SiC, and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), Ga 2 O 3 (gallium oxide), or the like.
  • Each semiconductor element 10 is bonded to any of a plurality of metal members 30 by the first bonding layer 41.
  • Each semiconductor element 10 has a rectangular shape when viewed in the z direction (hereinafter, also referred to as “planar view”).
  • each semiconductor element 10 has a main surface 101 and a back surface 102.
  • the main surface 101 and the back surface 102 are separated from each other in the z direction.
  • the main surface 101 faces the z2 direction, and the back surface 102 faces the z1 direction.
  • the back surface 102 is in contact with the first bonding layer 41 and faces any of the plurality of metal members 30.
  • each semiconductor element 10 has a first electrode 11, a second electrode 12, a third electrode 13, and an insulating film 14.
  • the first electrode 11 is arranged on the main surface 101 side in the z direction in each semiconductor element 10.
  • the first electrode 11 is exposed on the main surface 101 of the semiconductor element 10.
  • the first electrode 11 is, for example, a source electrode through which a source current flows. As shown in FIG. 12, the first electrode 11 has, for example, a configuration divided into four.
  • the second electrode 12 is arranged on the back surface 102 side in the z direction in each semiconductor element 10.
  • the second electrode 12 is exposed on the back surface 102 of the semiconductor element 10.
  • the second electrode 12 is, for example, a drain electrode through which a drain current flows.
  • the third electrode 13 is arranged on the main surface 101 side in the z direction in each semiconductor element 10.
  • the third electrode 13 is exposed on the main surface 101 of the semiconductor element 10.
  • the third electrode 13 is, for example, a gate electrode, and a gate voltage (control voltage) for driving the semiconductor element 10 is applied.
  • the size of the third electrode 13 is smaller than the size of one portion of the first electrode 11 divided into four.
  • the insulating film 14 is arranged on the main surface 101 side in the z direction in each semiconductor element 10.
  • the third electrode 13 is exposed on the main surface 101 of the semiconductor element 10.
  • the insulating film 14 surrounds the first electrode 11 and the third electrode 13 in a plan view, respectively.
  • the insulating film 14 insulates the first electrode 11 and the third electrode 13.
  • a SiO 2 (silicon dioxide) layer, a SiN 4 (silicon nitride) layer, and a polybenzoxazole layer are laminated in this order, and the polybenzoxazole layer is the main component of each semiconductor element 10. It is a surface layer on the surface 101 side.
  • a polyimide layer may be used instead of the polybenzoxazole layer.
  • the plurality of semiconductor elements 10 include a plurality of first elements 10A and a plurality of second elements 10B.
  • the semiconductor device A1 constitutes a half-bridge type switching circuit.
  • the plurality of first elements 10A form an upper arm circuit in this switching circuit.
  • the plurality of second elements 10B form a lower arm circuit in this switching circuit.
  • the semiconductor device A1 includes two (pair) first elements 10A and two (pair) second elements 10B.
  • the number of semiconductor elements 10 is not limited to this configuration, and can be freely set according to the performance required for the semiconductor device A1.
  • the support member 2 supports a plurality of semiconductor elements 10 via the plurality of metal members 30.
  • the support member 2 includes an insulating substrate 21 and a plurality of wiring layers 22.
  • the insulating substrate 21 has electrical insulation.
  • the constituent material of the insulating substrate 21 is, for example, ceramics having excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride), SiN (silicon nitride), and Al 2 O 3 (aluminum oxide).
  • the insulating substrate 21 has a flat plate shape. As shown in FIG. 3, the insulating substrate 21 has a rectangular shape in a plan view.
  • the thickness (dimension in the z direction) of each insulating substrate 21 is 0.2 mm or more and 1.0 mm or less (for example, 0.5 mm).
  • the insulating substrate 21 has a main surface 211 and a back surface 212.
  • the main surface 211 and the back surface 212 are separated from each other in the z direction.
  • the main surface 211 faces the z2 direction, and the back surface 212 faces the z1 direction.
  • the back surface 212 is exposed from the sealing member 7.
  • a heat sink (not shown) may be connected to the back surface 212.
  • the configuration of the insulating substrate 21 is not limited to that shown in the drawing, and may be provided individually for each of the plurality of wiring layers 22.
  • Each of the plurality of wiring layers 22 is formed on the main surface 211 of the insulating substrate 21.
  • the plurality of wiring layers 22 are separated from each other.
  • Each wiring layer 22 is made of, for example, a metal containing silver.
  • the constituent material of each wiring layer 22 is not limited to the metal containing silver.
  • it may be a metal containing copper, or the metal containing copper may be silver-plated.
  • a plurality of types of metal plating in which an aluminum layer, a nickel layer, and a silver layer are laminated in this order may be applied. All of the plurality of wiring layers 22 are located inward of the peripheral edge of the insulating substrate 21 in a plan view.
  • Each wiring layer 22 has a rectangular shape in a plan view.
  • Each wiring layer 22 is covered with a sealing member 7.
  • the thickness (dimension in the z direction) of each wiring layer 22 is, for example, 5 ⁇ m or more and 80 ⁇ m or less.
  • the plurality of wiring layers 22 include a pair of first wiring layers 22A, a pair of second wiring layers 22B, and a third wiring layer 22C.
  • the pair of first wiring layers 22A, the pair of second wiring layers 22B, and the third wiring layer 22C are separated from each other in a plan view.
  • the pair of first wiring layers 22A is located on the x1 direction side of the insulating substrate 21.
  • the pair of first wiring layers 22A are separated from each other in the y direction.
  • the pair of second wiring layers 22B are located on the x2 direction side of the insulating substrate 21.
  • the pair of second wiring layers 22B are separated from each other in the y direction.
  • the pair of second wiring layers 22B are located next to the pair of first wiring layers 22A in the x direction.
  • the third wiring layer 22C is located on the insulating substrate 21 on the x1 direction side.
  • the third wiring layer 22C is located between the pair of first wiring layers 22A.
  • the plurality of wiring layers 22 (a pair of first wiring layers 22A, a pair of second wiring layers 22B, and a third wiring layer 22C) have a main surface 221 and a back surface 222, respectively.
  • the main surface 221 and the back surface 222 are separated from each other in the z direction.
  • the main surface 221 faces the z2 direction, and the back surface 222 faces the z1 direction.
  • the back surface 222 faces the main surface 211 of the insulating substrate 21 in a state where each wiring layer 22 is joined to the insulating substrate 21.
  • the main surface 221 corresponds to the "second main surface” described in the claims
  • the back surface 222 corresponds to the "second back surface” described in the claims.
  • a plurality of metal members 30 are arranged one by one on each wiring layer 22. Each metal member 30 is joined to each wiring layer 22 by a second joining layer 42. A plurality of semiconductor elements 10 are bonded to the plurality of metal members 30 by the first bonding layer 41.
  • the thickness (dimension in the z direction) of each metal member 30 is 0.5 mm or more and 5 mm or less (preferably 1.0 mm or more and 3 mm or less).
  • the plurality of metal members 30 include a pair of first metal members 30A, a pair of second metal members 30B, and a third metal member 30C.
  • the pair of first metal members 30A, the pair of second metal members 30B, and the third metal member 30C are separated from each other in a plan view.
  • the pair of first metal members 30A are arranged on the pair of first wiring layers 22A, respectively.
  • Each of the first elements 10A is bonded onto each of the first metal members 30A.
  • the pair of second metal members 30B are arranged on the pair of second wiring layers 22B, respectively, as shown in FIGS. 3, 8 and 9. Each of the second elements 10B is bonded onto each of the second metal members 30B.
  • the third metal member 30C is arranged on the third wiring layer 22C as shown in FIGS. 3, 9 and 10. None of the plurality of semiconductor elements 10 are bonded to the third metal member 30C. Since none of the plurality of semiconductor elements 10 are bonded to the third metal member 30C, the semiconductor device A1 does not have to include the third metal member 30C.
  • the plurality of metal members 30 (a pair of first metal members 30A, a pair of second metal members 30B, and a third metal member 30C) have a main surface 301 and a back surface 302, respectively.
  • the main surface 301 and the back surface 302 are separated from each other in the z direction.
  • the main surface 301 faces the z2 direction, and the back surface 302 faces the z1 direction.
  • the main surface 301 faces the main surface 101 of each semiconductor element 10 in a state where each semiconductor element 10 is joined to each metal member 30.
  • the back surface 302 faces the main surface 221 of each wiring layer 22 in a state where each metal member 30 is joined to each wiring layer 22.
  • the main surface 301 corresponds to the "first main surface” described in the claims, and the back surface 302 corresponds to the "first back surface” described in the claims.
  • the pair of side surfaces 303 are connected to both the main surface 301 and the back surface 302 in the z direction, and are sandwiched between them.
  • the pair of side surfaces 303 are separated in the x direction and face opposite to each other.
  • the pair of side surfaces 304 are connected to and sandwiched between the main surface 301 and the back surface 302 in the z direction.
  • the pair of side surfaces 304 are separated in the y direction and face opposite to each other.
  • the side surface 303 corresponds to the "first side surface” described in the claims
  • the side surface 304 corresponds to the "second side surface” described in the claims.
  • each of the plurality of metal members 30 (a pair of first metal members 30A, a pair of second metal members 30B and a third metal member 30C) is a porous body in which a plurality of pores 31 are formed. Is.
  • the occupancy rate of the plurality of pores 31 with respect to each metal member 30 is, for example, 10% or more and 70% or less.
  • the constituent material of each metal member 30 is copper or a copper alloy.
  • the plurality of pores 31 are irregularly arranged as shown in FIGS. 13 and 14.
  • the plurality of pores 31 include those appearing on the main surface 301, those appearing on the back surface 302, those appearing on each side surface 303, and those appearing on each side surface 304.
  • the sealing member 7 is filled in the pores 31 connected to the main surface 301, the back surface 302, and the side surfaces 303, 304 in contact with the sealing member 7.
  • FIG. 14 shows how the sealing member 7 is filled in the pores 31 appearing on the main surface 301.
  • some of the plurality of pores 31 are formed inside each metal member 30.
  • the pores 31 formed inside each of the metal members 30 are pores filled with gas (for example, air).
  • Each of the plurality of first bonding layers 41 is interposed between each semiconductor element 10 and each metal member 30 to bond them.
  • the first bonding layer 41 is, for example, solder.
  • the solder may be lead-containing or lead-free.
  • each first bonding layer 41 is not limited to solder, and may be another conductive bonding material such as a sintered metal.
  • the first bonding layer 41 corresponds to the "conductive bonding material" described in the claims.
  • Each of the plurality of second bonding layers 42 is interposed between each metal member 30 and each wiring layer 22 to bond them.
  • Each second bonding layer 42 is, for example, solder.
  • the solder may be lead-containing or lead-free.
  • each second bonding layer 42 is not limited to solder, and may be another conductive bonding material such as a sintered metal, or may be an insulating bonding material (adhesive).
  • the second bonding layer 42 corresponds to the "bonding layer" described in the claims.
  • the pair of input terminals 51, the pair of output terminals 52, the plurality of control terminals 53, and the plurality of detection terminals 54 are each made of copper or a copper alloy.
  • the pair of input terminals 51, the pair of output terminals 52, the plurality of control terminals 53, and the plurality of detection terminals 54 are composed of the same lead frame.
  • the pair of input terminals 51 are located on the x1 direction side in the semiconductor device A1.
  • the pair of input terminals 51 are separated from each other in the y direction.
  • the pair of input terminals 51 are connected to an external DC power supply. For example, a DC voltage is applied between the pair of input terminals 51.
  • Each of the pair of input terminals 51 is partially covered with a sealing member 7, and is thereby supported by the sealing member 7.
  • the pair of input terminals 51 includes a first input terminal 51A and a second input terminal 51B.
  • the first input terminal 51A is a positive electrode (P terminal)
  • the second input terminal 51B is a negative electrode (N terminal).
  • the first input terminal 51A and the second input terminal 51B include a pad portion 511 and a terminal portion 512, respectively.
  • the pad portion 511 is located outside the peripheral edge of the support member 2 in a plan view, and is separated from the support member 2 in the z direction.
  • the pad portion 511 is covered with a sealing member 7.
  • the surface of the pad portion 511 may be silver-plated, for example.
  • the terminal portion 512 is connected to the pad portion 511 and is exposed from the sealing member 7.
  • the terminal portion 512 is used when the semiconductor device A1 is mounted on the wiring board.
  • the terminal portion 512 has an L shape when viewed in the y direction.
  • the surface of the terminal portion 512 may be nickel-plated, for example.
  • the terminal portion 512 includes a base portion 513 and an upright portion 514.
  • the base portion 513 is connected to the pad portion 511 and extends in the x direction from the sealing member 7 (side surface 731 described later).
  • the upright portion 514 extends in the z2 direction from the tip of the base portion 513 in the x direction.
  • the pair of output terminals 52 are located on the x2 direction side in the semiconductor device A1. As shown in FIGS. 1 to 4, the pair of output terminals 52 are separated from each other in the y direction. AC power (AC voltage) converted by a plurality of semiconductor elements 10 is output from the pair of output terminals 52. Each of the pair of output terminals 52 is partially covered with a sealing member 7, and is thereby supported by the sealing member 7.
  • the pair of output terminals 52 include a pad portion 521 and a terminal portion 522, respectively.
  • the pad portion 521 is located outside the peripheral edge of the support member 2 in a plan view, and is separated from the support member 2 in the z direction.
  • the pad portion 521 is covered with a sealing member 7.
  • the surface of the pad portion 521 may be silver-plated, for example.
  • the terminal portion 522 is connected to the pad portion 521 and is exposed from the sealing member 7.
  • the terminal portion 522 is used when mounting the semiconductor device A1 on the wiring board.
  • the terminal portion 522 has an L shape when viewed in the y direction.
  • the shape of the terminal portion 522 is substantially the same as the shape of the terminal portion 512 of each input terminal 51.
  • the surface of the terminal portion 522 may be nickel-plated, for example.
  • the terminal portion 522 includes a base portion 523 and an upright portion 524.
  • the base portion 523 is connected to the pad portion 521 and extends in the x direction from the sealing member 7 (side surface 732 described later).
  • the upright portion 524 extends in the z2 direction from the tip of the base portion 523 in the x direction.
  • the plurality of control terminals 53 are located on both sides in the x direction in the semiconductor device A1.
  • the plurality of control terminals 53 located on the x1 direction side are both located between the pair of input terminals 51 in the y direction.
  • the plurality of control terminals 53 located on the x2 direction side are both located between the pair of output terminals 52 in the y direction.
  • the number of control terminals 53 corresponds to the number of semiconductor elements 10. Therefore, the semiconductor device A1 includes four control terminals 53.
  • a control voltage (gate voltage) for driving each semiconductor element 10 is applied to each control terminal 53.
  • Each control terminal 53 is partially covered with a sealing member 7, and is thereby supported by the sealing member 7.
  • Each control terminal 53 includes a pad portion 531 and a terminal portion 532.
  • the pad portion 531 is located outside the peripheral edge of the support member 2 in a plan view, and is separated from the support member 2 in the z direction.
  • the pad portion 531 is covered with a sealing member 7.
  • the surface of the pad portion 531 may be silver-plated, for example.
  • the terminal portion 532 is connected to the pad portion 531 and is exposed from the sealing member 7.
  • the terminal portion 532 is used when the semiconductor device A1 is mounted on the wiring board.
  • the terminal portion 532 has an L shape when viewed in the y direction.
  • the surface of the terminal portion 532 may be nickel-plated, for example.
  • the terminal portion 532 includes a base portion 533 and an upright portion 534.
  • the base portion 533 is connected to the pad portion 531 and extends in the x direction from the sealing member 7 (either the side surface 731 or the side surface 732 described later).
  • the x-direction dimensions of the base 533 are smaller than the x-direction dimensions of each base 513 of the pair of input terminals 51 and each base 523 of the pair of output terminals 52.
  • the upright portion 534 extends in the z2 direction from the tip of the base portion 533 in the x direction.
  • the plurality of detection terminals 54 are located on both sides in the x direction in the semiconductor device A1.
  • the plurality of detection terminals 54 located on the x1 direction side are both located between the pair of input terminals 51 in the y direction.
  • the plurality of detection terminals 54 located on the x2 direction side are both located between the pair of output terminals 52 in the y direction.
  • the number of detection terminals 54 corresponds to the number of semiconductor elements 10. Therefore, the semiconductor device A1 includes four detection terminals 54. A voltage corresponding to the current flowing through the first electrode 11 (source electrode) of each semiconductor element 10 is applied to each detection terminal 54.
  • Each detection terminal 54 includes a pad portion 541 and a terminal portion 542.
  • the pad portion 541 is located outside the peripheral edge of the support member 2 in a plan view, and is separated from the support member 2 in the z direction.
  • the pad portion 541 is covered with a sealing member 7.
  • the surface of the pad portion 541 may be silver-plated, for example.
  • the terminal portion 542 is connected to the pad portion 541 and is exposed from the sealing member 7.
  • the terminal portion 542 is used when the semiconductor device A1 is mounted on the wiring board.
  • the terminal portion 542 has an L shape when viewed in the y direction.
  • the surface of the terminal portion 542 may be nickel-plated, for example.
  • the terminal portion 542 includes a base portion 543 and an upright portion 544.
  • the base portion 533 is connected to the pad portion 531 and extends in the x direction from the sealing member 7 (either the side surface 731 or the side surface 732 described later).
  • the x-direction dimensions of the base 543 are substantially the same as the x-direction dimensions of the base 533 of each control terminal 53, and the x of each base 513 of the pair of input terminals 51 and each base 523 of the pair of output terminals 52. Less than each dimension in the direction.
  • the upright portion 544 extends in the z2 direction from the tip of the base portion 543 in the x direction.
  • Each of the plurality of connecting members 6 conducts between two separated members.
  • the plurality of connecting members 6 include a plurality of first wires 611, a plurality of second wires 612, a plurality of third wires 613, a plurality of fourth wires 614, a first conductive member 621, and a second wire.
  • the conductive member 622, the third conductive member 623, and the fourth conductive member 624 are included.
  • Each of the plurality of first wires 611 is joined to each first electrode 11 of the pair of first elements 10A and each main surface 301 of the pair of second metal members 30B.
  • each of the second metal members 30B (each of the second wiring layers 22B) is conductive to the first electrode 11 of each of the first elements 10A via each of the first wires 611.
  • the constituent material of each first wire 611 is, for example, a metal containing aluminum, a metal containing copper, or a metal containing gold.
  • Each of the plurality of second wires 612 is joined to each first electrode 11 of the pair of second elements 10B and the main surface 301 of the third metal member 30C.
  • the third metal member 30C (third wiring layer 22C) is conducting to the first electrode 11 of each second element 10B via each second wire 612.
  • the constituent material of each second wire 612 is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, and the like.
  • Each of the plurality of third wires 613 is joined to each third electrode 13 of the plurality of semiconductor elements 10 and each pad portion 531 of the plurality of control terminals 53. As a result, each control terminal 53 is conductive to the third electrode 13 of each semiconductor element 10 via each third wire 613.
  • the constituent material of each third wire 613 is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, and the like.
  • Each of the plurality of fourth wires 614 is joined to each first electrode 11 of the plurality of semiconductor elements 10 and each pad portion 541 of the plurality of detection terminals 54. As a result, each detection terminal 54 is conductive to the first electrode 11 of each semiconductor element 10 via each fourth wire 614.
  • the constituent material of each fourth wire 614 is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, and the like.
  • the first conductive member 621 is joined to the main surface 301 of one first metal member 30A and the main surface 301 of the other first metal member 30A.
  • the pair of first metal members 30A (pair of first wiring layers 22A) are electrically connected to each other.
  • the first conductive member 621 extends in the y direction in a plan view and straddles the third wiring layer 22C.
  • the first conductive member 621 is composed of, for example, a plurality of bonding wires.
  • the constituent material of the bonding wire is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, or the like.
  • the second conductive member 622 is joined to the pad portion 511 of the first input terminal 51A and the main surface 301 of one of the first metal members 30A.
  • the first input terminal 51A is conducting to one of the first metal members 30A (one of the first wiring layers 22A) via the second conducting member 622. Therefore, the first input terminal 51A conducts to the second electrode 12 of one first element 10A via the second conduction member 622 and one first metal member 30A (one first wiring layer 22A).
  • the second conductive member 622 is composed of, for example, a plurality of bonding wires.
  • the constituent material of the bonding wire is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, or the like.
  • the third conductive member 623 is joined to the pad portion 511 of the second input terminal 51B and the main surface 221 of the third wiring layer 22C.
  • the second input terminal 51B is connected to the first electrode of each second element 10B via the third conductive member 623, the third metal member 30C (third wiring layer 22C), and the plurality of second wires 612. It is conducting to 11.
  • the third conductive member 623 is composed of, for example, a plurality of bonding wires.
  • the constituent material of the bonding wire is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, or the like.
  • the pair of fourth conductive members 624 are joined to each pad portion 521 of the pair of output terminals 52 and each main surface 301 of the pair of second metal members 30B.
  • the pair of output terminals 52 conduct with the second electrode 12 of each second element 10B via the pair of fourth conductive members 624 and the pair of second metal members 30B (pair of second wiring layers 22B).
  • the pair of output terminals 52 is the first of each first element 10A via the pair of fourth conductive members 624, the pair of second metal members 30B (second wiring layer 22B), and the plurality of first wires 611. It is conducting to the electrode 11.
  • Each of the pair of fourth conductive members 624 is composed of, for example, a plurality of bonding wires, as shown in FIG.
  • the constituent material of the bonding wire is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, or the like.
  • the first conductive member 621, the second conductive member 622, the third conductive member 623, and the pair of fourth conductive members 624 may be metal leads or bonding ribbons instead of a plurality of bonding wires, respectively.
  • Each constituent material of the metal lead or bonding ribbon is, for example, a metal containing copper, a metal containing aluminum, or a metal containing gold.
  • the sealing member 7 is a semiconductor package of the semiconductor device A1. As shown in FIGS. 1 to 11, the sealing member 7 covers each component of the semiconductor device A1. However, the support member 2, the pair of input terminals 51, the pair of output terminals 52, the plurality of control terminals 53, and the plurality of detection terminals 54 each partially cover each of them.
  • the constituent material of the sealing member 7 is, for example, an epoxy resin.
  • the sealing member 7 has, for example, a dimension in the x direction of 20 mm or more and 120 mm or less (preferably 25 mm or more and 60 mm or less), a dimension in the y direction of 20 mm or more and 120 mm or less (preferably 40 mm or more and 70 mm or less), and a z direction. The size of is 5 mm or more and 10 mm or less (preferably 7 mm).
  • the sealing member 7 has a main surface 71, a back surface 72, a plurality of side surfaces 731 to 734, and a pair of mounting holes 74.
  • the main surface 71 and the back surface 72 are separated from each other in the z direction as shown in FIGS. 5 to 7.
  • the main surface 71 faces the z2 direction
  • the back surface 72 faces the z1 direction.
  • the back surface 72 has a frame shape surrounding the back surface 212 of the insulating substrate 21 in a plan view.
  • the back surface 212 of the insulating substrate 21 is exposed from the back surface 72.
  • Each of the plurality of side surfaces 731 to 734 is sandwiched between the main surface 71 and the back surface 72 in the z direction, and is connected to both of them. As shown in FIG. 3, the side surfaces 731 and 732 are separated in the x direction.
  • the side surface 731 faces the x1 direction, and the side surface 732 faces the x2 direction. As shown in FIG. 3, the side surfaces 733 and 734 are separated in the y direction. The side surface 733 faces the y1 direction, and the side surface 734 faces the y2 direction.
  • Each terminal portion 542 of the terminal 54 is exposed.
  • Each terminal portion 542 of the detection terminal 54 of the above is exposed.
  • each of the pair of mounting holes 74 is connected from the main surface 71 to the back surface 72 in the z direction and penetrate the sealing member 7.
  • each of the pair of mounting holes 74 has, for example, a circular shape in a plan view.
  • the pair of mounting holes 74 are located on both sides of the insulating substrate 21 in the y direction.
  • the separation distance of the pair of mounting holes 74 in the y direction is, for example, 15 mm or more and 100 mm or less (preferably 30 mm or more and 70 mm or less).
  • the pair of mounting holes 74 can be used when mounting the semiconductor device A1 on the heat sink.
  • the semiconductor element 10, the support member 2, and the metal member 30 are provided.
  • the semiconductor element 10 is bonded to the metal member 30 by the first bonding layer 41, and the metal member 30 is bonded to the support member 2 by the second bonding layer 42.
  • the metal member 30 is a porous body in which a plurality of pores 31 are formed. According to this configuration, when the metal member 30 thermally expands due to the heat from the semiconductor element 10, thermal strain is generated in the vicinity of the plurality of pores 31, so that the thermal stress in the vicinity of the plurality of pores 31 is locally relaxed. To.
  • the thermal stress due to the thermal expansion of the metal member 30 can be relaxed, for example, the thermal stress applied to the second bonding layer 42 in contact with the metal member 30 can be relaxed, and the cohesive failure of the second bonding layer 42 can be suppressed. .. That is, the semiconductor device A1 can improve the reliability because the occurrence of product failures such as poor bonding and poor conduction is suppressed. Further, since the semiconductor device A1 can also relax the thermal stress applied to the first bonding layer 41 in contact with the metal member 30, it is possible to suppress the cohesive failure of the first bonding layer 41.
  • the thickness of each metal member 30 is larger than the thickness of the support member 2 and is 0.5 mm or more and 5 mm or less (preferably 1.0 mm or more and 3 mm or less).
  • the thermal stress can be relaxed by making the thickness of each metal member smaller than the thickness of the metal member 30 to lower the rigidity of the metal member. Is.
  • a method of thinning the metal member the metal member is warped, the sealing member 7 enters between the metal member and the support member 2, and the support member 2 is damaged (broken). )there is a possibility.
  • the method of thinning the metal member may reduce the heat diffusion efficiency of the metal member.
  • the rigidity of the metal member 30 is lowered by using the porous metal member 30 in which the plurality of pores 31 are formed. Therefore, the semiconductor device A1 can relieve the thermal stress applied to the second bonding layer 42 while suppressing the damage of the support member 2 and the decrease in the heat diffusion efficiency.
  • the occupancy rate of the plurality of pores 31 with respect to the metal member 30 is 10% or more and 70% or less.
  • this occupancy rate is larger than 70% (the maximum value in the above-mentioned occupancy rate range)
  • the first bonding layer 41 and the second bonding layer 42 are absorbed by the plurality of pores 31, and the semiconductor element.
  • the joining of the 10 and the metal member 30 becomes insufficient.
  • this occupancy rate is smaller than 10% (the minimum value in the above-mentioned occupancy rate range)
  • the thermal stress in the vicinity of a large number of pores 31 is insufficiently relaxed, and the thermal stress cannot be moderately relaxed.
  • the occupancy rate to 10% or more and 70% or less as described above, the bonding strength between the semiconductor element 10 and the metal member 30 and the bonding strength between the support member 2 (wiring layer 22) and the metal member 30 are ensured. , The thermal stress caused by the metal member 30 can be appropriately relaxed.
  • a part of the plurality of pores 31 is filled with the sealing member 7.
  • the region of the main surface 301 that is not in contact with the first bonding layer 41 and the plurality of pores 31 appearing in the entire regions of the side surfaces 303 and 304 are sealed.
  • the member 7 is filled.
  • the adhesion between each metal member 30 and the sealing member 7 can be improved by the anchor effect.
  • the thermal stress is relatively larger than in the vicinity of the pores 31 filled with air, but compared to the case where the pores 31 are not formed.
  • the thermal stress can be made relatively small. That is, even if some of the pores 31 are filled with the sealing member 7, the thermal stress can be qualitatively relaxed. Therefore, the semiconductor device A1 can improve the adhesion of the sealing member 7 while alleviating the thermal stress.
  • the support member 2 includes an insulating substrate 21.
  • the insulating substrate 21 is made of ceramics having a relatively high thermal conductivity. According to this configuration, the heat generated by the semiconductor element 10 is thermally diffused by the metal member 30 and transferred to the insulating substrate 21. Therefore, in the semiconductor device A1, the heat from the semiconductor element 10 is diffused to the metal member 30 and the insulating substrate 21, so that the heat dissipation efficiency of the semiconductor element 10 can be improved. Further, the back surface 212 of the insulating substrate 21 is exposed from the sealing member 7. According to this configuration, the heat transferred to the insulating substrate 21 is released to the outside from the back surface 212. When a heat sink is attached to the semiconductor device A1, the heat sink is transmitted from the back surface 212 to the heat sink. Therefore, the semiconductor device A1 can efficiently dissipate heat generated from the semiconductor element 10.
  • FIG. 15 shows the semiconductor device A2 according to the second embodiment.
  • FIG. 15 is a plan view showing the semiconductor device A2, and the sealing member 7 is shown by an imaginary line (dashed-dotted line).
  • the semiconductor device A2 is mainly different from the semiconductor device A1 in the configuration of the plurality of wiring layers 22 of the support member 2, and accordingly, the plurality of semiconductor elements 10, the plurality of metal members 30, and a pair of inputs.
  • the arrangement of the terminals 51, the pair of output terminals 52, the plurality of control terminals 53, the plurality of detection terminals 54, the plurality of connecting members 6, and the like are also different.
  • the plurality of wiring layers 22 of the support member 2 include a first wiring layer 22A, a pair of second wiring layers 22B, a third wiring layer 22C, and a fourth wiring layer 22D. Therefore, unlike the semiconductor device A1, the semiconductor device A2 has one first wiring layer 22A and further includes a fourth wiring layer 22D.
  • the first wiring layer 22A is located on the x2 direction side and the y2 direction side of the insulating substrate 21.
  • the pair of second wiring layers 22B are located on the x1 direction side and the y1 direction side of the insulating substrate 21.
  • the pair of second wiring layers 22B are adjacent to each other in the y direction.
  • the third wiring layer 22C is located on the x2 direction side and the y1 direction side.
  • the third wiring layer 22C is located next to the first wiring layer 22A in the y direction.
  • the third wiring layer 22C and the first wiring layer 22A have substantially the same shape.
  • the fourth wiring layer 22D is located on the x1 direction side and the y2 direction side.
  • the fourth wiring layer 22D is located next to the first wiring layer 22A in the x direction.
  • the fourth wiring layer 22D has substantially the same shape as one of the pair of second wiring layers 22B.
  • the plurality of metal members 30 include a first metal member 30A, a pair of second metal members 30B, a third metal member 30C, and a fourth metal member 30D. Therefore, unlike the semiconductor device A1, the semiconductor device A2 has one first metal member 30A and further includes a fourth metal member 30D.
  • the first metal member 30A is joined to the first wiring layer 22A by the second joining layer 42.
  • Two first elements 10A are joined to the first metal member 30A by a first joining layer 41, respectively. Therefore, in the present embodiment, two semiconductor elements 10 (first element 10A) are joined to one metal member 30 (first metal member 30A).
  • the pair of second metal members 30B each have a pair of second elements 10B bonded by the first bonding layer 41. None of the plurality of semiconductor elements 10 is joined to the fourth metal member 30D. A plurality of first wires 611 and a first conductive member 621 are joined to the fourth metal member 30D.
  • the first conductive member 621 is joined to one of the fourth metal member 30D and the pair of second metal members 30B, and these are conductive.
  • the pair of input terminals 51 are located on the x2 direction side as shown in FIG. Further, the pair of input terminals 51 are separated in the y direction, the first input terminal 51A is located in the y2 direction, and the second input terminal 51B is located in the y1 direction.
  • the first input terminal 51A is conductive to the second electrode 12 of each first element 10A via the second conductive member 622 and the first metal member 30A.
  • the second input terminal 51B is conductive to the first electrode 11 of each second element 10B via the third conductive member 623, the third metal member 30C, and the plurality of second wires 612.
  • the pair of output terminals 52 are located on the x1 direction side as shown in FIG.
  • the output terminal 52 on the y1 direction side conducts to one of the second electrodes 12 of the pair of second elements 10B via the fourth conductive member 624 and the second metal member 30B, and also conducts the fourth conduction. It conducts to one of the first electrodes 11 of the pair of first elements 10A via the member 624, the second metal member 30B, the first conductive member 621, the fourth metal member 30D, and the plurality of first wires 611.
  • the output terminal 52 on the y2 direction side conducts to the other second electrode 12 of the pair of second elements 10B via the fourth conductive member 624 and the second metal member 30B, and the fourth conductive member 624, It conducts to the other first electrode 11 of the pair of first elements 10A via the second metal member 30B and the plurality of first wires 611.
  • the semiconductor device A2 includes a control terminal 53 partially protruding from the side surface 731 and a control terminal 53 partially protruding from the side surface 732.
  • the control terminal 53 part of which protrudes from the side surface 731, is electrically connected to the third electrode 13 of each first element 10A via the plurality of third wires 613.
  • the control terminal 53 part of which protrudes from the side surface 732, is electrically connected to the third electrode 13 of each second element 10B via the plurality of third wires 613.
  • two control terminals 53 are provided, one control terminal 53 is common to the pair of first elements 10A, and the other control terminal 53 is common to the pair of second elements 10B. Indicates a case, but is not limited to this.
  • four control terminals 53 corresponding to a plurality of semiconductor elements 10 (a pair of first elements 10A and a pair of second elements 10B) may be provided.
  • the semiconductor device A2 includes a detection terminal 54 partially protruding from the side surface 731 and a detection terminal 54 partially protruding from the side surface 732.
  • the detection terminal 54, part of which protrudes from the side surface 732, is conducted to the first electrode 11 of any one of the pair of first elements 10A via the fourth wire 614. Further, the detection terminal 54, part of which protrudes from the side surface 731, is conducted to the first electrode 11 of any one of the pair of second elements 10B via the fourth wire 614.
  • two detection terminals 54 are provided, one detection terminal 54 conducts to one of the pair of first elements 10A, and the other detection terminal 54 conducts to any of the pair of second elements 10B.
  • the present invention is not limited to this.
  • four detection terminals 54 corresponding to a plurality of semiconductor elements 10 (a pair of first elements 10A and a pair of second elements 10B) may be provided.
  • the semiconductor element 10, the support member 2, and the metal member 30 are provided.
  • the semiconductor element 10 is bonded to the metal member 30 by the first bonding layer 41, and the metal member 30 is bonded to the support member 2 by the second bonding layer 42.
  • the metal member 30 is a porous body in which a plurality of pores 31 are formed. Therefore, similarly to the semiconductor device A1, the semiconductor device A2 can relieve the thermal stress applied to the second bonding layer 42 in contact with the metal member 30, so that the cohesive failure of the second bonding layer 42 can be suppressed. That is, the semiconductor device A2 can improve the reliability because the occurrence of product failures such as poor bonding and poor conduction is suppressed.
  • the same effect as that of the semiconductor device A1 can be obtained by the same or similar configuration as that of the semiconductor device A1.
  • each metal member 30 is joined to each wiring layer 22 by the second joining layer 42 , but the present invention is not limited to this.
  • each metal member 30 may be bonded to the insulating substrate 21 by a second bonding layer 42. That is, the support member 2 does not have to include the plurality of wiring layers 22. Even in this case, the thermal stress applied to the second bonding layer 42 in contact with the metal member 30 can be relaxed.
  • the case where the first input terminal 51A is conducting to the first metal member 30A via the second conductive member 622 is shown, but the first input terminal 51A is the first metal. They may be directly joined to the member 30A so as to be conductive.
  • the case where the second input terminal 51B is conducting to the third metal member 30C via the third conductive member 623 is shown, but the second input terminal 51B is directly joined to the third metal member 30C to these. May be conducting.
  • each output terminal 52 is conducting to each second metal member 30B via the fourth conductive member 624 is shown, each output terminal 52 is directly joined to each second metal member 30B, and this is It may be conducting.
  • FIG. 16 and 17 show the semiconductor device A3 according to the third embodiment.
  • FIG. 16 is a plan view showing the semiconductor device A3, and the sealing member 7 is shown by an imaginary line (dashed line).
  • FIG. 17 is a cross-sectional view taken along the line XVII-XVII of FIG.
  • the semiconductor device A3 is a so-called TO (Transistor Outline) package type.
  • the support member 2 is a so-called lead frame.
  • the constituent material of the support member 2 is, for example, copper or a copper alloy.
  • the support member 2 includes a die pad portion 251, a plurality of inner lead portions 252, and a plurality of outer lead portions 253.
  • a metal member 30 is joined to the die pad portion 251, and the semiconductor element 10 is mounted via the metal member 30.
  • the die pad portion 251 is covered with the sealing member 7 except for the surface of the die pad portion 251 facing the z1 direction. That is, the surface of the die pad portion 251 facing the z1 direction is exposed from the sealing member 7.
  • Each of the plurality of inner lead portions 252 is a portion that is separated from the die pad portion 251 and is covered with the sealing member 7. One end of each connecting member 6 is joined to each inner lead portion 252.
  • the support member 2 in the semiconductor device A3 includes two inner lead portions 252.
  • Each of the plurality of outer lead portions 253 is a portion connected to any of the plurality of inner lead portions 252 and exposed from the sealing member 7.
  • the plurality of outer lead portions 253 are terminals of the semiconductor device A3 and can be joined to a wiring board such as an electric product.
  • Each of the plurality of connecting members 6 is a bonding wire.
  • each connecting member 6 may use a metal lead, a bonding ribbon, or the like instead of the bonding wire.
  • the semiconductor device A3 includes two connecting members 6.
  • the number of connecting members 6 is not particularly limited. As shown in FIG. 16, one of the two connecting members 6 is joined to the third electrode 13 of the semiconductor element 10 and one of the two inner lead portions 252 to conduct them. The other of the two connecting members 6 is joined to the first electrode 11 of the semiconductor element 10 and the other of the two inner lead portions 252 to conduct them.
  • the semiconductor element 10 the support member 2, and the metal member 30 are provided.
  • the semiconductor element 10 is bonded to the metal member 30 by the first bonding layer 41, and the metal member 30 is bonded to the support member 2 by the second bonding layer 42.
  • the metal member 30 is a porous body in which a plurality of pores 31 are formed. Therefore, similarly to the semiconductor device A1, the semiconductor device A3 can relax the thermal stress applied to the second bonding layer 42 in contact with the metal member 30, so that the cohesive failure of the second bonding layer 42 can be suppressed. That is, the semiconductor device A3 can improve the reliability because the occurrence of product failures such as poor bonding and poor conduction is suppressed.
  • the same effect as that of the semiconductor device A1 (A2) can be obtained by the same or similar configuration as that of the semiconductor device A1 (A2).
  • the semiconductor device A3 is a so-called TO package type, but the present invention is not limited to this, and the SOP (Small Outline Package), Non-Lead package, or BGA (Ball Grid Array) package is used. It can be applied to various types of semiconductor packages.
  • the support member 2 is a lead frame
  • the present invention is not limited to this, and the support member 2 is an interposer, a printed circuit board, a DBC (Direct Bonded Copper) board, a DBA (Direct Bonded Aluminum) board, or the like. May be good.
  • DBC Direct Bonded Copper
  • DBA Direct Bonded Aluminum
  • FIGS. 18 to 24 show each modification of the metal member 30.
  • the metal members 30 shown in FIGS. 18 to 24 can be used in place of the metal members 30 in the semiconductor devices A1 to A3.
  • the plurality of pores 31 include a plurality of first through holes 31A, a plurality of second through holes 31B, and a plurality of third through holes 31C.
  • Each of the plurality of first through holes 31A is connected in the z direction from the main surface 301 to the back surface 302.
  • the plurality of first through holes 31A (part of the plurality of pores 31) appear on the main surface 301 and the back surface 302.
  • the penetration direction of each first through hole 31A is not limited to a linear shape along the z direction, and may be bent or curved, may be inclined, and all of the first through holes 31A may be inclined.
  • the penetration directions may or may not be aligned.
  • the plurality of first through holes 31A are arranged irregularly, for example, in a plan view.
  • the plurality of first through holes 31A are not irregularly arranged, but are regularly arranged, for example, in a square lattice shape, a rectangular lattice shape, a triangular lattice shape, a hexagonal lattice shape, or an orthorhombic lattice shape. It may have been done.
  • Each first through hole 31A corresponds to the "first hole" described in the claims.
  • Each of the plurality of second through holes 31B is connected in the x direction from one of the pair of side surfaces 303 to the other.
  • the plurality of second through holes 31B (part of the plurality of pores 31) appear on each of the pair of side surfaces 303.
  • the penetration direction of each of the second through holes 31B is not limited to a straight line along the x direction, may be bent or curved, may be inclined with respect to the x direction, or all.
  • the penetration directions of the second through holes 31B may or may not be aligned.
  • the plurality of second through holes 31B are arranged irregularly, for example, when viewed in the x direction.
  • the plurality of second through holes 31B are not arranged irregularly, but are arranged regularly, for example, in a square lattice shape, a rectangular lattice shape, a triangular lattice shape, a hexagonal lattice shape, or an orthorhombic lattice shape. It may have been done.
  • Each second through hole 31B corresponds to the "second hole" described in the claims.
  • Each of the plurality of third through holes 31C is connected in the y direction from one of the pair of side surfaces 304 to the other.
  • the plurality of third through holes 31C (part of the plurality of pores 31) appear on each of the pair of side surfaces 304.
  • the penetration direction of each third through hole 31C is not limited to a straight line along the y direction, may be bent or curved, may be inclined with respect to the y direction, and all the third through holes 31C.
  • the penetration directions of the three through holes 31C may or may not be aligned.
  • the plurality of third through holes 31C are arranged irregularly, for example, when viewed in the y direction.
  • the plurality of third through holes 31C are not arranged irregularly, but are arranged regularly, for example, in a square lattice shape, a rectangular lattice shape, a triangular lattice shape, a hexagonal lattice shape, or an orthorhombic lattice shape. It may have been done.
  • Each third through hole 31C corresponds to the "third hole" described in the claims.
  • the plurality of pores 31 do not include the plurality of first through holes 31A and the plurality of second through holes 31B, but include the plurality of third through holes 31C.
  • FIG. 19 shows a case where the plurality of pores 31 include a plurality of third through holes 31C, a configuration may include a plurality of second through holes 31B instead of these. ..
  • the plurality of pores 31 do not include the plurality of first through holes 31A, but include the plurality of second through holes 31B and the plurality of third through holes 31C.
  • the plurality of pores 31 do not include the plurality of second through holes 31B and the plurality of third through holes 31C, but include the plurality of first through holes 31A.
  • a plurality of first through holes 31A are provided in a portion of the main surface 301 of the metal member 30 to which the semiconductor element 10 is joined (a portion overlapping the semiconductor element 10 in a plan view). Not formed.
  • FIG. 22 shows a case where the metal member 30 shown in FIG. 21 is provided with a region in which a plurality of first through holes 31A are not formed, but the present invention is not limited to this, and the metal member 30 shown in FIG. 18 is not limited to this. Similarly, a region in which a plurality of first through holes 31A are not formed may be provided.
  • the occupancy rate of the plurality of pores 31 is, for example, 10% or more and 70% or less.
  • a plurality of pores 31 (a plurality of first through holes 31A, a plurality of second through holes 31B, and a plurality of third through holes 31C). Since thermal strain of the metal member 30 is generated in the vicinity due to heat generation of the semiconductor element 10, the thermal stress in the vicinity of each pore 31 is relaxed. Therefore, since the thermal stress due to the thermal expansion of each metal member 30 can be relaxed, the thermal stress applied to the second bonding layer 42 for joining the metal member 30 to the wiring layer 22 is relaxed, and the second bonding is performed. The cohesive failure of the layer 42 can be suppressed. Therefore, even in the semiconductor device using each of the metal members 30 shown in FIGS. 18 to 22, the occurrence of product failure such as bonding failure and conduction failure is suppressed, so that reliability can be improved.
  • Each of the metal members 30 shown in FIGS. 19 to 22 has a plurality of first through holes 31A, a plurality of second through holes 31B, or a plurality of third through holes 31C, as compared with the metal member 30 shown in FIG.
  • the metal is not formed. Therefore, since the area for diffusing heat is large, it is effective in improving heat dissipation. However, the thermal stress can be relaxed as compared with the metal member in which the plurality of pores 31 are not formed, but the effect of relaxing the thermal stress may be reduced as compared with the metal member 30 shown in FIG. is there.
  • Each of the metal members 30 shown in FIGS. 23 and 24 is formed by compressing a metal wire using, for example, a predetermined mold, in a complicatedly bent state.
  • the constituent material of this metal wire is, for example, copper or a copper alloy.
  • each metal member 30 may be composed of one metal wire, or may be composed of a plurality of metal wires.
  • FIG. 23 shows a case where a rectangular parallelepiped-shaped mass is formed
  • FIG. 24 shows a case where an annular mass is formed.
  • the metal member 30 according to this modification is not limited to a rectangular parallelepiped shape or an annular shape, and may be a cube shape or a columnar shape.
  • a plurality of spaces are incorporated in the gaps between the metal wires that are intricately intertwined.
  • Each metal member 30 having such a structure is a porous body in which a plurality of pores 31 are formed.
  • the semiconductor device according to the present disclosure is not limited to the above-described embodiment.
  • the specific configuration of each part of the semiconductor device of the present disclosure can be freely redesigned.
  • the semiconductor device includes embodiments relating to the following appendices.
  • Appendix 1 Support members and A metal member having a first main surface and a first back surface separated in the thickness direction, with the first back surface facing the support member and joined to the support member.
  • a bonding layer that joins the support member and the metal member, A semiconductor element facing the first main surface and bonded to the metal member,
  • the metal member is a semiconductor device which is a porous body in which a plurality of pores are formed.
  • Appendix 2 The semiconductor device according to Appendix 1, wherein the plurality of pores are irregularly arranged.
  • [Appendix 6] The semiconductor device according to Appendix 5, wherein the second hole is a through hole that connects one to the other of the pair of first side surfaces in the first direction.
  • the metal member has a pair of second sides separated in a second direction orthogonal to both the thickness direction and the first direction.
  • the semiconductor device according to Appendix 5 or Appendix 6, wherein the plurality of pores have a third hole appearing on at least one of the pair of second side surfaces.
  • [Appendix 8] The semiconductor device according to Appendix 7, wherein the third hole is a through hole that connects one to the other of the pair of second side surfaces in the second direction.
  • the semiconductor device according to any one of Appendix 1 to Appendix 8, wherein the occupancy of the plurality of pores with respect to the metal member is 10% or more and 70% or less.
  • the support member includes an insulating substrate and a wiring layer.
  • the wiring layer has a second main surface and a second back surface separated in the thickness direction, and the second back surface is joined to the insulating substrate.
  • the semiconductor device according to any one of Supplementary note 1 to Supplementary note 9, wherein the metal member has a first back surface facing the second main surface and is joined to the wiring layer.
  • [Appendix 11] The semiconductor device according to Appendix 10, wherein the back surface of the insulating substrate is exposed from the sealing member.
  • [Appendix 12] The semiconductor device according to any one of Supplementary note 1 to Supplementary note 11, wherein the bonding layer is solder.
  • [Appendix 13] The semiconductor device according to any one of Supplementary note 1 to Supplementary note 12, wherein the semiconductor element is bonded to the metal member by a conductive bonding material.
  • [Appendix 14] The semiconductor device according to any one of Supplementary note 1 to Supplementary note 13, wherein some of the pores of the plurality of pores are filled with the sealing member.
  • [Appendix 15] The semiconductor device according to Appendix 14, wherein the plurality of pores are pores except for a part of the pores filled with the sealing member.
  • [Appendix 16] The semiconductor device according to any one of Appendix 1 to Appendix 15, wherein the constituent material of the metal member is copper or a copper alloy.
  • Appendix 17] The semiconductor device according to any one of Supplementary note 1 to Supplementary note 16, wherein the thickness of the metal member is larger than the thickness of the support member.
  • Appendix 18] The semiconductor device according to any one of Supplementary note 1 to Supplementary note 17, wherein the thickness of the metal member is 0.5 mm or more and 5 mm or less.

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Abstract

A semiconductor device A1 according to the present disclosure comprises: a support member 2; a metal member 30 which has a main surface 301 and a rear surface 302 separated from each other in a Z direction and the rear surface 302 facing the support member 2 and joined to the support member 30; a second joining layer 42 that joins the support member 2 and the metal member 30; a semiconductor element 10 that faces the main surface 301 and is joined to the metal member 30; and a sealing member 7 that covers the support member 2, the metal member 30, the second joining layer 42, and the semiconductor element 10. The metal member 30 is a porous body having a plurality of pores 31 formed therein. A semiconductor device having improved reliability by relaxing the thermal stress that occurs during heat generation in a semiconductor element can be provided.

Description

半導体装置Semiconductor device
　本開示は、半導体素子が搭載された半導体装置に関する。 The present disclosure relates to a semiconductor device equipped with a semiconductor element.
　近年、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）やＩＧＢＴ（Insulated Gate Bipolar Transistor）などの半導体素子を搭載した半導体装置が知られている。特許文献１には、半導体素子を搭載した半導体装置の一例が開示されている。特許文献１に記載の半導体装置は、半導体素子、支持部材、熱拡散板、および、封止部材を備えている。半導体素子は、はんだによって、熱拡散板に接合されている。支持部材は、導電パターン、金属板および絶縁樹脂を含んでいる。支持部材は、金属板（たとえばアルミニウム、銅などの金属あるいはその合金）の上面に絶縁樹脂（たとえばセラミックス）が形成されており、当該絶縁樹脂の上に導電パターン（たとえばアルミニウム、銅などの金属あるいはその合金）が形成されている。熱拡散板は、たとえば銅あるいは銅合金からなる板状部材である。熱拡散板は、はんだによって、支持部材の導電パターンに接合されている。封止部材は、半導体素子、支持部材の一部、熱拡散板、および、各はんだを覆っている。 In recent years, semiconductor devices equipped with semiconductor elements such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) have been known. Patent Document 1 discloses an example of a semiconductor device equipped with a semiconductor element. The semiconductor device described in Patent Document 1 includes a semiconductor element, a support member, a heat diffusion plate, and a sealing member. The semiconductor element is bonded to the heat diffusion plate by soldering. The support member includes a conductive pattern, a metal plate and an insulating resin. In the support member, an insulating resin (for example, ceramics) is formed on the upper surface of a metal plate (for example, a metal such as aluminum or copper or an alloy thereof), and a conductive pattern (for example, a metal such as aluminum or copper or a metal thereof) is formed on the insulating resin. The alloy) is formed. The heat diffusion plate is, for example, a plate-shaped member made of copper or a copper alloy. The heat diffusion plate is joined to the conductive pattern of the support member by soldering. The sealing member covers the semiconductor element, a part of the support member, the heat diffusion plate, and each solder.
特開２００８－２９４３９０号公報Japanese Unexamined Patent Publication No. 2008-294390
　半導体装置の通電時に、半導体素子から熱が発生する。このとき、半導体素子の発熱による温度上昇とともに、構成部材の熱膨張差によって、たとえば熱拡散板と支持部材とを接合するはんだに熱応力がかかる。この熱応力は、当該はんだの凝集破壊を引き起こす可能性があり、接合不良や導通不良などの製品故障の原因である。 Heat is generated from the semiconductor element when the semiconductor device is energized. At this time, as the temperature rises due to the heat generated by the semiconductor element, thermal stress is applied to the solder that joins the heat diffusion plate and the support member, for example, due to the difference in thermal expansion of the constituent members. This thermal stress may cause cohesive failure of the solder, and is a cause of product failure such as poor joining and poor continuity.
　本開示は、上記事情に鑑みて考え出されたものであり、その目的は、半導体素子の発熱時の熱応力を緩和することにより、信頼性の向上を図った半導体装置を提供することにある。 The present disclosure has been conceived in view of the above circumstances, and an object thereof is to provide a semiconductor device having improved reliability by relaxing thermal stress at the time of heat generation of a semiconductor element. ..
　本開示の半導体装置は、支持部材と、厚さ方向において離間した第１主面および第１裏面を有し、前記第１裏面が前記支持部材に対向して、前記支持部材に接合された金属部材と、前記支持部材と前記金属部材とを接合する接合層と、前記第１主面に対向し、前記金属部材に接合された半導体素子と、前記支持部材、前記金属部材、前記接合層および前記半導体素子を覆う封止部材と、を備えており、前記金属部材は、複数の細孔が形成された多孔質体である。 The semiconductor device of the present disclosure has a first main surface and a first back surface separated from the support member in the thickness direction, and the first back surface faces the support member and is joined to the support member. A member, a bonding layer that joins the support member and the metal member, a semiconductor element that faces the first main surface and is bonded to the metal member, the support member, the metal member, the bonding layer, and the like. A sealing member for covering the semiconductor element is provided, and the metal member is a porous body in which a plurality of pores are formed.
　本開示の半導体装置によれば、半導体素子の発熱時の熱応力を緩和することができる。よって、半導体装置の信頼性を向上させることができる。 According to the semiconductor device of the present disclosure, the thermal stress at the time of heat generation of the semiconductor element can be relaxed. Therefore, the reliability of the semiconductor device can be improved.
第１実施形態にかかる半導体装置を示す斜視図である。It is a perspective view which shows the semiconductor device which concerns on 1st Embodiment. 第１実施形態にかかる半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on 1st Embodiment. 図２の平面図において、封止部材を想像線（二点鎖線）で示した図である。In the plan view of FIG. 2, the sealing member is shown by an imaginary line (dashed line). 第１実施形態にかかる半導体装置を示す底面図である。It is a bottom view which shows the semiconductor device which concerns on 1st Embodiment. 第１実施形態にかかる半導体装置を示す側面図（右側面図）である。It is a side view (right side view) which shows the semiconductor device which concerns on 1st Embodiment. 第１実施形態にかかる半導体装置を示す側面図（左側面図）である。It is a side view (left side view) which shows the semiconductor device which concerns on 1st Embodiment. 第１実施形態にかかる半導体装置を示す正面図である。It is a front view which shows the semiconductor device which concerns on 1st Embodiment. 図３のＶＩＩＩ－ＶＩＩＩ線に沿う断面図である。FIG. 3 is a cross-sectional view taken along the line VIII-VIII of FIG. 図３のＩＸ－ＩＸ線に沿う断面図である。It is sectional drawing which follows the IX-IX line of FIG. 図３のＸ－Ｘ線に沿う断面図である。It is sectional drawing which follows the XX line of FIG. 図３のＸＩ－ＸＩ線に沿う断面図である。It is sectional drawing which follows the XI-XI line of FIG. 図３の一部を拡大した部分拡大図である。It is a partially enlarged view which enlarged a part of FIG. 図１２のＸＩＩＩ－ＸＩＩＩ線に沿う断面図である。It is sectional drawing which follows the XIII-XIII line of FIG. 第１実施形態にかかる金属部材の断面模式図である。It is sectional drawing of the metal member which concerns on 1st Embodiment. 第２実施形態にかかる半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on 2nd Embodiment. 第３実施形態にかかる半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on 3rd Embodiment. 図１６のＸＶＩＩ－ＸＶＩＩ線に沿う断面図である。16 is a cross-sectional view taken along the line XVII-XVII of FIG. 変形例にかかる金属部材を示す斜視図である。It is a perspective view which shows the metal member which concerns on the modification. 変形例にかかる金属部材を示す斜視図である。It is a perspective view which shows the metal member which concerns on the modification. 変形例にかかる金属部材を示す斜視図である。It is a perspective view which shows the metal member which concerns on the modification. 変形例にかかる金属部材を示す斜視図である。It is a perspective view which shows the metal member which concerns on the modification. 変形例にかかる金属部材を示す斜視図である。It is a perspective view which shows the metal member which concerns on the modification. 変形例にかかる金属部材を示す斜視図である。It is a perspective view which shows the metal member which concerns on the modification. 変形例にかかる金属部材を示す斜視図である。It is a perspective view which shows the metal member which concerns on the modification.
　本開示の半導体装置の好ましい実施の形態について、図面を参照して、以下に説明する。なお、同一あるいは類似の構成には、同一の符号を付して、重複する説明を省略する。 A preferred embodiment of the semiconductor device of the present disclosure will be described below with reference to the drawings. The same or similar configurations are designated by the same reference numerals, and duplicate description will be omitted.
　図１～図１４は、第１実施形態にかかる半導体装置Ａ１を示している。半導体装置Ａ１は、複数の半導体素子１０、支持部材２、複数の金属部材３０、複数の第１接合層４１、複数の第２接合層４２、一対の入力端子５１、一対の出力端子５２、複数の制御端子５３、複数の検出端子５４、複数の接続部材６、および、封止部材７を備えている。 1 to 14 show the semiconductor device A1 according to the first embodiment. The semiconductor device A1 includes a plurality of semiconductor elements 10, a support member 2, a plurality of metal members 30, a plurality of first bonding layers 41, a plurality of second bonding layers 42, a pair of input terminals 51, a pair of output terminals 52, and a plurality of. The control terminal 53, the plurality of detection terminals 54, the plurality of connecting members 6, and the sealing member 7 are provided.
　図１は、半導体装置Ａ１を示す斜視図である。図２は、半導体装置Ａ１を示す平面図である。図３は、図２の平面図において、封止部材７を想像線（二点鎖線）で示した図である。図４は、半導体装置Ａ１を示す底面図である。図５は、半導体装置Ａ１を示す側面図（右側面図）である。図６は、半導体装置Ａ１を示す側面図（左側面図）である。図７は、半導体装置Ａ１を示す正面図である。図８は、図３のＶＩＩＩ－ＶＩＩＩ線に沿う断面図である。図９は、図３のＩＸ－ＩＸ線に沿う断面図である。図１０は、図３のＸ－Ｘ線に沿う断面図である。図１１は、図３のＸＩ－ＸＩ線に沿う断面図である。図１２は、図３の一部を拡大した部分拡大図である。図１３は、図１２のＸＩＩＩ－ＸＩＩＩ線に沿う断面図である。図１４は、金属部材３０の断面模式図である。 FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a plan view showing the semiconductor device A1. FIG. 3 is a plan view of FIG. 2 showing the sealing member 7 as an imaginary line (dashed-dotted line). FIG. 4 is a bottom view showing the semiconductor device A1. FIG. 5 is a side view (right side view) showing the semiconductor device A1. FIG. 6 is a side view (left side view) showing the semiconductor device A1. FIG. 7 is a front view showing the semiconductor device A1. FIG. 8 is a cross-sectional view taken along the line VIII-VIII of FIG. FIG. 9 is a cross-sectional view taken along the line IX-IX of FIG. FIG. 10 is a cross-sectional view taken along the line XX of FIG. FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG. FIG. 12 is a partially enlarged view of a part of FIG. FIG. 13 is a cross-sectional view taken along the line XIII-XIII of FIG. FIG. 14 is a schematic cross-sectional view of the metal member 30.
　説明の便宜上、互いに直交する３つの方向を、ｘ方向、ｙ方向、ｚ方向と定義する。ｚ方向は、半導体装置Ａ１の厚さ方向である。ｘ方向は、半導体装置Ａ１の平面図（図２参照）における左右方向である。ｙ方向は、半導体装置Ａ１の平面図（図２参照）における上下方向である。また、ｘ方向の一方をｘ１方向、ｘ方向の他方をｘ２方向とする。同様に、ｙ方向の一方をｙ１方向、ｙ方向の他方をｙ２方向とし、ｚ方向の一方をｚ１方向、ｚ方向の他方をｚ２方向とする。本開示において、ｚ１方向を下、ｚ２方向を上という場合もある。本実施形態においては、ｘ方向が特許請求の範囲に記載の「第１方向」に相当し、ｙ方向が特許請求の範囲に記載の「第２方向」に相当する。 For convenience of explanation, the three directions orthogonal to each other are defined as the x direction, the y direction, and the z direction. The z direction is the thickness direction of the semiconductor device A1. The x direction is the left-right direction in the plan view (see FIG. 2) of the semiconductor device A1. The y direction is the vertical direction in the plan view (see FIG. 2) of the semiconductor device A1. Further, one in the x direction is defined as the x1 direction, and the other in the x direction is defined as the x2 direction. Similarly, one in the y direction is the y1 direction, the other in the y direction is the y2 direction, one in the z direction is the z1 direction, and the other in the z direction is the z2 direction. In the present disclosure, the z1 direction may be referred to as the lower side, and the z2 direction may be referred to as the upper side. In the present embodiment, the x direction corresponds to the "first direction" described in the claims, and the y direction corresponds to the "second direction" described in the claims.
　半導体装置Ａ１は、たとえば、モータの駆動源、様々な電気製品のインバータ装置、および、様々な電気製品のＤＣ／ＤＣコンバータなどに用いられる電力変換装置（パワーモジュール）である。半導体装置Ａ１は、たとえばハーフブリッジ型のスイッチング回路を構成する。 The semiconductor device A1 is, for example, a power conversion device (power module) used for a drive source of a motor, an inverter device of various electric products, a DC / DC converter of various electric products, and the like. The semiconductor device A1 constitutes, for example, a half-bridge type switching circuit.
　複数の半導体素子１０の各々は、たとえばＭＯＳＦＥＴである。なお、各半導体素子１０は、ＭＯＳＦＥＴに限定されず、ＭＩＳＦＥＴ（Metal-Insulator-Semiconductor FET）を含む電界効果トランジスタ、または、ＩＧＢＴを含むバイポーラトランジスタなどのスイッチング素子であってもよい。あるいは、各半導体素子１０は、スイッチング素子のみならず、ＬＳＩなどのＩＣチップ、ダイオード、コンデンサなどであってもよい。本実施形態においては、各半導体素子１０は、ｎチャネル型のＭＯＳＦＥＴである場合を示すが、ｐチャネル型であってもよい。各半導体素子１０は、ＳｉＣ（炭化ケイ素）を主とする半導体材料を用いて構成されている。なお、当該半導体材料は、ＳｉＣに限定されず、Ｓｉ（シリコン）、ＧａＡｓ（ヒ化ガリウム）、ＧａＮ（窒化ガリウム）、あるいは、Ｇａ2Ｏ3（酸化ガリウム）などであってもよい。 Each of the plurality of semiconductor elements 10 is, for example, a MOSFET. The semiconductor element 10 is not limited to a MOSFET, and may be a switching element such as a field effect transistor including a MISFET (Metal-Insulator-Semiconductor FET) or a bipolar transistor including an IGBT. Alternatively, each semiconductor element 10 may be not only a switching element but also an IC chip such as an LSI, a diode, a capacitor, or the like. In the present embodiment, each semiconductor element 10 shows a case where it is an n-channel type MOSFET, but it may be a p-channel type. Each semiconductor element 10 is configured by using a semiconductor material mainly composed of SiC (silicon carbide). The semiconductor material is not limited to SiC, and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), Ga 2 O 3 (gallium oxide), or the like.
　各半導体素子１０は、第１接合層４１によって、複数の金属部材３０のいずれかに接合される。各半導体素子１０は、たとえば、ｚ方向に見て（以下、「平面視」ともいう。）、矩形状である。 Each semiconductor element 10 is bonded to any of a plurality of metal members 30 by the first bonding layer 41. Each semiconductor element 10 has a rectangular shape when viewed in the z direction (hereinafter, also referred to as “planar view”).
　各半導体素子１０は、図１３に示すように、主面１０１および裏面１０２を有する。主面１０１および裏面１０２は、ｚ方向において、互いに離間する。主面１０１は、ｚ２方向を向き、裏面１０２は、ｚ１方向を向く。裏面１０２は、第１接合層４１に接しており、かつ、複数の金属部材３０のいずれかに対向する。 As shown in FIG. 13, each semiconductor element 10 has a main surface 101 and a back surface 102. The main surface 101 and the back surface 102 are separated from each other in the z direction. The main surface 101 faces the z2 direction, and the back surface 102 faces the z1 direction. The back surface 102 is in contact with the first bonding layer 41 and faces any of the plurality of metal members 30.
　各半導体素子１０は、図１２および図１３に示すように、第１電極１１、第２電極１２、第３電極１３および絶縁膜１４を有する。 As shown in FIGS. 12 and 13, each semiconductor element 10 has a first electrode 11, a second electrode 12, a third electrode 13, and an insulating film 14.
　第１電極１１は、各半導体素子１０において、ｚ方向の主面１０１側に配置されている。第１電極１１は、当該半導体素子１０の主面１０１において露出する。第１電極１１は、たとえばソース電極であって、ソース電流が流れる。第１電極１１は、図１２に示すように、たとえば４つに分割された構成となっている。 The first electrode 11 is arranged on the main surface 101 side in the z direction in each semiconductor element 10. The first electrode 11 is exposed on the main surface 101 of the semiconductor element 10. The first electrode 11 is, for example, a source electrode through which a source current flows. As shown in FIG. 12, the first electrode 11 has, for example, a configuration divided into four.
　第２電極１２は、各半導体素子１０において、ｚ方向の裏面１０２側に配置されている。第２電極１２は、当該半導体素子１０の裏面１０２において露出する。第２電極１２は、たとえばドレイン電極であって、ドレイン電流が流れる。 The second electrode 12 is arranged on the back surface 102 side in the z direction in each semiconductor element 10. The second electrode 12 is exposed on the back surface 102 of the semiconductor element 10. The second electrode 12 is, for example, a drain electrode through which a drain current flows.
　第３電極１３は、各半導体素子１０において、ｚ方向の主面１０１側に配置されている。第３電極１３は、当該半導体素子１０の主面１０１において露出する。第３電極１３は、たとえばゲート電極であって、半導体素子１０を駆動させるためのゲート電圧（制御電圧）が印加される。平面視において、第３電極１３の大きさは、４つに分割された第１電極１１の１つの部分の大きさよりも小さい。 The third electrode 13 is arranged on the main surface 101 side in the z direction in each semiconductor element 10. The third electrode 13 is exposed on the main surface 101 of the semiconductor element 10. The third electrode 13 is, for example, a gate electrode, and a gate voltage (control voltage) for driving the semiconductor element 10 is applied. In a plan view, the size of the third electrode 13 is smaller than the size of one portion of the first electrode 11 divided into four.
　絶縁膜１４は、各半導体素子１０において、ｚ方向の主面１０１側に配置されている。第３電極１３は、当該半導体素子１０の主面１０１において露出する。絶縁膜１４は、平面視において第１電極１１および第３電極１３をそれぞれ囲んでいる。絶縁膜１４は、第１電極１１と第３電極１３とを絶縁する。絶縁膜１４は、たとえば、ＳｉＯ2（二酸化ケイ素）層、ＳｉＮ4（窒化ケイ素）層、ポリベンゾオキサゾール層がこの順番で積層されたものであり、ポリベンゾオキサゾール層が、各半導体素子１０の主面１０１側の表層である。なお、絶縁膜１４においては、ポリベンゾオキサゾール層に代えてポリイミド層でもよい。 The insulating film 14 is arranged on the main surface 101 side in the z direction in each semiconductor element 10. The third electrode 13 is exposed on the main surface 101 of the semiconductor element 10. The insulating film 14 surrounds the first electrode 11 and the third electrode 13 in a plan view, respectively. The insulating film 14 insulates the first electrode 11 and the third electrode 13. In the insulating film 14, for example, a SiO 2 (silicon dioxide) layer, a SiN 4 (silicon nitride) layer, and a polybenzoxazole layer are laminated in this order, and the polybenzoxazole layer is the main component of each semiconductor element 10. It is a surface layer on the surface 101 side. In the insulating film 14, a polyimide layer may be used instead of the polybenzoxazole layer.
　複数の半導体素子１０は、複数の第１素子１０Ａおよび複数の第２素子１０Ｂを含む。先述のとおり、半導体装置Ａ１はハーフブリッジ型のスイッチング回路を構成する。複数の第１素子１０Ａは、このスイッチング回路における上アーム回路を構成する。複数の第２素子１０Ｂは、このスイッチング回路における下アーム回路を構成する。半導体装置Ａ１は、図３に示すように、２つの（一対の）第１素子１０Ａおよび２つの（一対の）第２素子１０Ｂを含む。なお、半導体素子１０の個数は、本構成に限定されず、半導体装置Ａ１に要求される性能に応じて自在に設定可能である。 The plurality of semiconductor elements 10 include a plurality of first elements 10A and a plurality of second elements 10B. As described above, the semiconductor device A1 constitutes a half-bridge type switching circuit. The plurality of first elements 10A form an upper arm circuit in this switching circuit. The plurality of second elements 10B form a lower arm circuit in this switching circuit. As shown in FIG. 3, the semiconductor device A1 includes two (pair) first elements 10A and two (pair) second elements 10B. The number of semiconductor elements 10 is not limited to this configuration, and can be freely set according to the performance required for the semiconductor device A1.
　支持部材２は、複数の金属部材３０を介して、複数の半導体素子１０を支持する。支持部材２は、絶縁基板２１および複数の配線層２２を含む。 The support member 2 supports a plurality of semiconductor elements 10 via the plurality of metal members 30. The support member 2 includes an insulating substrate 21 and a plurality of wiring layers 22.
　絶縁基板２１は、複数の配線層２２が配置されている。絶縁基板２１は、電気絶縁性を有する。絶縁基板２１の構成材料は、たとえば熱伝導性に優れたセラミックスである。このようなセラミックスとしては、たとえばＡｌＮ（窒化アルミニウム）、ＳｉＮ（窒化ケイ素）、Ａｌ2Ｏ3（酸化アルミニウム）などが挙げられる。絶縁基板２１は、平板状である。絶縁基板２１は、図３に示すように、平面視矩形状である。各絶縁基板２１の厚さ（ｚ方向の寸法）は、０．２ｍｍ以上１．０ｍｍ以下（たとえば０．５ｍｍ）である。 A plurality of wiring layers 22 are arranged on the insulating substrate 21. The insulating substrate 21 has electrical insulation. The constituent material of the insulating substrate 21 is, for example, ceramics having excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride), SiN (silicon nitride), and Al 2 O 3 (aluminum oxide). The insulating substrate 21 has a flat plate shape. As shown in FIG. 3, the insulating substrate 21 has a rectangular shape in a plan view. The thickness (dimension in the z direction) of each insulating substrate 21 is 0.2 mm or more and 1.0 mm or less (for example, 0.5 mm).
　絶縁基板２１は、図８～図１１に示すように、主面２１１および裏面２１２を有する。主面２１１および裏面２１２は、ｚ方向において、互いに離間する。主面２１１は、ｚ２方向を向き、裏面２１２は、ｚ１方向を向く。裏面２１２は、封止部材７から露出する。裏面２１２には、たとえば図示しないヒートシンクなどが接続されうる。なお、絶縁基板２１の構成は、図示したものに限定されず、複数の配線層２２ごとに個別に設けてもよい。 As shown in FIGS. 8 to 11, the insulating substrate 21 has a main surface 211 and a back surface 212. The main surface 211 and the back surface 212 are separated from each other in the z direction. The main surface 211 faces the z2 direction, and the back surface 212 faces the z1 direction. The back surface 212 is exposed from the sealing member 7. For example, a heat sink (not shown) may be connected to the back surface 212. The configuration of the insulating substrate 21 is not limited to that shown in the drawing, and may be provided individually for each of the plurality of wiring layers 22.
　複数の配線層２２はそれぞれ、絶縁基板２１の主面２１１上に形成される。複数の配線層２２は、互いに離間する。各配線層２２は、たとえば銀を含む金属からなる。なお、各配線層２２の構成材料は、銀を含む金属に限定されない。たとえば、銅を含む金属であってもよいし、当該銅を含む金属に銀めっきが施されていてもよい。または、当該銀めっきの代わりに、アルミニウム層、ニッケル層、銀層の順に積層された複数種の金属めっきを施してもよい。複数の配線層２２はいずれも、平面視において、絶縁基板２１の周縁よりも内方に位置する。各配線層２２は平面視矩形状である。各配線層２２は、封止部材７に覆われている。各配線層２２の厚さ（ｚ方向の寸法）は、たとえば５μｍ以上８０μｍ以下である。 Each of the plurality of wiring layers 22 is formed on the main surface 211 of the insulating substrate 21. The plurality of wiring layers 22 are separated from each other. Each wiring layer 22 is made of, for example, a metal containing silver. The constituent material of each wiring layer 22 is not limited to the metal containing silver. For example, it may be a metal containing copper, or the metal containing copper may be silver-plated. Alternatively, instead of the silver plating, a plurality of types of metal plating in which an aluminum layer, a nickel layer, and a silver layer are laminated in this order may be applied. All of the plurality of wiring layers 22 are located inward of the peripheral edge of the insulating substrate 21 in a plan view. Each wiring layer 22 has a rectangular shape in a plan view. Each wiring layer 22 is covered with a sealing member 7. The thickness (dimension in the z direction) of each wiring layer 22 is, for example, 5 μm or more and 80 μm or less.
　複数の配線層２２は、図３に示すように、一対の第１配線層２２Ａ、一対の第２配線層２２Ｂおよび第３配線層２２Ｃを含む。一対の第１配線層２２Ａ、一対の第２配線層２２Ｂおよび第３配線層２２Ｃは、平面視において互いに離間する。 As shown in FIG. 3, the plurality of wiring layers 22 include a pair of first wiring layers 22A, a pair of second wiring layers 22B, and a third wiring layer 22C. The pair of first wiring layers 22A, the pair of second wiring layers 22B, and the third wiring layer 22C are separated from each other in a plan view.
　一対の第１配線層２２Ａは、絶縁基板２１においてｘ１方向側に位置する。一対の第１配線層２２Ａは、ｙ方向において互いに離間している。 The pair of first wiring layers 22A is located on the x1 direction side of the insulating substrate 21. The pair of first wiring layers 22A are separated from each other in the y direction.
　一対の第２配線層２２Ｂは、絶縁基板２１においてｘ２方向側に位置する。一対の第２配線層２２Ｂは、ｙ方向において、互いに離間している。一対の第２配線層２２Ｂは、ｘ方向において、一対の第１配線層２２Ａの隣に位置する。 The pair of second wiring layers 22B are located on the x2 direction side of the insulating substrate 21. The pair of second wiring layers 22B are separated from each other in the y direction. The pair of second wiring layers 22B are located next to the pair of first wiring layers 22A in the x direction.
　第３配線層２２Ｃは、絶縁基板２１においてｘ１方向側に位置する。第３配線層２２Ｃは、一対の第１配線層２２Ａの間に位置する。 The third wiring layer 22C is located on the insulating substrate 21 on the x1 direction side. The third wiring layer 22C is located between the pair of first wiring layers 22A.
　複数の配線層２２（一対の第１配線層２２Ａ、一対の第２配線層２２Ｂおよび第３配線層２２Ｃ）はそれぞれ、主面２２１および裏面２２２を有する。主面２２１および裏面２２２は、ｚ方向において、互いに離間する。主面２２１は、ｚ２方向を向き、裏面２２２は、ｚ１方向を向く。裏面２２２は、各配線層２２が絶縁基板２１に接合された状態において、絶縁基板２１の主面２１１に対向する。主面２２１が特許請求の範囲に記載の「第２主面」に相当し、裏面２２２が特許請求の範囲に記載の「第２裏面」に相当する。 The plurality of wiring layers 22 (a pair of first wiring layers 22A, a pair of second wiring layers 22B, and a third wiring layer 22C) have a main surface 221 and a back surface 222, respectively. The main surface 221 and the back surface 222 are separated from each other in the z direction. The main surface 221 faces the z2 direction, and the back surface 222 faces the z1 direction. The back surface 222 faces the main surface 211 of the insulating substrate 21 in a state where each wiring layer 22 is joined to the insulating substrate 21. The main surface 221 corresponds to the "second main surface" described in the claims, and the back surface 222 corresponds to the "second back surface" described in the claims.
　複数の金属部材３０は、各配線層２２の上にそれぞれ１つずつ配置される。各金属部材３０は、第２接合層４２によって、各配線層２２に接合される。複数の金属部材３０は、第１接合層４１によって、複数の半導体素子１０が接合されている。各金属部材３０の厚さ（ｚ方向の寸法）は、０．５ｍｍ以上５ｍｍ以下（好ましくは１．０ｍｍ以上３ｍｍ以下）である。 A plurality of metal members 30 are arranged one by one on each wiring layer 22. Each metal member 30 is joined to each wiring layer 22 by a second joining layer 42. A plurality of semiconductor elements 10 are bonded to the plurality of metal members 30 by the first bonding layer 41. The thickness (dimension in the z direction) of each metal member 30 is 0.5 mm or more and 5 mm or less (preferably 1.0 mm or more and 3 mm or less).
　複数の金属部材３０は、図３に示すように、一対の第１金属部材３０Ａ、一対の第２金属部材３０Ｂおよび第３金属部材３０Ｃを含む。一対の第１金属部材３０Ａ、一対の第２金属部材３０Ｂおよび第３金属部材３０Ｃは、平面視において互いに離間する。 As shown in FIG. 3, the plurality of metal members 30 include a pair of first metal members 30A, a pair of second metal members 30B, and a third metal member 30C. The pair of first metal members 30A, the pair of second metal members 30B, and the third metal member 30C are separated from each other in a plan view.
　一対の第１金属部材３０Ａは、図３および図１０に示すように、一対の第１配線層２２Ａの上にそれぞれ配置されている。各第１金属部材３０Ａの上にはそれぞれ、各第１素子１０Ａがそれぞれ接合される。 As shown in FIGS. 3 and 10, the pair of first metal members 30A are arranged on the pair of first wiring layers 22A, respectively. Each of the first elements 10A is bonded onto each of the first metal members 30A.
　一対の第２金属部材３０Ｂは、図３、図８および図９に示すように、一対の第２配線層２２Ｂの上にそれぞれ配置されている。各第２金属部材３０Ｂの上にはそれぞれ、各第２素子１０Ｂがそれぞれ接合されている。 The pair of second metal members 30B are arranged on the pair of second wiring layers 22B, respectively, as shown in FIGS. 3, 8 and 9. Each of the second elements 10B is bonded onto each of the second metal members 30B.
　第３金属部材３０Ｃは、図３、図９および図１０に示すように、第３配線層２２Ｃの上に配置されている。第３金属部材３０Ｃには、複数の半導体素子１０のいずれも接合されていない。なお、第３金属部材３０Ｃには複数の半導体素子１０のいずれも接合されないため、半導体装置Ａ１は第３金属部材３０Ｃを備えていなくてもよい。 The third metal member 30C is arranged on the third wiring layer 22C as shown in FIGS. 3, 9 and 10. None of the plurality of semiconductor elements 10 are bonded to the third metal member 30C. Since none of the plurality of semiconductor elements 10 are bonded to the third metal member 30C, the semiconductor device A1 does not have to include the third metal member 30C.
　複数の金属部材３０（一対の第１金属部材３０Ａ、一対の第２金属部材３０Ｂおよび第３金属部材３０Ｃ）はそれぞれ、図８～図１１および図１３に示すように、主面３０１、裏面３０２、一対の側面３０３および一対の側面３０４を有する。 As shown in FIGS. 8 to 11 and 13, the plurality of metal members 30 (a pair of first metal members 30A, a pair of second metal members 30B, and a third metal member 30C) have a main surface 301 and a back surface 302, respectively. Has a pair of side surfaces 303 and a pair of side surfaces 304.
　主面３０１および裏面３０２は、ｚ方向において、互いに離間する。主面３０１は、ｚ２方向を向き、裏面３０２は、ｚ１方向を向く。主面３０１は、各半導体素子１０が各金属部材３０に接合された状態において、各半導体素子１０の主面１０１に対向する。裏面３０２は、各金属部材３０が各配線層２２に接合された状態において、各配線層２２の主面２２１に対向する。主面３０１が特許請求の範囲に記載の「第１主面」に相当し、裏面３０２が特許請求の範囲に記載の「第１裏面」に相当する。 The main surface 301 and the back surface 302 are separated from each other in the z direction. The main surface 301 faces the z2 direction, and the back surface 302 faces the z1 direction. The main surface 301 faces the main surface 101 of each semiconductor element 10 in a state where each semiconductor element 10 is joined to each metal member 30. The back surface 302 faces the main surface 221 of each wiring layer 22 in a state where each metal member 30 is joined to each wiring layer 22. The main surface 301 corresponds to the "first main surface" described in the claims, and the back surface 302 corresponds to the "first back surface" described in the claims.
　一対の側面３０３は、ｚ方向において、主面３０１および裏面３０２の両方に繋がり、かつ、これらに挟まれている。一対の側面３０３は、ｘ方向において離間し、かつ、互いに反対側を向く。一対の側面３０４は、ｚ方向において、主面３０１および裏面３０２の両方に繋がり、かつ、これらに挟まれている。一対の側面３０４は、ｙ方向において離間し、かつ、互いに反対側を向く。側面３０３が特許請求の範囲に記載の「第１側面」に相当し、側面３０４が特許請求の範囲に記載の「第２側面」に相当する。 The pair of side surfaces 303 are connected to both the main surface 301 and the back surface 302 in the z direction, and are sandwiched between them. The pair of side surfaces 303 are separated in the x direction and face opposite to each other. The pair of side surfaces 304 are connected to and sandwiched between the main surface 301 and the back surface 302 in the z direction. The pair of side surfaces 304 are separated in the y direction and face opposite to each other. The side surface 303 corresponds to the "first side surface" described in the claims, and the side surface 304 corresponds to the "second side surface" described in the claims.
　複数の金属部材３０（一対の第１金属部材３０Ａ、一対の第２金属部材３０Ｂおよび第３金属部材３０Ｃ）はそれぞれ、図１４に示すように、複数の細孔３１が形成された多孔質体である。各金属部材３０に対する複数の細孔３１の占有率は、たとえば１０％以上７０％以下である。また、各金属部材３０の構成材料は、銅あるいは銅合金である。 As shown in FIG. 14, each of the plurality of metal members 30 (a pair of first metal members 30A, a pair of second metal members 30B and a third metal member 30C) is a porous body in which a plurality of pores 31 are formed. Is. The occupancy rate of the plurality of pores 31 with respect to each metal member 30 is, for example, 10% or more and 70% or less. The constituent material of each metal member 30 is copper or a copper alloy.
　複数の細孔３１は、図１３および図１４に示すように、不規則に配置されている。複数の細孔３１には、主面３０１に表れたもの、裏面３０２に表れたもの、各側面３０３に表れたもの、各側面３０４に表れたものがある。これらにおいて、封止部材７に接する主面３０１、裏面３０２および各側面３０３，３０４に繋がる細孔３１には、封止部材７が充填されている。たとえば、図１４には、主面３０１に表れた細孔３１に封止部材７が充填された様子が示されている。また、複数の細孔３１には、各金属部材３０の内方に形成されたものがある。この各金属部材３０の内方に形成された細孔３１は、気体（たとえば空気）が充填された気孔である。 The plurality of pores 31 are irregularly arranged as shown in FIGS. 13 and 14. The plurality of pores 31 include those appearing on the main surface 301, those appearing on the back surface 302, those appearing on each side surface 303, and those appearing on each side surface 304. In these, the sealing member 7 is filled in the pores 31 connected to the main surface 301, the back surface 302, and the side surfaces 303, 304 in contact with the sealing member 7. For example, FIG. 14 shows how the sealing member 7 is filled in the pores 31 appearing on the main surface 301. Further, some of the plurality of pores 31 are formed inside each metal member 30. The pores 31 formed inside each of the metal members 30 are pores filled with gas (for example, air).
　本実施形態においては、複数の細孔３１のうち、主面３０１に表れたもの、各側面３０３に表れたもの、そして、各側面３０４に表れたものが、特許請求の範囲に記載の「第１孔」、「第２孔」そして「第３孔」にそれぞれに相当する。 In the present embodiment, among the plurality of pores 31, those appearing on the main surface 301, those appearing on each side surface 303, and those appearing on each side surface 304 are described in the claims. It corresponds to "1 hole", "2nd hole" and "3rd hole" respectively.
　複数の第１接合層４１はそれぞれ、各半導体素子１０と各金属部材３０との間に介在し、これらを接合する。第１接合層４１は、たとえばはんだである。当該はんだは、鉛含有であってもよいし、鉛フリーであってもよい。また、各第１接合層４１は、はんだに限定されず、焼結金属などの他の導電性接合材であってもよい。第１接合層４１が、特許請求の範囲に記載の「導電性接合材」に相当する。 Each of the plurality of first bonding layers 41 is interposed between each semiconductor element 10 and each metal member 30 to bond them. The first bonding layer 41 is, for example, solder. The solder may be lead-containing or lead-free. Further, each first bonding layer 41 is not limited to solder, and may be another conductive bonding material such as a sintered metal. The first bonding layer 41 corresponds to the "conductive bonding material" described in the claims.
　複数の第２接合層４２はそれぞれ、各金属部材３０と各配線層２２との間に介在し、これらを接合する。各第２接合層４２は、たとえばはんだである。当該はんだは、鉛含有であってもよいし、鉛フリーであってもよい。また、各第２接合層４２は、はんだに限定されず、焼結金属などの他の導電性接合材であってもよいし、絶縁性接合材（接着剤）であってもよい。第２接合層４２が、特許請求の範囲に記載の「接合層」に相当する。 Each of the plurality of second bonding layers 42 is interposed between each metal member 30 and each wiring layer 22 to bond them. Each second bonding layer 42 is, for example, solder. The solder may be lead-containing or lead-free. Further, each second bonding layer 42 is not limited to solder, and may be another conductive bonding material such as a sintered metal, or may be an insulating bonding material (adhesive). The second bonding layer 42 corresponds to the "bonding layer" described in the claims.
　一対の入力端子５１、一対の出力端子５２、複数の制御端子５３および複数の検出端子５４はそれぞれ、銅または銅合金からなる。一対の入力端子５１、一対の出力端子５２、複数の制御端子５３および複数の検出端子５４は、同一のリードフレームから構成される。 The pair of input terminals 51, the pair of output terminals 52, the plurality of control terminals 53, and the plurality of detection terminals 54 are each made of copper or a copper alloy. The pair of input terminals 51, the pair of output terminals 52, the plurality of control terminals 53, and the plurality of detection terminals 54 are composed of the same lead frame.
　一対の入力端子５１は、図１～図４に示すように、半導体装置Ａ１において、ｘ１方向側に位置する。一対の入力端子５１は、ｙ方向において、互いに離間している。一対の入力端子５１は、外部の直流電源に接続される。一対の入力端子５１の間には、たとえば直流電圧が印加される。一対の入力端子５１はそれぞれ、一部が封止部材７に覆われており、これにより、封止部材７に支持されている。 As shown in FIGS. 1 to 4, the pair of input terminals 51 are located on the x1 direction side in the semiconductor device A1. The pair of input terminals 51 are separated from each other in the y direction. The pair of input terminals 51 are connected to an external DC power supply. For example, a DC voltage is applied between the pair of input terminals 51. Each of the pair of input terminals 51 is partially covered with a sealing member 7, and is thereby supported by the sealing member 7.
　一対の入力端子５１は、第１入力端子５１Ａおよび第２入力端子５１Ｂを含む。第１入力端子５１Ａは、正極（Ｐ端子）であり、第２入力端子５１Ｂは、負極（Ｎ端子）である。第１入力端子５１Ａおよび第２入力端子５１Ｂ（一対の入力端子５１）はそれぞれ、パッド部５１１および端子部５１２を含む。 The pair of input terminals 51 includes a first input terminal 51A and a second input terminal 51B. The first input terminal 51A is a positive electrode (P terminal), and the second input terminal 51B is a negative electrode (N terminal). The first input terminal 51A and the second input terminal 51B (a pair of input terminals 51) include a pad portion 511 and a terminal portion 512, respectively.
　パッド部５１１は、平面視において支持部材２の周縁の外方に位置し、かつ、支持部材２に対してｚ方向に離間している。パッド部５１１は、封止部材７に覆われている。なお、パッド部５１１の表面には、たとえば銀めっきを施していてもよい。 The pad portion 511 is located outside the peripheral edge of the support member 2 in a plan view, and is separated from the support member 2 in the z direction. The pad portion 511 is covered with a sealing member 7. The surface of the pad portion 511 may be silver-plated, for example.
　端子部５１２は、パッド部５１１に繋がり、かつ、封止部材７から露出している。端子部５１２は、半導体装置Ａ１を配線基板に実装する際に用いられる。端子部５１２は、ｙ方向に見て、Ｌ字状をなす。なお、端子部５１２の表面には、たとえばニッケルめっきを施していてもよい。 The terminal portion 512 is connected to the pad portion 511 and is exposed from the sealing member 7. The terminal portion 512 is used when the semiconductor device A1 is mounted on the wiring board. The terminal portion 512 has an L shape when viewed in the y direction. The surface of the terminal portion 512 may be nickel-plated, for example.
　端子部５１２は、基部５１３および起立部５１４を含む。基部５１３は、パッド部５１１に繋がり、かつ、封止部材７（後述の側面７３１）からｘ方向に延びている。起立部５１４は、基部５１３のｘ方向における先端から、ｚ２方向に延びている。 The terminal portion 512 includes a base portion 513 and an upright portion 514. The base portion 513 is connected to the pad portion 511 and extends in the x direction from the sealing member 7 (side surface 731 described later). The upright portion 514 extends in the z2 direction from the tip of the base portion 513 in the x direction.
　一対の出力端子５２は、図１～図４に示すように、半導体装置Ａ１において、ｘ２方向側に位置する。一対の出力端子５２は、図１～図４に示すように、ｙ方向において互いに離間している。一対の出力端子５２から、複数の半導体素子１０により電力変換された交流電力（交流電圧）が出力される。一対の出力端子５２はそれぞれ、一部が封止部材７に覆われており、これにより、封止部材７に支持されている。一対の出力端子５２はそれぞれ、パッド部５２１および端子部５２２を含む。 As shown in FIGS. 1 to 4, the pair of output terminals 52 are located on the x2 direction side in the semiconductor device A1. As shown in FIGS. 1 to 4, the pair of output terminals 52 are separated from each other in the y direction. AC power (AC voltage) converted by a plurality of semiconductor elements 10 is output from the pair of output terminals 52. Each of the pair of output terminals 52 is partially covered with a sealing member 7, and is thereby supported by the sealing member 7. The pair of output terminals 52 include a pad portion 521 and a terminal portion 522, respectively.
　パッド部５２１は、平面視において支持部材２の周縁の外方に位置し、かつ、支持部材２に対してｚ方向に離間している。パッド部５２１は、封止部材７に覆われている。なお、パッド部５２１の表面には、たとえば銀めっきを施していてもよい。 The pad portion 521 is located outside the peripheral edge of the support member 2 in a plan view, and is separated from the support member 2 in the z direction. The pad portion 521 is covered with a sealing member 7. The surface of the pad portion 521 may be silver-plated, for example.
　端子部５２２は、パッド部５２１に繋がり、かつ、封止部材７から露出している。端子部５２２は、半導体装置Ａ１を配線基板に実装する際に用いられる。端子部５２２は、ｙ方向に見て、Ｌ字状をなす。端子部５２２の形状は、各入力端子５１の端子部５１２の形状と略同一である。なお、端子部５２２の表面には、たとえばニッケルめっきを施していてもよい。 The terminal portion 522 is connected to the pad portion 521 and is exposed from the sealing member 7. The terminal portion 522 is used when mounting the semiconductor device A1 on the wiring board. The terminal portion 522 has an L shape when viewed in the y direction. The shape of the terminal portion 522 is substantially the same as the shape of the terminal portion 512 of each input terminal 51. The surface of the terminal portion 522 may be nickel-plated, for example.
　端子部５２２は、基部５２３および起立部５２４を含む。基部５２３は、パッド部５２１に繋がり、かつ、封止部材７（後述の側面７３２）からｘ方向に延びている。起立部５２４は、基部５２３のｘ方向における先端から、ｚ２方向に延びている。 The terminal portion 522 includes a base portion 523 and an upright portion 524. The base portion 523 is connected to the pad portion 521 and extends in the x direction from the sealing member 7 (side surface 732 described later). The upright portion 524 extends in the z2 direction from the tip of the base portion 523 in the x direction.
　複数の制御端子５３は、図１～図４に示すように、半導体装置Ａ１において、ｘ方向の両側に位置する。ｘ１方向側に位置する複数の制御端子５３はともに、ｙ方向において、一対の入力端子５１の間に位置する。ｘ２方向側に位置する複数の制御端子５３はともに、ｙ方向において、一対の出力端子５２の間に位置する。制御端子５３の個数は、半導体素子１０の個数に対応している。よって、半導体装置Ａ１は、４つの制御端子５３を備えている。各制御端子５３には、各半導体素子１０を駆動させるための制御電圧（ゲート電圧）が印加される。各制御端子５３は、一部が封止部材７に覆われており、これにより、封止部材７に支持されている。各制御端子５３は、パッド部５３１および端子部５３２を含む。 As shown in FIGS. 1 to 4, the plurality of control terminals 53 are located on both sides in the x direction in the semiconductor device A1. The plurality of control terminals 53 located on the x1 direction side are both located between the pair of input terminals 51 in the y direction. The plurality of control terminals 53 located on the x2 direction side are both located between the pair of output terminals 52 in the y direction. The number of control terminals 53 corresponds to the number of semiconductor elements 10. Therefore, the semiconductor device A1 includes four control terminals 53. A control voltage (gate voltage) for driving each semiconductor element 10 is applied to each control terminal 53. Each control terminal 53 is partially covered with a sealing member 7, and is thereby supported by the sealing member 7. Each control terminal 53 includes a pad portion 531 and a terminal portion 532.
　パッド部５３１は、平面視において支持部材２の周縁の外方に位置し、かつ、支持部材２に対してｚ方向に離間している。パッド部５３１は、封止部材７に覆われている。なお、パッド部５３１の表面には、たとえば銀めっきを施していてもよい。 The pad portion 531 is located outside the peripheral edge of the support member 2 in a plan view, and is separated from the support member 2 in the z direction. The pad portion 531 is covered with a sealing member 7. The surface of the pad portion 531 may be silver-plated, for example.
　端子部５３２は、パッド部５３１に繋がり、かつ、封止部材７から露出している。端子部５３２は、半導体装置Ａ１を配線基板に実装する際に用いられる。端子部５３２は、ｙ方向に見て、Ｌ字状をなす。なお、端子部５３２の表面には、たとえばニッケルめっきを施していてもよい。 The terminal portion 532 is connected to the pad portion 531 and is exposed from the sealing member 7. The terminal portion 532 is used when the semiconductor device A1 is mounted on the wiring board. The terminal portion 532 has an L shape when viewed in the y direction. The surface of the terminal portion 532 may be nickel-plated, for example.
　端子部５３２は、基部５３３および起立部５３４を含む。基部５３３は、パッド部５３１に繋がり、かつ、封止部材７（後述の側面７３１あるいは側面７３２のいずれか）からｘ方向に延びている。基部５３３のｘ方向の寸法は、一対の入力端子５１の各基部５１３および一対の出力端子５２の各基部５２３のｘ方向の各寸法よりも小さい。起立部５３４は、基部５３３のｘ方向における先端から、ｚ２方向に延びている。 The terminal portion 532 includes a base portion 533 and an upright portion 534. The base portion 533 is connected to the pad portion 531 and extends in the x direction from the sealing member 7 (either the side surface 731 or the side surface 732 described later). The x-direction dimensions of the base 533 are smaller than the x-direction dimensions of each base 513 of the pair of input terminals 51 and each base 523 of the pair of output terminals 52. The upright portion 534 extends in the z2 direction from the tip of the base portion 533 in the x direction.
　複数の検出端子５４は、図１～図４に示すように、半導体装置Ａ１において、ｘ方向の両側に位置する。ｘ１方向側に位置する複数の検出端子５４はともに、ｙ方向において、一対の入力端子５１の間に位置する。ｘ２方向側に位置する複数の検出端子５４はともに、ｙ方向において、一対の出力端子５２の間に位置する。本実施形態においては、検出端子５４の個数は、半導体素子１０の個数に対応している。よって、半導体装置Ａ１は、４つの検出端子５４を備えている。各検出端子５４には、各半導体素子１０の第１電極１１（ソース電極）に流れる電流に対応した電圧が印加される。各検出端子５４は、パッド部５４１および端子部５４２を含む。 As shown in FIGS. 1 to 4, the plurality of detection terminals 54 are located on both sides in the x direction in the semiconductor device A1. The plurality of detection terminals 54 located on the x1 direction side are both located between the pair of input terminals 51 in the y direction. The plurality of detection terminals 54 located on the x2 direction side are both located between the pair of output terminals 52 in the y direction. In the present embodiment, the number of detection terminals 54 corresponds to the number of semiconductor elements 10. Therefore, the semiconductor device A1 includes four detection terminals 54. A voltage corresponding to the current flowing through the first electrode 11 (source electrode) of each semiconductor element 10 is applied to each detection terminal 54. Each detection terminal 54 includes a pad portion 541 and a terminal portion 542.
　パッド部５４１は、平面視において支持部材２の周縁の外方に位置し、かつ、支持部材２に対して、ｚ方向に離間している。パッド部５４１は、封止部材７に覆われている。なお、パッド部５４１の表面には、たとえば銀めっきを施していてもよい。 The pad portion 541 is located outside the peripheral edge of the support member 2 in a plan view, and is separated from the support member 2 in the z direction. The pad portion 541 is covered with a sealing member 7. The surface of the pad portion 541 may be silver-plated, for example.
　端子部５４２は、パッド部５４１に繋がり、かつ、封止部材７から露出している。端子部５４２は、半導体装置Ａ１を配線基板に実装する際に用いられる。端子部５４２は、ｙ方向に見て、Ｌ字状をなす。なお、端子部５４２の表面には、たとえばニッケルめっきを施していてもよい。 The terminal portion 542 is connected to the pad portion 541 and is exposed from the sealing member 7. The terminal portion 542 is used when the semiconductor device A1 is mounted on the wiring board. The terminal portion 542 has an L shape when viewed in the y direction. The surface of the terminal portion 542 may be nickel-plated, for example.
　端子部５４２は、基部５４３および起立部５４４を含む。基部５３３は、パッド部５３１に繋がり、かつ、封止部材７（後述の側面７３１あるいは側面７３２のいずれか）からｘ方向に延びている。基部５４３のｘ方向の寸法は、各制御端子５３の基部５３３のｘ方向の寸法と略同じであり、かつ、一対の入力端子５１の各基部５１３および一対の出力端子５２の各基部５２３のｘ方向の各寸法よりも小さい。起立部５４４は、基部５４３のｘ方向における先端から、ｚ２方向に延びている。 The terminal portion 542 includes a base portion 543 and an upright portion 544. The base portion 533 is connected to the pad portion 531 and extends in the x direction from the sealing member 7 (either the side surface 731 or the side surface 732 described later). The x-direction dimensions of the base 543 are substantially the same as the x-direction dimensions of the base 533 of each control terminal 53, and the x of each base 513 of the pair of input terminals 51 and each base 523 of the pair of output terminals 52. Less than each dimension in the direction. The upright portion 544 extends in the z2 direction from the tip of the base portion 543 in the x direction.
　複数の接続部材６はそれぞれ、離間した２つの部材間を導通させる。複数の接続部材６は、図３に示すように、複数の第１ワイヤ６１１、複数の第２ワイヤ６１２、複数の第３ワイヤ６１３、複数の第４ワイヤ６１４、第１導通部材６２１、第２導通部材６２２、第３導通部材６２３および第４導通部材６２４を含む。 Each of the plurality of connecting members 6 conducts between two separated members. As shown in FIG. 3, the plurality of connecting members 6 include a plurality of first wires 611, a plurality of second wires 612, a plurality of third wires 613, a plurality of fourth wires 614, a first conductive member 621, and a second wire. The conductive member 622, the third conductive member 623, and the fourth conductive member 624 are included.
　複数の第１ワイヤ６１１はそれぞれ、一対の第１素子１０Ａの各第１電極１１と、一対の第２金属部材３０Ｂの各主面３０１とに接合されている。これにより、各第２金属部材３０Ｂ（各第２配線層２２Ｂ）は、各第１ワイヤ６１１を介して、各第１素子１０Ａの第１電極１１に導通している。各第１ワイヤ６１１の構成材料は、たとえばアルミニウムを含む金属、銅を含む金属あるいは金を含む金属などである。 Each of the plurality of first wires 611 is joined to each first electrode 11 of the pair of first elements 10A and each main surface 301 of the pair of second metal members 30B. As a result, each of the second metal members 30B (each of the second wiring layers 22B) is conductive to the first electrode 11 of each of the first elements 10A via each of the first wires 611. The constituent material of each first wire 611 is, for example, a metal containing aluminum, a metal containing copper, or a metal containing gold.
　複数の第２ワイヤ６１２はそれぞれ、一対の第２素子１０Ｂの各第１電極１１と、第３金属部材３０Ｃの主面３０１とに接合されている。これにより、第３金属部材３０Ｃ（第３配線層２２Ｃ）は、各第２ワイヤ６１２を介して、各第２素子１０Ｂの第１電極１１に導通している。各第２ワイヤ６１２の構成材料は、たとえばアルミニウムを含む金属、銅を含む金属あるいは金を含む金属などである。 Each of the plurality of second wires 612 is joined to each first electrode 11 of the pair of second elements 10B and the main surface 301 of the third metal member 30C. As a result, the third metal member 30C (third wiring layer 22C) is conducting to the first electrode 11 of each second element 10B via each second wire 612. The constituent material of each second wire 612 is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, and the like.
　複数の第３ワイヤ６１３はそれぞれ、複数の半導体素子１０の各第３電極１３と、複数の制御端子５３の各パッド部５３１とに接合されている。これにより、各制御端子５３は、各第３ワイヤ６１３を介して、各半導体素子１０の第３電極１３に導通している。各第３ワイヤ６１３の構成材料は、たとえばアルミニウムを含む金属、銅を含む金属あるいは金を含む金属などである。 Each of the plurality of third wires 613 is joined to each third electrode 13 of the plurality of semiconductor elements 10 and each pad portion 531 of the plurality of control terminals 53. As a result, each control terminal 53 is conductive to the third electrode 13 of each semiconductor element 10 via each third wire 613. The constituent material of each third wire 613 is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, and the like.
　複数の第４ワイヤ６１４はそれぞれ、複数の半導体素子１０の各第１電極１１と、複数の検出端子５４の各パッド部５４１とに接合されている。これにより、各検出端子５４は、各第４ワイヤ６１４を介して、各半導体素子１０の第１電極１１に導通している。各第４ワイヤ６１４の構成材料は、たとえばアルミニウムを含む金属、銅を含む金属あるいは金を含む金属などである。 Each of the plurality of fourth wires 614 is joined to each first electrode 11 of the plurality of semiconductor elements 10 and each pad portion 541 of the plurality of detection terminals 54. As a result, each detection terminal 54 is conductive to the first electrode 11 of each semiconductor element 10 via each fourth wire 614. The constituent material of each fourth wire 614 is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, and the like.
　第１導通部材６２１は、図３および図１０に示すように、一方の第１金属部材３０Ａの主面３０１と、他方の第１金属部材３０Ａの主面３０１とに接合されている。これにより、一対の第１金属部材３０Ａ（一対の第１配線層２２Ａ）は、相互に導通している。第１導通部材６２１は、平面視において、ｙ方向に延び、かつ、第３配線層２２Ｃを跨いでいる。第１導通部材６２１は、図３に示すように、たとえば複数のボンディングワイヤから構成される。当該ボンディングワイヤの構成材料は、たとえばアルミニウムを含む金属、銅を含む金属あるいは金を含む金属などである。 As shown in FIGS. 3 and 10, the first conductive member 621 is joined to the main surface 301 of one first metal member 30A and the main surface 301 of the other first metal member 30A. As a result, the pair of first metal members 30A (pair of first wiring layers 22A) are electrically connected to each other. The first conductive member 621 extends in the y direction in a plan view and straddles the third wiring layer 22C. As shown in FIG. 3, the first conductive member 621 is composed of, for example, a plurality of bonding wires. The constituent material of the bonding wire is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, or the like.
　第２導通部材６２２は、図３および図８に示すように、第１入力端子５１Ａのパッド部５１１と、一方の第１金属部材３０Ａの主面３０１とに接合されている。これにより、第１入力端子５１Ａは、第２導通部材６２２を介して、一方の第１金属部材３０Ａ（一方の第１配線層２２Ａ）に導通している。よって、第１入力端子５１Ａは、第２導通部材６２２および一方の第１金属部材３０Ａ（一方の第１配線層２２Ａ）を介して、一方の第１素子１０Ａの第２電極１２に導通している。第２導通部材６２２は、図３に示すように、たとえば複数のボンディングワイヤから構成される。当該ボンディングワイヤの構成材料は、たとえばアルミニウムを含む金属、銅を含む金属あるいは金を含む金属などである。 As shown in FIGS. 3 and 8, the second conductive member 622 is joined to the pad portion 511 of the first input terminal 51A and the main surface 301 of one of the first metal members 30A. As a result, the first input terminal 51A is conducting to one of the first metal members 30A (one of the first wiring layers 22A) via the second conducting member 622. Therefore, the first input terminal 51A conducts to the second electrode 12 of one first element 10A via the second conduction member 622 and one first metal member 30A (one first wiring layer 22A). There is. As shown in FIG. 3, the second conductive member 622 is composed of, for example, a plurality of bonding wires. The constituent material of the bonding wire is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, or the like.
　第３導通部材６２３は、図３に示すように、第２入力端子５１Ｂのパッド部５１１と、第３配線層２２Ｃの主面２２１とに接合されている。これにより、第２入力端子５１Ｂは、第３導通部材６２３、第３金属部材３０Ｃ（第３配線層２２Ｃ）、および、複数の第２ワイヤ６１２を介して、各第２素子１０Ｂの第１電極１１に導通している。第３導通部材６２３は、図３に示すように、たとえば複数のボンディングワイヤから構成される。当該ボンディングワイヤの構成材料は、たとえばアルミニウムを含む金属、銅を含む金属あるいは金を含む金属などである。 As shown in FIG. 3, the third conductive member 623 is joined to the pad portion 511 of the second input terminal 51B and the main surface 221 of the third wiring layer 22C. As a result, the second input terminal 51B is connected to the first electrode of each second element 10B via the third conductive member 623, the third metal member 30C (third wiring layer 22C), and the plurality of second wires 612. It is conducting to 11. As shown in FIG. 3, the third conductive member 623 is composed of, for example, a plurality of bonding wires. The constituent material of the bonding wire is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, or the like.
　一対の第４導通部材６２４は、図３および図８に示すように、一対の出力端子５２の各パッド部５２１と、一対の第２金属部材３０Ｂの各主面３０１とに接合されている。これにより、一対の出力端子５２は、一対の第４導通部材６２４および一対の第２金属部材３０Ｂ（一対の第２配線層２２Ｂ）を介して、各第２素子１０Ｂの第２電極１２に導通している。また、一対の出力端子５２は、一対の第４導通部材６２４、一対の第２金属部材３０Ｂ（第２配線層２２Ｂ）および複数の第１ワイヤ６１１を介して、各第１素子１０Ａの第１電極１１に導通している。一対の第４導通部材６２４はそれぞれ、図３に示すように、たとえば複数のボンディングワイヤから構成される。当該ボンディングワイヤの構成材料は、たとえばアルミニウムを含む金属、銅を含む金属あるいは金を含む金属などである。 As shown in FIGS. 3 and 8, the pair of fourth conductive members 624 are joined to each pad portion 521 of the pair of output terminals 52 and each main surface 301 of the pair of second metal members 30B. As a result, the pair of output terminals 52 conduct with the second electrode 12 of each second element 10B via the pair of fourth conductive members 624 and the pair of second metal members 30B (pair of second wiring layers 22B). doing. Further, the pair of output terminals 52 is the first of each first element 10A via the pair of fourth conductive members 624, the pair of second metal members 30B (second wiring layer 22B), and the plurality of first wires 611. It is conducting to the electrode 11. Each of the pair of fourth conductive members 624 is composed of, for example, a plurality of bonding wires, as shown in FIG. The constituent material of the bonding wire is, for example, a metal containing aluminum, a metal containing copper, a metal containing gold, or the like.
　なお、第１導通部材６２１、第２導通部材６２２、第３導通部材６２３および一対の第４導通部材６２４はそれぞれ、複数のボンディングワイヤではなく、金属リードあるいはボンディングリボンであってもよい。当該金属リードあるいはボンディングリボンの各構成材料は、たとえば銅を含む金属、アルミニウムを含む金属あるいは金を含む金属などである。 The first conductive member 621, the second conductive member 622, the third conductive member 623, and the pair of fourth conductive members 624 may be metal leads or bonding ribbons instead of a plurality of bonding wires, respectively. Each constituent material of the metal lead or bonding ribbon is, for example, a metal containing copper, a metal containing aluminum, or a metal containing gold.
　封止部材７は、半導体装置Ａ１の半導体パッケージである。封止部材７は、図１～図１１に示すように、半導体装置Ａ１の各構成部材を覆う。ただし、支持部材２、一対の入力端子５１、一対の出力端子５２、複数の制御端子５３および複数の検出端子５４においては、それぞれ一部ずつを覆っている。封止部材７の構成材料は、たとえばエポキシ樹脂である。封止部材７は、たとえば、ｘ方向の寸法が２０ｍｍ以上１２０ｍｍ以下（好ましくは２５ｍｍ以上６０ｍｍ以下）であり、ｙ方向の寸法が２０ｍｍ以上１２０ｍｍ以下（好ましくは４０ｍｍ以上７０ｍｍ以下）であり、ｚ方向の寸法が５ｍｍ以上１０ｍｍ以下（好ましくは７ｍｍ）である。封止部材７は、主面７１、裏面７２、複数の側面７３１～７３４および一対の取付孔７４を有する。 The sealing member 7 is a semiconductor package of the semiconductor device A1. As shown in FIGS. 1 to 11, the sealing member 7 covers each component of the semiconductor device A1. However, the support member 2, the pair of input terminals 51, the pair of output terminals 52, the plurality of control terminals 53, and the plurality of detection terminals 54 each partially cover each of them. The constituent material of the sealing member 7 is, for example, an epoxy resin. The sealing member 7 has, for example, a dimension in the x direction of 20 mm or more and 120 mm or less (preferably 25 mm or more and 60 mm or less), a dimension in the y direction of 20 mm or more and 120 mm or less (preferably 40 mm or more and 70 mm or less), and a z direction. The size of is 5 mm or more and 10 mm or less (preferably 7 mm). The sealing member 7 has a main surface 71, a back surface 72, a plurality of side surfaces 731 to 734, and a pair of mounting holes 74.
　主面７１および裏面７２は、図５～図７に示すように、ｚ方向において、離間する。主面７１は、ｚ２方向を向き、裏面７２は、ｚ１方向を向く。裏面７２は、図４に示すように、平面視において、絶縁基板２１の裏面２１２を囲む枠状である。絶縁基板２１の裏面２１２は、当該裏面７２から露出する。複数の側面７３１～７３４の各々は、ｚ方向において主面７１および裏面７２に挟まれており、かつ、これらの双方に繋がる。図３に示すように、側面７３１，７３２は、ｘ方向において、離間する。側面７３１は、ｘ１方向を向き、側面７３２は、ｘ２方向を向く。図３に示すように、側面７３３，７３４は、ｙ方向において、離間する。側面７３３は、ｙ１方向を向き、側面７３４は、ｙ２方向を向く。 The main surface 71 and the back surface 72 are separated from each other in the z direction as shown in FIGS. 5 to 7. The main surface 71 faces the z2 direction, and the back surface 72 faces the z1 direction. As shown in FIG. 4, the back surface 72 has a frame shape surrounding the back surface 212 of the insulating substrate 21 in a plan view. The back surface 212 of the insulating substrate 21 is exposed from the back surface 72. Each of the plurality of side surfaces 731 to 734 is sandwiched between the main surface 71 and the back surface 72 in the z direction, and is connected to both of them. As shown in FIG. 3, the side surfaces 731 and 732 are separated in the x direction. The side surface 731 faces the x1 direction, and the side surface 732 faces the x2 direction. As shown in FIG. 3, the side surfaces 733 and 734 are separated in the y direction. The side surface 733 faces the y1 direction, and the side surface 734 faces the y2 direction.
　図３に示すように、側面７３１から、一対の入力端子５１の各端子部５１２と、一対の第２素子１０Ｂに対応して配置された一対の制御端子５３の各端子部５３２および一対の検出端子５４の各端子部５４２とが露出している。また、図３に示すように、側面７３２から、一対の出力端子５２の各端子部５２２と、一対の第１素子１０Ａに対応して配置された一対の制御端子５３の各端子部５３２および一対の検出端子５４の各端子部５４２とが露出している。 As shown in FIG. 3, from the side surface 731, each terminal portion 512 of the pair of input terminals 51, each terminal portion 532 of the pair of control terminals 53 arranged corresponding to the pair of second elements 10B, and the pair of detections. Each terminal portion 542 of the terminal 54 is exposed. Further, as shown in FIG. 3, from the side surface 732, each terminal portion 522 of the pair of output terminals 52 and each terminal portion 532 and a pair of the pair of control terminals 53 arranged corresponding to the pair of the first elements 10A. Each terminal portion 542 of the detection terminal 54 of the above is exposed.
　一対の取付孔７４は、図５～図７および図１０に示すように、ｚ方向において主面７１から裏面７２まで繋がり、封止部材７を貫通する。一対の取付孔７４はそれぞれ、図２～図４に示すように、たとえば平面視円形状である。一対の取付孔７４は、絶縁基板２１のｙ方向の両側に位置する。一対の取付孔７４のｙ方向の離間距離は、たとえば１５ｍｍ以上１００ｍｍ以下（好ましくは３０ｍｍ以上７０ｍｍ以下）である。一対の取付孔７４は、半導体装置Ａ１をヒートシンクに取り付ける際に利用されうる。 As shown in FIGS. 5 to 7 and 10, the pair of mounting holes 74 are connected from the main surface 71 to the back surface 72 in the z direction and penetrate the sealing member 7. As shown in FIGS. 2 to 4, each of the pair of mounting holes 74 has, for example, a circular shape in a plan view. The pair of mounting holes 74 are located on both sides of the insulating substrate 21 in the y direction. The separation distance of the pair of mounting holes 74 in the y direction is, for example, 15 mm or more and 100 mm or less (preferably 30 mm or more and 70 mm or less). The pair of mounting holes 74 can be used when mounting the semiconductor device A1 on the heat sink.
　以上のように構成された半導体装置Ａ１の作用効果は、次の通りである。 The effects of the semiconductor device A1 configured as described above are as follows.
　半導体装置Ａ１によれば、半導体素子１０、支持部材２、および、金属部材３０を備えている。半導体素子１０は、第１接合層４１によって、金属部材３０に接合されており、金属部材３０は、第２接合層４２によって、支持部材２に接合されている。金属部材３０は、複数の細孔３１が形成された多孔質体である。この構成によると、半導体素子１０からの熱によって、金属部材３０が熱膨張する際、複数の細孔３１付近に熱ひずみが生じるため、複数の細孔３１付近の熱応力が局所的に緩和される。したがって、金属部材３０の熱膨張による熱応力を緩和させることができるので、たとえば、金属部材３０に接する第２接合層４２にかかる熱応力を緩和させ、第２接合層４２の凝集破壊を抑制できる。つまり、半導体装置Ａ１は、接合不良や導通不良などの製品故障の発生が抑制されるので、信頼性を向上させることができる。また、半導体装置Ａ１は、金属部材３０に接する第１接合層４１にかかる熱応力も緩和させることができるので、第１接合層４１の凝集破壊を抑制できる。 According to the semiconductor device A1, the semiconductor element 10, the support member 2, and the metal member 30 are provided. The semiconductor element 10 is bonded to the metal member 30 by the first bonding layer 41, and the metal member 30 is bonded to the support member 2 by the second bonding layer 42. The metal member 30 is a porous body in which a plurality of pores 31 are formed. According to this configuration, when the metal member 30 thermally expands due to the heat from the semiconductor element 10, thermal strain is generated in the vicinity of the plurality of pores 31, so that the thermal stress in the vicinity of the plurality of pores 31 is locally relaxed. To. Therefore, since the thermal stress due to the thermal expansion of the metal member 30 can be relaxed, for example, the thermal stress applied to the second bonding layer 42 in contact with the metal member 30 can be relaxed, and the cohesive failure of the second bonding layer 42 can be suppressed. .. That is, the semiconductor device A1 can improve the reliability because the occurrence of product failures such as poor bonding and poor conduction is suppressed. Further, since the semiconductor device A1 can also relax the thermal stress applied to the first bonding layer 41 in contact with the metal member 30, it is possible to suppress the cohesive failure of the first bonding layer 41.
　半導体装置Ａ１によれば、各金属部材３０は、その厚さが、支持部材２の厚さよりも大きく、０．５ｍｍ以上５ｍｍ以下（好ましくは１．０ｍｍ以上３ｍｍ以下）である。たとえば、本開示の半導体装置Ａ１と異なる半導体装置において、各金属部材の厚さを金属部材３０の厚さよりも小さくして、金属部材の剛性を低くすることで、熱応力を緩和させることも可能である。しかしながら、このような手法（金属部材を薄くする手法）では、金属部材に反りが生じて、当該金属部材と支持部材２との間に封止部材７が入り込み、支持部材２が損壊する（割れる）可能性がある。また、金属部材を薄くする手法では、金属部材による熱拡散効率が低下する可能性がある。一方、半導体装置Ａ１においては、複数の細孔３１が形成された多孔質体の金属部材３０を用いることで、金属部材３０の剛性を低くしている。したがって、半導体装置Ａ１は、支持部材２の損壊や熱拡散効率の低下を抑制しつつ、第２接合層４２にかかる熱応力を緩和させることができる。 According to the semiconductor device A1, the thickness of each metal member 30 is larger than the thickness of the support member 2 and is 0.5 mm or more and 5 mm or less (preferably 1.0 mm or more and 3 mm or less). For example, in a semiconductor device different from the semiconductor device A1 of the present disclosure, the thermal stress can be relaxed by making the thickness of each metal member smaller than the thickness of the metal member 30 to lower the rigidity of the metal member. Is. However, in such a method (a method of thinning the metal member), the metal member is warped, the sealing member 7 enters between the metal member and the support member 2, and the support member 2 is damaged (broken). )there is a possibility. In addition, the method of thinning the metal member may reduce the heat diffusion efficiency of the metal member. On the other hand, in the semiconductor device A1, the rigidity of the metal member 30 is lowered by using the porous metal member 30 in which the plurality of pores 31 are formed. Therefore, the semiconductor device A1 can relieve the thermal stress applied to the second bonding layer 42 while suppressing the damage of the support member 2 and the decrease in the heat diffusion efficiency.
　半導体装置Ａ１によれば、金属部材３０に対する複数の細孔３１の占有率は、１０％以上７０％以下である。たとえば、この占有率が、７０％（先述の占有率の範囲の最大値）よりも大きい場合、第１接合層４１や第２接合層４２が複数の細孔３１に吸収されてしまい、半導体素子１０および金属部材３０の接合が不十分となる。一方、この占有率が、１０％（先述の占有率の範囲の最小値）よりも小さい場合、多数の細孔３１付近の熱応力の緩和が不十分となり、熱応力を適度に緩和できない。したがって、先述の占有率を１０％以上７０％以下とすることで、半導体素子１０と金属部材３０との接合強度および支持部材２（配線層２２）と金属部材３０との接合強度を確保しつつ、金属部材３０による熱応力を適度に緩和させることができる。 According to the semiconductor device A1, the occupancy rate of the plurality of pores 31 with respect to the metal member 30 is 10% or more and 70% or less. For example, when this occupancy rate is larger than 70% (the maximum value in the above-mentioned occupancy rate range), the first bonding layer 41 and the second bonding layer 42 are absorbed by the plurality of pores 31, and the semiconductor element. The joining of the 10 and the metal member 30 becomes insufficient. On the other hand, when this occupancy rate is smaller than 10% (the minimum value in the above-mentioned occupancy rate range), the thermal stress in the vicinity of a large number of pores 31 is insufficiently relaxed, and the thermal stress cannot be moderately relaxed. Therefore, by setting the occupancy rate to 10% or more and 70% or less as described above, the bonding strength between the semiconductor element 10 and the metal member 30 and the bonding strength between the support member 2 (wiring layer 22) and the metal member 30 are ensured. , The thermal stress caused by the metal member 30 can be appropriately relaxed.
　半導体装置Ａ１によれば、複数の細孔３１の一部には、封止部材７が充填されている。具体的には、各金属部材３０において、主面３０１のうち第１接合層４１に接していない領域、および、各側面３０３，３０４の全領域に表れた複数の細孔３１には、封止部材７が充填されている。この構成によると、アンカー効果によって、各金属部材３０と封止部材７との密着性を向上させることができる。なお、封止部材７が充填された細孔３１付近においては、空気が充填された細孔３１付近よりも、熱応力が比較的大きくなるが、細孔３１が形成されていない場合よりも、熱応力を比較的に小さくすることができる。つまり、一部の細孔３１に封止部材７が充填されていても、定性的に熱応力の緩和を図ることができる。したがって、半導体装置Ａ１は、熱応力の緩和を図りつつ、封止部材７の密着性を向上させることができる。 According to the semiconductor device A1, a part of the plurality of pores 31 is filled with the sealing member 7. Specifically, in each metal member 30, the region of the main surface 301 that is not in contact with the first bonding layer 41 and the plurality of pores 31 appearing in the entire regions of the side surfaces 303 and 304 are sealed. The member 7 is filled. According to this configuration, the adhesion between each metal member 30 and the sealing member 7 can be improved by the anchor effect. In the vicinity of the pores 31 filled with the sealing member 7, the thermal stress is relatively larger than in the vicinity of the pores 31 filled with air, but compared to the case where the pores 31 are not formed. The thermal stress can be made relatively small. That is, even if some of the pores 31 are filled with the sealing member 7, the thermal stress can be qualitatively relaxed. Therefore, the semiconductor device A1 can improve the adhesion of the sealing member 7 while alleviating the thermal stress.
　半導体装置Ａ１によれば、支持部材２は、絶縁基板２１を含んでいる。絶縁基板２１は、熱伝導率が比較的高いセラミックスからなる。この構成によると、半導体素子１０によって生じた熱は、金属部材３０によって熱拡散され、そして、絶縁基板２１に伝達される。したがって、半導体装置Ａ１は、半導体素子１０からの熱が、金属部材３０および絶縁基板２１に拡散されるため、半導体素子１０の放熱効率の向上を図ることができる。さらに、絶縁基板２１は、裏面２１２が封止部材７から露出している。この構成によると、絶縁基板２１に伝達された熱が、裏面２１２から外部に放出される。また、半導体装置Ａ１にヒートシンクが取り付けられている場合、裏面２１２から当該ヒートシンクに伝達される。したがって、半導体装置Ａ１は、半導体素子１０からの発熱を、効率よく放熱することができる。 According to the semiconductor device A1, the support member 2 includes an insulating substrate 21. The insulating substrate 21 is made of ceramics having a relatively high thermal conductivity. According to this configuration, the heat generated by the semiconductor element 10 is thermally diffused by the metal member 30 and transferred to the insulating substrate 21. Therefore, in the semiconductor device A1, the heat from the semiconductor element 10 is diffused to the metal member 30 and the insulating substrate 21, so that the heat dissipation efficiency of the semiconductor element 10 can be improved. Further, the back surface 212 of the insulating substrate 21 is exposed from the sealing member 7. According to this configuration, the heat transferred to the insulating substrate 21 is released to the outside from the back surface 212. When a heat sink is attached to the semiconductor device A1, the heat sink is transmitted from the back surface 212 to the heat sink. Therefore, the semiconductor device A1 can efficiently dissipate heat generated from the semiconductor element 10.
　図１５は、第２実施形態にかかる半導体装置Ａ２を示している。図１５は、半導体装置Ａ２を示す平面図であって、封止部材７を想像線（二点鎖線）で示している。半導体装置Ａ２は、半導体装置Ａ１と比較して、支持部材２の複数の配線層２２の構成が主に異なっており、これに伴い、複数の半導体素子１０、複数の金属部材３０、一対の入力端子５１、一対の出力端子５２、複数の制御端子５３、複数の検出端子５４および複数の接続部材６などの配置もそれぞれ異なっている。 FIG. 15 shows the semiconductor device A2 according to the second embodiment. FIG. 15 is a plan view showing the semiconductor device A2, and the sealing member 7 is shown by an imaginary line (dashed-dotted line). The semiconductor device A2 is mainly different from the semiconductor device A1 in the configuration of the plurality of wiring layers 22 of the support member 2, and accordingly, the plurality of semiconductor elements 10, the plurality of metal members 30, and a pair of inputs. The arrangement of the terminals 51, the pair of output terminals 52, the plurality of control terminals 53, the plurality of detection terminals 54, the plurality of connecting members 6, and the like are also different.
　図１５に示すように、支持部材２の複数の配線層２２は、第１配線層２２Ａ、一対の第２配線層２２Ｂ、第３配線層２２Ｃおよび第４配線層２２Ｄを含む。よって、半導体装置Ａ２は、半導体装置Ａ１と異なり、第１配線層２２Ａが１つであり、かつ、第４配線層２２Ｄをさらに備えている。 As shown in FIG. 15, the plurality of wiring layers 22 of the support member 2 include a first wiring layer 22A, a pair of second wiring layers 22B, a third wiring layer 22C, and a fourth wiring layer 22D. Therefore, unlike the semiconductor device A1, the semiconductor device A2 has one first wiring layer 22A and further includes a fourth wiring layer 22D.
　第１配線層２２Ａは、絶縁基板２１において、ｘ２方向側、かつ、ｙ２方向側に位置する。一対の第２配線層２２Ｂは、絶縁基板２１において、ｘ１方向側、かつ、ｙ１方向側に位置する。一対の第２配線層２２Ｂは、ｙ方向に隣接している。第３配線層２２Ｃは、ｘ２方向側、かつ、ｙ１方向側に位置する。第３配線層２２Ｃは、ｙ方向において、第１配線層２２Ａの隣に位置する。第３配線層２２Ｃと第１配線層２２Ａとは略同じ形状である。第４配線層２２Ｄは、ｘ１方向側、かつ、ｙ２方向側に位置する。第４配線層２２Ｄは、ｘ方向において、第１配線層２２Ａの隣に位置する。第４配線層２２Ｄは、一対の第２配線層２２Ｂの一方と略同じ形状である。 The first wiring layer 22A is located on the x2 direction side and the y2 direction side of the insulating substrate 21. The pair of second wiring layers 22B are located on the x1 direction side and the y1 direction side of the insulating substrate 21. The pair of second wiring layers 22B are adjacent to each other in the y direction. The third wiring layer 22C is located on the x2 direction side and the y1 direction side. The third wiring layer 22C is located next to the first wiring layer 22A in the y direction. The third wiring layer 22C and the first wiring layer 22A have substantially the same shape. The fourth wiring layer 22D is located on the x1 direction side and the y2 direction side. The fourth wiring layer 22D is located next to the first wiring layer 22A in the x direction. The fourth wiring layer 22D has substantially the same shape as one of the pair of second wiring layers 22B.
　図１５に示すように、複数の金属部材３０は、第１金属部材３０Ａ、一対の第２金属部材３０Ｂ、第３金属部材３０Ｃおよび第４金属部材３０Ｄを含む。よって、半導体装置Ａ２は、半導体装置Ａ１と異なり、第１金属部材３０Ａが１つであり、かつ、第４金属部材３０Ｄをさらに備えている。 As shown in FIG. 15, the plurality of metal members 30 include a first metal member 30A, a pair of second metal members 30B, a third metal member 30C, and a fourth metal member 30D. Therefore, unlike the semiconductor device A1, the semiconductor device A2 has one first metal member 30A and further includes a fourth metal member 30D.
　第１金属部材３０Ａは、第２接合層４２によって、第１配線層２２Ａに接合されている。第１金属部材３０Ａには、２つの第１素子１０Ａがそれぞれ、第１接合層４１によって接合されている。したがって、本実施形態においては、１つの金属部材３０（第１金属部材３０Ａ）に、２つの半導体素子１０（第１素子１０Ａ）が接合されている。 The first metal member 30A is joined to the first wiring layer 22A by the second joining layer 42. Two first elements 10A are joined to the first metal member 30A by a first joining layer 41, respectively. Therefore, in the present embodiment, two semiconductor elements 10 (first element 10A) are joined to one metal member 30 (first metal member 30A).
　一対の第２金属部材３０Ｂはそれぞれ、第１実施形態と同様に、一対の第２素子１０Ｂがそれぞれ、第１接合層４１によって接合されている。第４金属部材３０Ｄは、複数の半導体素子１０のいずれも接合されていない。第４金属部材３０Ｄは、複数の第１ワイヤ６１１および第１導通部材６２１が接合されている。 As in the first embodiment, the pair of second metal members 30B each have a pair of second elements 10B bonded by the first bonding layer 41. None of the plurality of semiconductor elements 10 is joined to the fourth metal member 30D. A plurality of first wires 611 and a first conductive member 621 are joined to the fourth metal member 30D.
　半導体装置Ａ２において、第１導通部材６２１は、第４金属部材３０Ｄと一対の第２金属部材３０Ｂの一方とに接合され、これらを導通している。 In the semiconductor device A2, the first conductive member 621 is joined to one of the fourth metal member 30D and the pair of second metal members 30B, and these are conductive.
　半導体装置Ａ２において、一対の入力端子５１は、図１５に示すように、ｘ２方向側に位置する。また、一対の入力端子５１は、ｙ方向において離間しており、第１入力端子５１Ａがｙ２方向に位置し、第２入力端子５１Ｂがｙ１方向に位置する。 In the semiconductor device A2, the pair of input terminals 51 are located on the x2 direction side as shown in FIG. Further, the pair of input terminals 51 are separated in the y direction, the first input terminal 51A is located in the y2 direction, and the second input terminal 51B is located in the y1 direction.
　半導体装置Ａ２において、第１入力端子５１Ａは、第２導通部材６２２および第１金属部材３０Ａを介して、各第１素子１０Ａの第２電極１２に導通している。第２入力端子５１Ｂは、第３導通部材６２３、第３金属部材３０Ｃおよび複数の第２ワイヤ６１２を介して、各第２素子１０Ｂの第１電極１１に導通している。 In the semiconductor device A2, the first input terminal 51A is conductive to the second electrode 12 of each first element 10A via the second conductive member 622 and the first metal member 30A. The second input terminal 51B is conductive to the first electrode 11 of each second element 10B via the third conductive member 623, the third metal member 30C, and the plurality of second wires 612.
　半導体装置Ａ２において、一対の出力端子５２は、図１５に示すように、ｘ１方向側に位置する。半導体装置Ａ２において、ｙ１方向側の出力端子５２は、第４導通部材６２４および第２金属部材３０Ｂを介して、一対の第２素子１０Ｂの一方の第２電極１２に導通するとともに、第４導通部材６２４、第２金属部材３０Ｂ、第１導通部材６２１、第４金属部材３０Ｄおよび複数の第１ワイヤ６１１を介して、一対の第１素子１０Ａの一方の第１電極１１に導通している。また、ｙ２方向側の出力端子５２は、第４導通部材６２４および第２金属部材３０Ｂを介して、一対の第２素子１０Ｂの他方の第２電極１２に導通するとともに、第４導通部材６２４、第２金属部材３０Ｂおよび複数の第１ワイヤ６１１を介して、一対の第１素子１０Ａの他方の第１電極１１に導通している。 In the semiconductor device A2, the pair of output terminals 52 are located on the x1 direction side as shown in FIG. In the semiconductor device A2, the output terminal 52 on the y1 direction side conducts to one of the second electrodes 12 of the pair of second elements 10B via the fourth conductive member 624 and the second metal member 30B, and also conducts the fourth conduction. It conducts to one of the first electrodes 11 of the pair of first elements 10A via the member 624, the second metal member 30B, the first conductive member 621, the fourth metal member 30D, and the plurality of first wires 611. Further, the output terminal 52 on the y2 direction side conducts to the other second electrode 12 of the pair of second elements 10B via the fourth conductive member 624 and the second metal member 30B, and the fourth conductive member 624, It conducts to the other first electrode 11 of the pair of first elements 10A via the second metal member 30B and the plurality of first wires 611.
　半導体装置Ａ２は、一部が側面７３１から突き出た制御端子５３と、一部が側面７３２から突き出た制御端子５３とを備えている。一部が側面７３１から突き出た制御端子５３は、複数の第３ワイヤ６１３を介して、各第１素子１０Ａの第３電極１３にそれぞれ導通している。また、一部が側面７３２から突き出た制御端子５３は、複数の第３ワイヤ６１３を介して、各第２素子１０Ｂの第３電極１３にそれぞれ導通している。本実施形態においては、２つの制御端子５３を設け、一方の制御端子５３が一対の第１素子１０Ａに対して共通であり、他方の制御端子５３が一対の第２素子１０Ｂに対して共通である場合を示すが、これに限定されない。たとえば、半導体装置Ａ１と同様に、複数の半導体素子１０（一対の第１素子１０Ａおよび一対の第２素子１０Ｂ）にそれぞれ対応した４つの制御端子５３を設けてもよい。 The semiconductor device A2 includes a control terminal 53 partially protruding from the side surface 731 and a control terminal 53 partially protruding from the side surface 732. The control terminal 53, part of which protrudes from the side surface 731, is electrically connected to the third electrode 13 of each first element 10A via the plurality of third wires 613. Further, the control terminal 53, part of which protrudes from the side surface 732, is electrically connected to the third electrode 13 of each second element 10B via the plurality of third wires 613. In the present embodiment, two control terminals 53 are provided, one control terminal 53 is common to the pair of first elements 10A, and the other control terminal 53 is common to the pair of second elements 10B. Indicates a case, but is not limited to this. For example, similarly to the semiconductor device A1, four control terminals 53 corresponding to a plurality of semiconductor elements 10 (a pair of first elements 10A and a pair of second elements 10B) may be provided.
　半導体装置Ａ２は、一部が側面７３１から突き出た検出端子５４と、一部が側面７３２から突き出た検出端子５４とを備えている。一部が側面７３２から突き出た検出端子５４は、第４ワイヤ６１４を介して、一対の第１素子１０Ａのいずれかの第１電極１１に導通している。また、一部が側面７３１から突き出た検出端子５４は、第４ワイヤ６１４を介して、一対の第２素子１０Ｂのいずれかの第１電極１１に導通している。本実施形態において、２つの検出端子５４を設け、一方の検出端子５４が一対の第１素子１０Ａのいずれかに導通し、他方の検出端子５４が一対の第２素子１０Ｂのいずれかに導通している場合を示すが、これに限定されない。たとえば、半導体装置Ａ１と同様に、複数の半導体素子１０（一対の第１素子１０Ａおよび一対の第２素子１０Ｂ）にそれぞれ対応した４つの検出端子５４を設けてもよい。 The semiconductor device A2 includes a detection terminal 54 partially protruding from the side surface 731 and a detection terminal 54 partially protruding from the side surface 732. The detection terminal 54, part of which protrudes from the side surface 732, is conducted to the first electrode 11 of any one of the pair of first elements 10A via the fourth wire 614. Further, the detection terminal 54, part of which protrudes from the side surface 731, is conducted to the first electrode 11 of any one of the pair of second elements 10B via the fourth wire 614. In the present embodiment, two detection terminals 54 are provided, one detection terminal 54 conducts to one of the pair of first elements 10A, and the other detection terminal 54 conducts to any of the pair of second elements 10B. However, the present invention is not limited to this. For example, similarly to the semiconductor device A1, four detection terminals 54 corresponding to a plurality of semiconductor elements 10 (a pair of first elements 10A and a pair of second elements 10B) may be provided.
　以上のように構成された半導体装置Ａ２の作用効果は、次の通りである。 The effects of the semiconductor device A2 configured as described above are as follows.
　半導体装置Ａ２によれば、半導体素子１０、支持部材２および金属部材３０を備えている。半導体素子１０は、第１接合層４１によって、金属部材３０に接合されており、金属部材３０は、第２接合層４２によって、支持部材２に接合されている。金属部材３０は、複数の細孔３１が形成された多孔質体である。したがって、半導体装置Ａ２は、半導体装置Ａ１と同様に、金属部材３０に接する第２接合層４２にかかる熱応力を緩和させることができるので、第２接合層４２の凝集破壊を抑制できる。つまり、半導体装置Ａ２は、接合不良や導通不良などの製品故障の発生が抑制されるので、信頼性を向上させることができる。 According to the semiconductor device A2, the semiconductor element 10, the support member 2, and the metal member 30 are provided. The semiconductor element 10 is bonded to the metal member 30 by the first bonding layer 41, and the metal member 30 is bonded to the support member 2 by the second bonding layer 42. The metal member 30 is a porous body in which a plurality of pores 31 are formed. Therefore, similarly to the semiconductor device A1, the semiconductor device A2 can relieve the thermal stress applied to the second bonding layer 42 in contact with the metal member 30, so that the cohesive failure of the second bonding layer 42 can be suppressed. That is, the semiconductor device A2 can improve the reliability because the occurrence of product failures such as poor bonding and poor conduction is suppressed.
　半導体装置Ａ２によれば、その他、半導体装置Ａ１と同一あるいは類似の構成によって、半導体装置Ａ１と同様の効果を奏することができる。 According to the semiconductor device A2, the same effect as that of the semiconductor device A1 can be obtained by the same or similar configuration as that of the semiconductor device A1.
　第１実施形態および第２実施形態では、各金属部材３０が第２接合層４２によって各配線層２２に接合された場合を示したが、これに限定されない。たとえば、各金属部材３０が第２接合層４２によって絶縁基板２１に接合されていてもよい。つまり、支持部材２が複数の配線層２２を含んでいなくてもよい。この場合であっても、金属部材３０に接する第２接合層４２にかかる熱応力を緩和させることができる。 In the first embodiment and the second embodiment, the case where each metal member 30 is joined to each wiring layer 22 by the second joining layer 42 is shown, but the present invention is not limited to this. For example, each metal member 30 may be bonded to the insulating substrate 21 by a second bonding layer 42. That is, the support member 2 does not have to include the plurality of wiring layers 22. Even in this case, the thermal stress applied to the second bonding layer 42 in contact with the metal member 30 can be relaxed.
　第１実施形態および第２実施形態では、第１入力端子５１Ａが第２導通部材６２２を介して第１金属部材３０Ａに導通している場合を示したが、第１入力端子５１Ａが第１金属部材３０Ａに直接接合されてこれらが導通していてもよい。同様に、第２入力端子５１Ｂが第３導通部材６２３を介して第３金属部材３０Ｃに導通している場合を示したが、第２入力端子５１Ｂが第３金属部材３０Ｃに直接接合されてこれらが導通していてもよい。また、各出力端子５２が第４導通部材６２４を介して各第２金属部材３０Ｂに導通している場合を示したが、各出力端子５２が各第２金属部材３０Ｂにそれぞれ直接接合されてこれが導通していてもよい。 In the first embodiment and the second embodiment, the case where the first input terminal 51A is conducting to the first metal member 30A via the second conductive member 622 is shown, but the first input terminal 51A is the first metal. They may be directly joined to the member 30A so as to be conductive. Similarly, the case where the second input terminal 51B is conducting to the third metal member 30C via the third conductive member 623 is shown, but the second input terminal 51B is directly joined to the third metal member 30C to these. May be conducting. Further, although the case where each output terminal 52 is conducting to each second metal member 30B via the fourth conductive member 624 is shown, each output terminal 52 is directly joined to each second metal member 30B, and this is It may be conducting.
　図１６および図１７は、第３実施形態にかかる半導体装置Ａ３を示している。図１６は、半導体装置Ａ３を示す平面図であって、封止部材７を想像線（二点鎖線）で示している。図１７は、図１６のＸＶＩＩ－ＸＶＩＩ線に沿う断面図である。半導体装置Ａ３は、いわゆるＴＯ（Transistor Outline）パッケージ型である。 16 and 17 show the semiconductor device A3 according to the third embodiment. FIG. 16 is a plan view showing the semiconductor device A3, and the sealing member 7 is shown by an imaginary line (dashed line). FIG. 17 is a cross-sectional view taken along the line XVII-XVII of FIG. The semiconductor device A3 is a so-called TO (Transistor Outline) package type.
　支持部材２は、いわゆるリードフレームである。支持部材２の構成材料は、たとえば銅あるいは銅合金である。支持部材２は、図１６および図１７に示すように、ダイパッド部２５１、複数のインナーリード部２５２および複数のアウターリード部２５３を含む。 The support member 2 is a so-called lead frame. The constituent material of the support member 2 is, for example, copper or a copper alloy. As shown in FIGS. 16 and 17, the support member 2 includes a die pad portion 251, a plurality of inner lead portions 252, and a plurality of outer lead portions 253.
　ダイパッド部２５１は、金属部材３０が接合されており、当該金属部材３０を介して、半導体素子１０が搭載されている。ダイパッド部２５１は、図１６および図１７に示すように、ダイパッド部２５１のｚ１方向を向く面を除き、封止部材７に覆われている。つまり、ダイパッド部２５１のｚ１方向を向く面は、封止部材７から露出している。 A metal member 30 is joined to the die pad portion 251, and the semiconductor element 10 is mounted via the metal member 30. As shown in FIGS. 16 and 17, the die pad portion 251 is covered with the sealing member 7 except for the surface of the die pad portion 251 facing the z1 direction. That is, the surface of the die pad portion 251 facing the z1 direction is exposed from the sealing member 7.
　複数のインナーリード部２５２はそれぞれ、ダイパッド部２５１から離間しており、かつ、封止部材７に覆われた部分である。各インナーリード部２５２には、各接続部材６の一端が接合されている。半導体装置Ａ３における支持部材２は、２つのインナーリード部２５２を備えている。 Each of the plurality of inner lead portions 252 is a portion that is separated from the die pad portion 251 and is covered with the sealing member 7. One end of each connecting member 6 is joined to each inner lead portion 252. The support member 2 in the semiconductor device A3 includes two inner lead portions 252.
　複数のアウターリード部２５３はそれぞれ、複数のインナーリード部２５２のいずれかに繋がり、かつ、封止部材７から露出した部分である。複数のアウターリード部２５３は、半導体装置Ａ３の端子であり、電気製品などの配線基板に接合されうる。 Each of the plurality of outer lead portions 253 is a portion connected to any of the plurality of inner lead portions 252 and exposed from the sealing member 7. The plurality of outer lead portions 253 are terminals of the semiconductor device A3 and can be joined to a wiring board such as an electric product.
　複数の接続部材６はそれぞれ、ボンディングワイヤである。なお、各接続部材６は、ボンディングワイヤの代わりに、金属リードやボンディングリボンなどを用いてもよい。半導体装置Ａ３は、図１６に示すように、２つの接続部材６を備えている。なお、接続部材６の数は、特に限定されない。図１６に示すように、２つの接続部材６の一方は、半導体素子１０の第３電極１３と、２つのインナーリード部２５２の一方とに接合され、これらを導通させる。２つの接続部材６の他方は、半導体素子１０の第１電極１１と、２つのインナーリード部２５２の他方とに接合され、これらを導通させる。 Each of the plurality of connecting members 6 is a bonding wire. In addition, each connecting member 6 may use a metal lead, a bonding ribbon, or the like instead of the bonding wire. As shown in FIG. 16, the semiconductor device A3 includes two connecting members 6. The number of connecting members 6 is not particularly limited. As shown in FIG. 16, one of the two connecting members 6 is joined to the third electrode 13 of the semiconductor element 10 and one of the two inner lead portions 252 to conduct them. The other of the two connecting members 6 is joined to the first electrode 11 of the semiconductor element 10 and the other of the two inner lead portions 252 to conduct them.
　以上のように構成された半導体装置Ａ３の作用効果は、次の通りである。 The effects of the semiconductor device A3 configured as described above are as follows.
　半導体装置Ａ３によれば、半導体素子１０、支持部材２および金属部材３０を備えている。半導体素子１０は、第１接合層４１によって、金属部材３０に接合されており、金属部材３０は、第２接合層４２によって、支持部材２に接合されている。金属部材３０は、複数の細孔３１が形成された多孔質体である。したがって、半導体装置Ａ３は、半導体装置Ａ１と同様に、金属部材３０に接する第２接合層４２にかかる熱応力を緩和させることができるので、第２接合層４２の凝集破壊を抑制できる。つまり、半導体装置Ａ３は、接合不良や導通不良などの製品故障の発生が抑制されるので、信頼性を向上させることができる。 According to the semiconductor device A3, the semiconductor element 10, the support member 2, and the metal member 30 are provided. The semiconductor element 10 is bonded to the metal member 30 by the first bonding layer 41, and the metal member 30 is bonded to the support member 2 by the second bonding layer 42. The metal member 30 is a porous body in which a plurality of pores 31 are formed. Therefore, similarly to the semiconductor device A1, the semiconductor device A3 can relax the thermal stress applied to the second bonding layer 42 in contact with the metal member 30, so that the cohesive failure of the second bonding layer 42 can be suppressed. That is, the semiconductor device A3 can improve the reliability because the occurrence of product failures such as poor bonding and poor conduction is suppressed.
　半導体装置Ａ３によれば、その他、半導体装置Ａ１（Ａ２）と同一あるいは類似の構成によって、半導体装置Ａ１（Ａ２）と同様の効果を奏することができる。 According to the semiconductor device A3, the same effect as that of the semiconductor device A1 (A2) can be obtained by the same or similar configuration as that of the semiconductor device A1 (A2).
　第３実施形態では、半導体装置Ａ３は、いわゆるＴＯパッケージ型である場合を示したが、これに限定されず、ＳＯＰ（Small Outline Package）、Ｎｏｎ－Ｌｅａｄパッケージ、あるいは、ＢＧＡ（Ball Grid Array）パッケージなど様々な形式の半導体パッケージに適用できる。 In the third embodiment, the semiconductor device A3 is a so-called TO package type, but the present invention is not limited to this, and the SOP (Small Outline Package), Non-Lead package, or BGA (Ball Grid Array) package is used. It can be applied to various types of semiconductor packages.
　第３実施形態では、支持部材２がリードフレームである場合を示したが、これに限定されず、インタポーザ、プリント基板、ＤＢＣ（Direct Bonded Copper）基板あるいはＤＢＡ（Direct Bonded Aluminum）基板などであってもよい。 In the third embodiment, the case where the support member 2 is a lead frame is shown, but the present invention is not limited to this, and the support member 2 is an interposer, a printed circuit board, a DBC (Direct Bonded Copper) board, a DBA (Direct Bonded Aluminum) board, or the like. May be good.
　図１８～図２４は、金属部材３０の各変形例を示している。図１８～図２４に示す金属部材３０は、半導体装置Ａ１～Ａ３における各金属部材３０の代わりに用いることができる。 18 to 24 show each modification of the metal member 30. The metal members 30 shown in FIGS. 18 to 24 can be used in place of the metal members 30 in the semiconductor devices A1 to A3.
　図１８に示す金属部材３０において、複数の細孔３１は、複数の第１貫通孔３１Ａ、複数の第２貫通孔３１Ｂおよび複数の第３貫通孔３１Ｃを含む。 In the metal member 30 shown in FIG. 18, the plurality of pores 31 include a plurality of first through holes 31A, a plurality of second through holes 31B, and a plurality of third through holes 31C.
　複数の第１貫通孔３１Ａはそれぞれ、主面３０１から裏面３０２までｚ方向に繋がっている。複数の第１貫通孔３１Ａ（複数の細孔３１の一部）は、主面３０１および裏面３０２に表れている。各第１貫通孔３１Ａの貫通方向は、ｚ方向に沿う直線状に限定されず、屈曲あるいは湾曲していてもよいし、傾斜していてもよいし、また、すべての第１貫通孔３１Ａの貫通方向が揃っていてもよいし揃っていなくてもよい。複数の第１貫通孔３１Ａは、平面視において、たとえば不規則に配置されている。なお、複数の第１貫通孔３１Ａは、不規則に配置されているのではなく、たとえば正方格子状、矩形格子状、三角格子状、六角格子状、あるいは、斜方格子状など規則的に配置されていてもよい。各第１貫通孔３１Ａが、特許請求の範囲に記載の「第１孔」に相当する。 Each of the plurality of first through holes 31A is connected in the z direction from the main surface 301 to the back surface 302. The plurality of first through holes 31A (part of the plurality of pores 31) appear on the main surface 301 and the back surface 302. The penetration direction of each first through hole 31A is not limited to a linear shape along the z direction, and may be bent or curved, may be inclined, and all of the first through holes 31A may be inclined. The penetration directions may or may not be aligned. The plurality of first through holes 31A are arranged irregularly, for example, in a plan view. The plurality of first through holes 31A are not irregularly arranged, but are regularly arranged, for example, in a square lattice shape, a rectangular lattice shape, a triangular lattice shape, a hexagonal lattice shape, or an orthorhombic lattice shape. It may have been done. Each first through hole 31A corresponds to the "first hole" described in the claims.
　複数の第２貫通孔３１Ｂはそれぞれ、一対の側面３０３の一方から他方までｘ方向に繋がっている。複数の第２貫通孔３１Ｂ（複数の細孔３１の一部）は、一対の側面３０３のそれぞれに表れている。各第２貫通孔３１Ｂの貫通方向は、ｘ方向に沿う直線状に限定されず、屈曲あるいは湾曲していてもよいし、ｘ方向に対して傾斜していてもよいし、また、また、すべての第２貫通孔３１Ｂの貫通方向が揃っていてもよいし揃っていなくてもよい。複数の第２貫通孔３１Ｂは、ｘ方向に見て、たとえば不規則に配置されている。なお、複数の第２貫通孔３１Ｂは、不規則に配置されているのではなく、たとえば正方格子状、矩形格子状、三角格子状、六角格子状、あるいは、斜方格子状など規則的に配置されていてもよい。各第２貫通孔３１Ｂが、特許請求の範囲に記載の「第２孔」に相当する。 Each of the plurality of second through holes 31B is connected in the x direction from one of the pair of side surfaces 303 to the other. The plurality of second through holes 31B (part of the plurality of pores 31) appear on each of the pair of side surfaces 303. The penetration direction of each of the second through holes 31B is not limited to a straight line along the x direction, may be bent or curved, may be inclined with respect to the x direction, or all. The penetration directions of the second through holes 31B may or may not be aligned. The plurality of second through holes 31B are arranged irregularly, for example, when viewed in the x direction. The plurality of second through holes 31B are not arranged irregularly, but are arranged regularly, for example, in a square lattice shape, a rectangular lattice shape, a triangular lattice shape, a hexagonal lattice shape, or an orthorhombic lattice shape. It may have been done. Each second through hole 31B corresponds to the "second hole" described in the claims.
　複数の第３貫通孔３１Ｃはそれぞれ、一対の側面３０４の一方から他方までｙ方向に繋がっている。複数の第３貫通孔３１Ｃ（複数の細孔３１の一部）は、一対の側面３０４のそれぞれに表れている。各第３貫通孔３１Ｃの貫通方向は、ｙ方向に沿う直線状に限定されず、屈曲あるいは湾曲していてもよいし、ｙ方向に対して傾斜していてもよいし、また、すべての第３貫通孔３１Ｃの貫通方向が揃っていてもよいし揃っていなくてもよい。複数の第３貫通孔３１Ｃは、ｙ方向に見て、たとえば不規則に配置されている。なお、複数の第３貫通孔３１Ｃは、不規則に配置されているのではなく、たとえば正方格子状、矩形格子状、三角格子状、六角格子状、あるいは、斜方格子状など規則的に配置されていてもよい。各第３貫通孔３１Ｃが、特許請求の範囲に記載の「第３孔」に相当する。 Each of the plurality of third through holes 31C is connected in the y direction from one of the pair of side surfaces 304 to the other. The plurality of third through holes 31C (part of the plurality of pores 31) appear on each of the pair of side surfaces 304. The penetration direction of each third through hole 31C is not limited to a straight line along the y direction, may be bent or curved, may be inclined with respect to the y direction, and all the third through holes 31C. The penetration directions of the three through holes 31C may or may not be aligned. The plurality of third through holes 31C are arranged irregularly, for example, when viewed in the y direction. The plurality of third through holes 31C are not arranged irregularly, but are arranged regularly, for example, in a square lattice shape, a rectangular lattice shape, a triangular lattice shape, a hexagonal lattice shape, or an orthorhombic lattice shape. It may have been done. Each third through hole 31C corresponds to the "third hole" described in the claims.
　図１９に示す金属部材３０においては、複数の細孔３１は、複数の第１貫通孔３１Ａおよび複数の第２貫通孔３１Ｂを含まず、複数の第３貫通孔３１Ｃを含む。なお、図１９においては、複数の細孔３１が、複数の第３貫通孔３１Ｃを含んだ場合を示すが、これらの代わりに、複数の第２貫通孔３１Ｂを含んだ構成であってもよい。 In the metal member 30 shown in FIG. 19, the plurality of pores 31 do not include the plurality of first through holes 31A and the plurality of second through holes 31B, but include the plurality of third through holes 31C. Although FIG. 19 shows a case where the plurality of pores 31 include a plurality of third through holes 31C, a configuration may include a plurality of second through holes 31B instead of these. ..
　図２０に示す金属部材３０においては、複数の細孔３１は、複数の第１貫通孔３１Ａを含まず、複数の第２貫通孔３１Ｂおよび複数の第３貫通孔３１Ｃを含む。 In the metal member 30 shown in FIG. 20, the plurality of pores 31 do not include the plurality of first through holes 31A, but include the plurality of second through holes 31B and the plurality of third through holes 31C.
　図２１に示す金属部材３０においては、複数の細孔３１は、複数の第２貫通孔３１Ｂおよび複数の第３貫通孔３１Ｃを含まず、複数の第１貫通孔３１Ａを含む。 In the metal member 30 shown in FIG. 21, the plurality of pores 31 do not include the plurality of second through holes 31B and the plurality of third through holes 31C, but include the plurality of first through holes 31A.
　図２２に示す金属部材３０においては、金属部材３０の主面３０１のうち、半導体素子１０が接合される部分（平面視において半導体素子１０に重なる部分）には、複数の第１貫通孔３１Ａが形成されていない。なお、図２２においては、図２１に示す金属部材３０において、複数の第１貫通孔３１Ａが形成されていない領域を設けた場合を示すが、これに限定されず、図１８に示す金属部材３０においても同様に、複数の第１貫通孔３１Ａが形成されていない領域を設けてもよい。 In the metal member 30 shown in FIG. 22, a plurality of first through holes 31A are provided in a portion of the main surface 301 of the metal member 30 to which the semiconductor element 10 is joined (a portion overlapping the semiconductor element 10 in a plan view). Not formed. Note that FIG. 22 shows a case where the metal member 30 shown in FIG. 21 is provided with a region in which a plurality of first through holes 31A are not formed, but the present invention is not limited to this, and the metal member 30 shown in FIG. 18 is not limited to this. Similarly, a region in which a plurality of first through holes 31A are not formed may be provided.
　なお、図１８～図２２に示す各金属部材３０においても、複数の細孔３１の占有率は、たとえば１０％以上７０％以下である。 Also in each of the metal members 30 shown in FIGS. 18 to 22, the occupancy rate of the plurality of pores 31 is, for example, 10% or more and 70% or less.
　図１８～図２２に示す各金属部材３０を用いた場合であっても、複数の細孔３１（複数の第１貫通孔３１Ａ、複数の第２貫通孔３１Ｂおよび複数の第３貫通孔３１Ｃ）付近において、半導体素子１０の発熱に起因する金属部材３０の熱ひずみが生じるため、各細孔３１付近の熱応力が緩和される。したがって、各金属部材３０の熱膨張による熱応力を緩和させることができるので、当該金属部材３０を配線層２２に接合するための第２接合層４２にかかる熱応力が緩和し、当該第２接合層４２の凝集破壊を抑制できる。よって、図１８～図２２に示す各金属部材３０を用いた半導体装置においても、接合不良や導通不良などの製品故障の発生が抑制されるので、信頼性を向上させることができる。 Even when the metal members 30 shown in FIGS. 18 to 22 are used, a plurality of pores 31 (a plurality of first through holes 31A, a plurality of second through holes 31B, and a plurality of third through holes 31C). Since thermal strain of the metal member 30 is generated in the vicinity due to heat generation of the semiconductor element 10, the thermal stress in the vicinity of each pore 31 is relaxed. Therefore, since the thermal stress due to the thermal expansion of each metal member 30 can be relaxed, the thermal stress applied to the second bonding layer 42 for joining the metal member 30 to the wiring layer 22 is relaxed, and the second bonding is performed. The cohesive failure of the layer 42 can be suppressed. Therefore, even in the semiconductor device using each of the metal members 30 shown in FIGS. 18 to 22, the occurrence of product failure such as bonding failure and conduction failure is suppressed, so that reliability can be improved.
　図１９～図２２に示す各金属部材３０は、図１８に示す金属部材３０と比較して、複数の第１貫通孔３１Ａ、複数の第２貫通孔３１Ｂあるいは複数の第３貫通孔３１Ｃのいずれかが形成されていない。そのため、熱を拡散するための領域が大きいので、放熱性の向上を図る上で有効である。ただし、複数の細孔３１が形成されていない金属部材と比較すると、熱応力を緩和させることができるが、図１８に示す金属部材３０と比較すると、熱応力の緩和効果は低減する可能性がある。 Each of the metal members 30 shown in FIGS. 19 to 22 has a plurality of first through holes 31A, a plurality of second through holes 31B, or a plurality of third through holes 31C, as compared with the metal member 30 shown in FIG. The metal is not formed. Therefore, since the area for diffusing heat is large, it is effective in improving heat dissipation. However, the thermal stress can be relaxed as compared with the metal member in which the plurality of pores 31 are not formed, but the effect of relaxing the thermal stress may be reduced as compared with the metal member 30 shown in FIG. is there.
　図２３および図２４に示す各金属部材３０は、金属ワイヤをたとえば所定の金型を用いて圧縮することにより、複雑に屈曲した状態でひと塊にしたものである。この金属ワイヤの構成材料は、たとえば銅あるいは銅合金である。なお、各金属部材３０は、１つの金属ワイヤから構成されていてもよいし、複数の金属ワイヤから構成されていてもよい。図２３は、直方体状の塊にした場合を示しており、図２４は、円環状の塊にした場合を示している。なお、本変形例にかかる金属部材３０は、直方体状あるいは円環状に限定されず、その他、立方体状、円柱状などであってもよい。当該各金属部材３０は、複雑に絡み合った金属ワイヤの隙間に、複数の空間が取り込まれている。このような構成の各金属部材３０は、複数の細孔３１が形成された多孔質体である。 Each of the metal members 30 shown in FIGS. 23 and 24 is formed by compressing a metal wire using, for example, a predetermined mold, in a complicatedly bent state. The constituent material of this metal wire is, for example, copper or a copper alloy. In addition, each metal member 30 may be composed of one metal wire, or may be composed of a plurality of metal wires. FIG. 23 shows a case where a rectangular parallelepiped-shaped mass is formed, and FIG. 24 shows a case where an annular mass is formed. The metal member 30 according to this modification is not limited to a rectangular parallelepiped shape or an annular shape, and may be a cube shape or a columnar shape. In each of the metal members 30, a plurality of spaces are incorporated in the gaps between the metal wires that are intricately intertwined. Each metal member 30 having such a structure is a porous body in which a plurality of pores 31 are formed.
　図２３および図２４に示す各金属部材３０を用いた場合であっても、先述の空間付近において、半導体素子１０の発熱に起因する金属部材３０の熱ひずみが生じるため、空間付近の熱応力が緩和される。したがって、各金属部材３０の熱膨張による熱応力を緩和させることができるので、当該金属部材３０を配線層２２に接合するための第２接合層４２にかかる熱応力が緩和し、第２接合層４２の凝集破壊を抑制できる。よって、図２３および図２４に示す各金属部材３０を用いた半導体装置においても、接合不良や導通不良などの製品故障の発生が抑制されるので、信頼性を向上させることができる。 Even when the metal members 30 shown in FIGS. 23 and 24 are used, thermal strain of the metal member 30 due to heat generation of the semiconductor element 10 occurs in the vicinity of the above-mentioned space, so that thermal stress in the vicinity of the space is generated. It will be relaxed. Therefore, since the thermal stress due to the thermal expansion of each metal member 30 can be relaxed, the thermal stress applied to the second bonding layer 42 for joining the metal member 30 to the wiring layer 22 is relaxed, and the second bonding layer is relaxed. The cohesive failure of 42 can be suppressed. Therefore, even in the semiconductor device using each of the metal members 30 shown in FIGS. 23 and 24, the occurrence of product failure such as bonding failure and conduction failure is suppressed, so that reliability can be improved.
　本開示にかかる半導体装置は、上記した実施形態に限定されるものではない。本開示の半導体装置の各部の具体的な構成は、種々に設計変更自在である。 The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device of the present disclosure can be freely redesigned.
　本開示にかかる半導体装置は、以下の付記に関する実施形態を含む。
　［付記１］
　支持部材と、
　厚さ方向において離間した第１主面および第１裏面を有し、前記第１裏面が前記支持部材に対向して、前記支持部材に接合された金属部材と、
　前記支持部材と前記金属部材とを接合する接合層と、
　前記第１主面に対向し、前記金属部材に接合された半導体素子と、
　前記支持部材、前記金属部材、前記接合層および前記半導体素子を覆う封止部材と、
を備えており、
　前記金属部材は、複数の細孔が形成された多孔質体である、半導体装置。
　［付記２］
　前記複数の細孔は、不規則に配置されている、付記１に記載の半導体装置。
　［付記３］
　前記複数の細孔は、前記第１主面に表れた第１孔を有している、付記１または付記２に記載の半導体装置。
　［付記４］
　前記第１孔は、前記第１主面から前記第１裏面まで前記厚さ方向に繋がる貫通孔である、付記３に記載の半導体装置。
　［付記５］
　前記金属部材は、前記厚さ方向に直交する第１方向において離間した一対の第１側面を有し、
　前記複数の細孔は、前記一対の第１側面の少なくとも一方に表れた第２孔を有している、付記１ないし付記４のいずれかに記載の半導体装置。
　［付記６］
　前記第２孔は、前記一対の第１側面の一方から他方まで前記第１方向に繋がる貫通孔である、付記５に記載の半導体装置。
　［付記７］
　前記金属部材は、前記厚さ方向および前記第１方向の両方に直交する第２方向において離間した一対の第２側面を有し、
　前記複数の細孔は、前記一対の第２側面の少なくとも一方に表れた第３孔を有している、付記５または付記６に記載の半導体装置。
　［付記８］
　前記第３孔は、前記一対の第２側面の一方から他方まで前記第２方向に繋がる貫通孔である、付記７に記載の半導体装置。
　［付記９］
　前記金属部材に対する前記複数の細孔の占有率は、１０％以上７０％以下である、付記１ないし付記８のいずれかに記載の半導体装置。
　［付記１０］
　前記支持部材は、絶縁基板および配線層を含んでおり、
　前記配線層は、前記厚さ方向において離間した第２主面および第２裏面を有し、前記第２裏面が前記絶縁基板に接合され、
　前記金属部材は、前記第１裏面が前記第２主面に対向して、前記配線層に接合されている、付記１ないし付記９のいずれかに記載の半導体装置。
　［付記１１］
　前記絶縁基板の裏面は、前記封止部材から露出している、付記１０に記載の半導体装置。
　［付記１２］
　前記接合層は、はんだである、付記１ないし付記１１のいずれかに記載の半導体装置。
　［付記１３］
　前記半導体素子は、導電性接合材によって、前記金属部材に接合されている、付記１ないし付記１２のいずれかに記載の半導体装置。
　［付記１４］
　前記複数の細孔のうちの一部の細孔には、前記封止部材が充填されている、付記１ないし付記１３のいずれかに記載の半導体装置。
　［付記１５］
　前記複数の細孔は、前記封止部材が充填された前記一部の細孔を除いて、気孔である、付記１４に記載の半導体装置。
　［付記１６］
　前記金属部材の構成材料は、銅あるいは銅合金である、付記１ないし付記１５のいずれかに記載の半導体装置。
　［付記１７］
　前記金属部材の厚さは、前記支持部材の厚さよりも大きい、付記１ないし付記１６のいずれかに記載の半導体装置。
　［付記１８］
　前記金属部材の厚さは、０．５ｍｍ以上５ｍｍ以下である、付記１ないし付記１７のいずれかに記載の半導体装置。 The semiconductor device according to the present disclosure includes embodiments relating to the following appendices.
[Appendix 1]
Support members and
A metal member having a first main surface and a first back surface separated in the thickness direction, with the first back surface facing the support member and joined to the support member.
A bonding layer that joins the support member and the metal member,
A semiconductor element facing the first main surface and bonded to the metal member,
The supporting member, the metal member, the bonding layer, and the sealing member covering the semiconductor element,
Is equipped with
The metal member is a semiconductor device which is a porous body in which a plurality of pores are formed.
[Appendix 2]
The semiconductor device according to Appendix 1, wherein the plurality of pores are irregularly arranged.
[Appendix 3]
The semiconductor device according to Appendix 1 or Appendix 2, wherein the plurality of pores have a first hole appearing on the first main surface.
[Appendix 4]
The semiconductor device according to Appendix 3, wherein the first hole is a through hole that connects the first main surface to the first back surface in the thickness direction.
[Appendix 5]
The metal member has a pair of first sides separated in a first direction orthogonal to the thickness direction.
The semiconductor device according to any one of Supplementary note 1 to Supplementary note 4, wherein the plurality of pores have a second hole appearing on at least one of the pair of first side surfaces.
[Appendix 6]
The semiconductor device according to Appendix 5, wherein the second hole is a through hole that connects one to the other of the pair of first side surfaces in the first direction.
[Appendix 7]
The metal member has a pair of second sides separated in a second direction orthogonal to both the thickness direction and the first direction.
The semiconductor device according to Appendix 5 or Appendix 6, wherein the plurality of pores have a third hole appearing on at least one of the pair of second side surfaces.
[Appendix 8]
The semiconductor device according to Appendix 7, wherein the third hole is a through hole that connects one to the other of the pair of second side surfaces in the second direction.
[Appendix 9]
The semiconductor device according to any one of Appendix 1 to Appendix 8, wherein the occupancy of the plurality of pores with respect to the metal member is 10% or more and 70% or less.
[Appendix 10]
The support member includes an insulating substrate and a wiring layer.
The wiring layer has a second main surface and a second back surface separated in the thickness direction, and the second back surface is joined to the insulating substrate.
The semiconductor device according to any one of Supplementary note 1 to Supplementary note 9, wherein the metal member has a first back surface facing the second main surface and is joined to the wiring layer.
[Appendix 11]
The semiconductor device according to Appendix 10, wherein the back surface of the insulating substrate is exposed from the sealing member.
[Appendix 12]
The semiconductor device according to any one of Supplementary note 1 to Supplementary note 11, wherein the bonding layer is solder.
[Appendix 13]
The semiconductor device according to any one of Supplementary note 1 to Supplementary note 12, wherein the semiconductor element is bonded to the metal member by a conductive bonding material.
[Appendix 14]
The semiconductor device according to any one of Supplementary note 1 to Supplementary note 13, wherein some of the pores of the plurality of pores are filled with the sealing member.
[Appendix 15]
The semiconductor device according to Appendix 14, wherein the plurality of pores are pores except for a part of the pores filled with the sealing member.
[Appendix 16]
The semiconductor device according to any one of Appendix 1 to Appendix 15, wherein the constituent material of the metal member is copper or a copper alloy.
[Appendix 17]
The semiconductor device according to any one of Supplementary note 1 to Supplementary note 16, wherein the thickness of the metal member is larger than the thickness of the support member.
[Appendix 18]
The semiconductor device according to any one of Supplementary note 1 to Supplementary note 17, wherein the thickness of the metal member is 0.5 mm or more and 5 mm or less.

Claims (18)

  1. 　支持部材と、
    　厚さ方向において離間した第１主面および第１裏面を有し、前記第１裏面が前記支持部材に対向して、前記支持部材に接合された金属部材と、
    　前記支持部材と前記金属部材とを接合する接合層と、
    　前記第１主面に対向し、前記金属部材に接合された半導体素子と、
    　前記支持部材、前記金属部材、前記接合層および前記半導体素子を覆う封止部材と、
    を備えており、
    　前記金属部材は、複数の細孔が形成された多孔質体である、半導体装置。     Support members and
    A metal member having a first main surface and a first back surface separated in the thickness direction, with the first back surface facing the support member and joined to the support member.
    A bonding layer that joins the support member and the metal member,
    A semiconductor element facing the first main surface and bonded to the metal member,
    The supporting member, the metal member, the bonding layer, and the sealing member covering the semiconductor element,
    Is equipped with
    A semiconductor device in which the metal member is a porous body in which a plurality of pores are formed.
  2. 　前記複数の細孔は、不規則に配置されている、
    請求項１に記載の半導体装置。     The plurality of pores are irregularly arranged,
    The semiconductor device according to claim 1.
  3. 　前記複数の細孔は、前記第１主面に表れた第１孔を有している、
    請求項１または請求項２に記載の半導体装置。     The plurality of pores have a first hole appearing on the first main surface.
    The semiconductor device according to claim 1 or 2.
  4. 　前記第１孔は、前記第１主面から前記第１裏面まで前記厚さ方向に繋がる貫通孔である、
    請求項３に記載の半導体装置。     The first hole is a through hole that connects from the first main surface to the first back surface in the thickness direction.
    The semiconductor device according to claim 3.
  5. 　前記金属部材は、前記厚さ方向に直交する第１方向において離間した一対の第１側面を有し、
    　前記複数の細孔は、前記一対の第１側面の少なくとも一方に表れた第２孔を有している、
    請求項１ないし請求項４のいずれか一項に記載の半導体装置。     The metal member has a pair of first sides separated in a first direction orthogonal to the thickness direction.
    The plurality of pores have a second pore appearing on at least one of the pair of first side surfaces.
    The semiconductor device according to any one of claims 1 to 4.
  6. 　前記第２孔は、前記一対の第１側面の一方から他方まで前記第１方向に繋がる貫通孔である、
    請求項５に記載の半導体装置。     The second hole is a through hole that connects one of the pair of first side surfaces to the other in the first direction.
    The semiconductor device according to claim 5.
  7. 　前記金属部材は、前記厚さ方向および前記第１方向の両方に直交する第２方向において離間した一対の第２側面を有し、
    　前記複数の細孔は、前記一対の第２側面の少なくとも一方に表れた第３孔を有している、
    請求項５または請求項６に記載の半導体装置。     The metal member has a pair of second sides separated in a second direction orthogonal to both the thickness direction and the first direction.
    The plurality of pores have a third pore appearing on at least one of the pair of second side surfaces.
    The semiconductor device according to claim 5 or 6.
  8. 　前記第３孔は、前記一対の第２側面の一方から他方まで前記第２方向に繋がる貫通孔である、
    請求項７に記載の半導体装置。     The third hole is a through hole that connects one to the other of the pair of second side surfaces in the second direction.
    The semiconductor device according to claim 7.
  9. 　前記金属部材に対する前記複数の細孔の占有率は、１０％以上７０％以下である、
    請求項１ないし請求項８のいずれか一項に記載の半導体装置。     The occupancy of the plurality of pores with respect to the metal member is 10% or more and 70% or less.
    The semiconductor device according to any one of claims 1 to 8.
  10. 　前記支持部材は、絶縁基板および配線層を含んでおり、
    　前記配線層は、前記厚さ方向において離間した第２主面および第２裏面を有し、前記第２裏面が前記絶縁基板に接合され、
    　前記金属部材は、前記第１裏面が前記第２主面に対向して、前記配線層に接合されている、請求項１ないし請求項９のいずれか一項に記載の半導体装置。     The support member includes an insulating substrate and a wiring layer.
    The wiring layer has a second main surface and a second back surface separated in the thickness direction, and the second back surface is joined to the insulating substrate.
    The semiconductor device according to any one of claims 1 to 9, wherein the metal member has a first back surface facing the second main surface and is joined to the wiring layer.
  11. 　前記絶縁基板の裏面は、前記封止部材から露出している、
    請求項１０に記載の半導体装置。     The back surface of the insulating substrate is exposed from the sealing member.
    The semiconductor device according to claim 10.
  12. 　前記接合層は、はんだである、
    請求項１ないし請求項１１のいずれか一項に記載の半導体装置。     The bonding layer is solder.
    The semiconductor device according to any one of claims 1 to 11.
  13. 　前記半導体素子は、導電性接合材によって、前記金属部材に接合されている、
    請求項１ないし請求項１２のいずれか一項に記載の半導体装置。     The semiconductor element is bonded to the metal member by a conductive bonding material.
    The semiconductor device according to any one of claims 1 to 12.
  14. 　前記複数の細孔のうちの一部の細孔には、前記封止部材が充填されている、
    請求項１ないし請求項１３のいずれか一項に記載の半導体装置。     Some of the plurality of pores are filled with the sealing member.
    The semiconductor device according to any one of claims 1 to 13.
  15. 　前記複数の細孔は、前記封止部材が充填された前記一部の細孔を除いて、気孔である、請求項１４に記載の半導体装置。 The semiconductor device according to claim 14, wherein the plurality of pores are pores except for a part of the pores filled with the sealing member.
  16. 　前記金属部材の構成材料は、銅あるいは銅合金である、
    請求項１ないし請求項１５のいずれか一項に記載の半導体装置。     The constituent material of the metal member is copper or a copper alloy.
    The semiconductor device according to any one of claims 1 to 15.
  17. 　前記金属部材の厚さは、前記支持部材の厚さよりも大きい、
    請求項１ないし請求項１６のいずれか一項に記載の半導体装置。     The thickness of the metal member is larger than the thickness of the support member.
    The semiconductor device according to any one of claims 1 to 16.
  18. 　前記金属部材の厚さは、０．５ｍｍ以上５ｍｍ以下である、
    請求項１ないし請求項１７のいずれか一項に記載の半導体装置。     The thickness of the metal member is 0.5 mm or more and 5 mm or less.
    The semiconductor device according to any one of claims 1 to 17.
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