JPH06204219A - 半導体装置のコンタクト構造形成方法 - Google Patents
半導体装置のコンタクト構造形成方法Info
- Publication number
- JPH06204219A JPH06204219A JP5254414A JP25441493A JPH06204219A JP H06204219 A JPH06204219 A JP H06204219A JP 5254414 A JP5254414 A JP 5254414A JP 25441493 A JP25441493 A JP 25441493A JP H06204219 A JPH06204219 A JP H06204219A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- material layer
- forming
- layer
- contact structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 94
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 239000000463 material Substances 0.000 claims abstract description 121
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 30
- 238000000151 deposition Methods 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000002131 composite material Substances 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 description 11
- 238000007796 conventional method Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1992P18788 | 1992-10-13 | ||
| KR1019920018788A KR940010196A (ko) | 1992-10-13 | 1992-10-13 | 반도체장치의 콘택구조 형성방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06204219A true JPH06204219A (ja) | 1994-07-22 |
Family
ID=19341068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5254414A Pending JPH06204219A (ja) | 1992-10-13 | 1993-10-12 | 半導体装置のコンタクト構造形成方法 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH06204219A (ko) |
| KR (1) | KR940010196A (ko) |
-
1992
- 1992-10-13 KR KR1019920018788A patent/KR940010196A/ko not_active Application Discontinuation
-
1993
- 1993-10-12 JP JP5254414A patent/JPH06204219A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| KR940010196A (ko) | 1994-05-24 |
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