JPH06151851A

JPH06151851A - Structure of thin film transistor

Info

Publication number: JPH06151851A
Application number: JP31625892A
Authority: JP
Inventors: Masatoshi Utaka; 正俊右高; Shigeichi Yamamoto; 茂市山本; Michitaka Noda; 理崇野田; Junji Nakamura; 潤二中村
Original assignee: Individual
Current assignee: Individual
Priority date: 1992-10-29
Filing date: 1992-10-29
Publication date: 1994-05-31

Abstract

PURPOSE:To achieve a high field effect mobility and low power consumption by so structuring a thin film transistor that both faces of a main semiconductor layer has at least one gate electrode, and by applying voltage to one of these gates to control the carrier concentration of the area near the other semiconductor surface. CONSTITUTION:When a transistor is in the off-state, positive or negative voltage is applied to one gate electrode 2, and the concentration of electrons or holes in the semiconductor layer in proximity to the other gate electrode 9 is thereby controlled, the leakage current being reduced. When the transistor is in the on-state, contrarily, positive or negative voltage is applied to the source 6 and drain 7 electrodes and auxiliary gate electrodes 3 opposite thereto with a semiconductor film and insulating film in-between, and the carrier concentration is thereby increased in the contact area between the source 6 and drain 7 electrodes and the semiconductor. This reduces the contact resistance and improves the field effect mobility. These two effects result in a thin film transistor with a less power consumption and high field effect mobility.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は消費電力が少なく，かつ
高電界効果移動度を持った薄膜トランジスタの構造に関
するものである．BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film transistor having low power consumption and high field effect mobility.

【０００２】[0002]

【従来の技術】ＴＦＴはアクティブマトリックス方式の
液晶ディスプレイの駆動用スイッチング素子として主に
用いられており，通常はガラス基板上に形成されてい
る．そのためシリコン基板を用いたプロセスのように３
００度をこえる処理ができない．シリコン薄膜の堆積に
ついては単結晶シリコンや多結晶シリコンよりも堆積温
度が低いアモルファスシリコンが用いられている．しか
しアモルファスシリコンは堆積時よりｎ型の導電性を示
し，オフ状態においてもソース電極とゲート電極の間に
ある程度の電流が流れ，これが消費電力の増加の原因と
なっていた．2. Description of the Related Art A TFT is mainly used as a driving switching element of an active matrix type liquid crystal display, and is usually formed on a glass substrate. Therefore, like the process using a silicon substrate,
It cannot process over 00 degrees. Amorphous silicon, which has a lower deposition temperature than single-crystal silicon or polycrystalline silicon, is used for the deposition of silicon thin films. However, amorphous silicon exhibits n-type conductivity from the time of deposition, and a certain amount of current flows between the source electrode and the gate electrode even in the off state, which causes increase in power consumption.

【０００３】アモルファスシリコンは，単結晶シリコン
や多結晶シリコンと比較して電界効果移動度が低く，反
応速度が遅くなるという欠点がある．この問題が大画面
化，高精細化，高開口率化といった液晶ディスプレイに
対する最近の要求の実現を阻害していた．Amorphous silicon has the drawback that it has a lower field effect mobility and a slower reaction rate than single crystal silicon or polycrystalline silicon. This problem has hindered the realization of recent demands for liquid crystal displays such as large screens, high definition, and high aperture ratio.

【０００４】３００度を越える高温処理ができないた
め，ソース，ドレイン電極と半導体層の間に不純物を高
濃度に拡散した低抵抗層の設定が困難である．そのため
アモルファスシリコンとソース，ドレイン電極の良好な
オーミック接触がとれないといった問題がある．この大
きなコンタクト抵抗は電界効果移動度を低下させている
要因の一つであった．Since a high temperature treatment exceeding 300 ° C. cannot be performed, it is difficult to set a low resistance layer in which impurities are diffused in a high concentration between the source and drain electrodes and the semiconductor layer. Therefore, there is a problem that good ohmic contact cannot be established between the amorphous silicon and the source and drain electrodes. This large contact resistance was one of the factors that reduced the field effect mobility.

【０００５】[0005]

【発明が解決しようとする課題】解決しようとする問題
点は，トランジスタがオフ状態時における漏れ電流が原
因となっている高い消費電力．さらに高いソース及びド
レイン電極のコンタクト抵抗による電界効果移動度の低
下である．The problem to be solved is high power consumption due to leakage current when the transistor is in the off state. Furthermore, the field effect mobility decreases due to the higher contact resistance of the source and drain electrodes.

【０００６】[0006]

【課題を解決するための手段】本発明はトランジスタが
オフ状態の時のみソース，ドレイン間付近の半導体のキ
ャリア濃度を，新たに設定したゲート電極により低減す
ることによって，半導体の抵抗値を高め，漏れ電流を低
減した．一方トランジスタがオン状態の時には反対にキ
ャリア濃度を高くすることによって，チャネルの抵抗値
を下げ，高い電界効果移動度を実現することができた．
ソース，ドレイン電極のコンタクト抵抗の低減はソー
ス，ドレイン電極が存在する面と反対側の半導体層の面
に新たに設定した補助ゲート電極に，正または負の電圧
を印加することによってソース，ドレイン電極の近傍に
キャリアを集め，低抵抗半導体層を設定したのと同様の
効果を実現した．According to the present invention, the resistance value of the semiconductor is increased by reducing the carrier concentration of the semiconductor near the source and drain only by the newly set gate electrode only when the transistor is in the off state. The leakage current has been reduced. On the other hand, when the transistor is in the ON state, conversely, by increasing the carrier concentration, the resistance value of the channel was lowered and high field effect mobility could be realized.
The contact resistance of the source and drain electrodes is reduced by applying a positive or negative voltage to the auxiliary gate electrode newly set on the surface of the semiconductor layer opposite to the surface where the source and drain electrodes are present. Carriers were collected in the vicinity of and the same effect as setting the low-resistance semiconductor layer was realized.

【０００７】[0007]

【実施例】図１は，本発明の薄膜トランジスタの実施例
の断面図である．EXAMPLE FIG. 1 is a sectional view of an example of a thin film transistor of the present invention.

【図１】[Figure 1]

【０００８】ゲート電極２に電圧を印加することによっ
て，もう一方のゲート電極９の直下の半導体薄膜５とゲ
ート絶縁膜８との界面のキャリア濃度を制御することが
できる．ゲート電極９に電圧が印加されていない時，即
ちトランジスタがオフ状態の時はキャリア濃度を低下さ
せ，半導体の抵抗値を増加させ、漏れ電流を減らすこと
が可能となる．このことにより消費電力を低下させるこ
とができる．By applying a voltage to the gate electrode 2, the carrier concentration at the interface between the semiconductor thin film 5 and the gate insulating film 8 immediately below the other gate electrode 9 can be controlled. When no voltage is applied to the gate electrode 9, that is, when the transistor is in the off state, it is possible to reduce the carrier concentration, increase the resistance value of the semiconductor, and reduce the leakage current. This can reduce the power consumption.

【０００９】ゲート電極９に電圧が印加されている時，
即ちトランジスタがオン状態の時，ゲート電極９の直下
の半導体薄膜５とゲート絶縁膜８との界面のキャリア濃
度を高くして，電界効果移動度の良好なチャネルを形成
することが可能となる．When a voltage is applied to the gate electrode 9,
That is, when the transistor is in the ON state, the carrier concentration at the interface between the semiconductor thin film 5 directly below the gate electrode 9 and the gate insulating film 8 can be increased to form a channel with good field effect mobility.

【００１０】ソース電極６とドレイン電極７と半導体薄
膜５を挟んだ位置にある補助電極３に電圧を印加するこ
とによって，これらの電極と半導体層５の界面のキャリ
ア濃度を増加させ，電極と半導体層の間に低抵抗の半導
体層を設定した場合と同じ効果により，コンタクト抵抗
が小さくなり電界効果移動度が向上する．By applying a voltage to the auxiliary electrode 3 located at the position between the source electrode 6 and the drain electrode 7 and the semiconductor thin film 5, the carrier concentration at the interface between these electrodes and the semiconductor layer 5 is increased, and the electrode and semiconductor Due to the same effect as when a low resistance semiconductor layer is set between the layers, the contact resistance is reduced and the field effect mobility is improved.

【００１１】[0011]

【発明の効果】以上説明したように本発明の薄膜トラン
ジスタはオフ状態における漏れ電流の低減を実現するた
め及び，ソース，ドレイン電極のコンタクト抵抗の低減
を実現するためにその構造に改良を加えたものである．
以上より薄膜トランジスタに於いて，低消費電力及び高
電界効果移動度を実現することができた．As described above, the thin film transistor of the present invention has its structure improved in order to reduce the leakage current in the OFF state and to reduce the contact resistance of the source and drain electrodes. Is.
From the above, it was possible to realize low power consumption and high field effect mobility in thin film transistors.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例の断面図である．FIG. 1 is a sectional view of an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１絶縁基板２ゲート電極３補助電極４ゲート絶縁膜５半導体薄膜６ソース電極７ドレイン電極８ゲート絶縁膜９ゲート電極 1 Insulating Substrate 2 Gate Electrode 3 Auxiliary Electrode 4 Gate Insulating Film 5 Semiconductor Thin Film 6 Source Electrode 7 Drain Electrode 8 Gate Insulating Film 9 Gate Electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者中村潤二名古屋市緑区相川２丁目43番地ベラビスタ相川203号 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Junji Nakamura 2-43 Aikawa, Midori-ku, Nagoya Bella Vista No. 203 Aikawa

Claims

【特許請求の範囲】[Claims]

【請求項１】ソース及び，ドレイン電極の他に，主体
半導体薄膜層の上下に相対するように一つずつの電極及
び絶縁膜からなるゲート電極を持つ薄膜トランジスタに
ついて，トランジスタが一方のゲート電極でオフ状態及
び，オン状態となった時に，もう一つのゲート電極に電
圧を印加して使うようになっていることを特徴とした薄
膜トランジスタの構造．1. A thin film transistor having, in addition to a source and drain electrode, a gate electrode composed of an insulating film and an electrode so as to face each other above and below the main semiconductor thin film layer, the transistor is off at one gate electrode. Structure of thin film transistor characterized by applying a voltage to another gate electrode when it is turned on and turned on.

【請求項２】請求項１の薄膜トランジスタにおいて，
ソース電極及び，ドレイン電極が形成されている面と反
対側の主体半導体薄膜面上に，絶縁膜及び電極からなる
補助電極を設け，この電極に電圧を印加するようになっ
ていることを特徴とする薄膜トランジスタの構造．2. The thin film transistor according to claim 1, wherein
An auxiliary electrode composed of an insulating film and an electrode is provided on the surface of the main semiconductor thin film opposite to the surface on which the source electrode and the drain electrode are formed, and a voltage is applied to this electrode. Of thin film transistor.

【請求項３】請求項２において，請求項１で述べたも
う一つのゲート電極を付加したことを特徴とする薄膜ト
ランジスタの構造．3. The structure of a thin film transistor according to claim 2, wherein the other gate electrode described in claim 1 is added.