JPH0784285A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH0784285A JPH0784285A JP22916693A JP22916693A JPH0784285A JP H0784285 A JPH0784285 A JP H0784285A JP 22916693 A JP22916693 A JP 22916693A JP 22916693 A JP22916693 A JP 22916693A JP H0784285 A JPH0784285 A JP H0784285A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- liquid crystal
- layer
- tft
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 52
- 239000000463 material Substances 0.000 claims abstract description 34
- 239000010408 film Substances 0.000 claims description 61
- 239000000758 substrate Substances 0.000 claims description 38
- 239000003990 capacitor Substances 0.000 claims description 24
- 239000010409 thin film Substances 0.000 claims description 18
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 18
- 238000000034 method Methods 0.000 abstract description 17
- 238000000059 patterning Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000000593 degrading effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 101
- 239000011521 glass Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 229910001362 Ta alloys Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高精細で表示品位の良
好な薄型・軽量の液晶表示装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin and lightweight liquid crystal display device having high definition and good display quality.
【０００２】[0002]
【従来の技術】プラズマディスプレイパネルや、ＥＬ
（エレクトロルミネッセンス）ディスプレイパネル、Ｌ
ＥＤ（発光ダイオード）ディスプレイパネル、蛍光表示
パネル、そして液晶表示装置などの、いわゆるフラット
パネルディスプレイデバイスは、表示部の薄型化、軽量
化が可能であることから、例えばＯＡ機器やコンピュー
タ等の情報表示デバイスとして利用されている。2. Description of the Related Art Plasma display panels and EL
(Electroluminescence) display panel, L
Since so-called flat panel display devices such as an ED (light emitting diode) display panel, a fluorescent display panel, and a liquid crystal display device can have a thinner and lighter display portion, for example, information display for OA equipment, computers, etc. It is used as a device.
【０００３】このようなフラットパネルディスプレイの
中でも、特に非晶質（アモルファス）シリコンを用いた
薄膜トランジスタ（ａ−ＳｉＴＦＴ）を画素電極に接続
して印加電圧を制御（スイッチング）するためのスイッ
チング素子として、基板上にマトリックス状に配置した
アクティブマトリックス型の液晶表示装置は、単純マト
リックス型の液晶表示装置よりもさらに表示品位が高く
低消費電力である特長を有することから、上記のフラッ
トパネルディスプレイデバイスの中でも特に注目され、
その開発が盛んに行なわれている。Among such flat panel displays, a thin film transistor (a-SiTFT) using amorphous silicon is connected to a pixel electrode to control (switch) an applied voltage as a switching element. Among the above flat panel display devices, the active matrix type liquid crystal display device arranged in a matrix on the substrate has the characteristics of higher display quality and lower power consumption than the simple matrix type liquid crystal display device. Of particular attention,
Its development is being actively conducted.
【０００４】従来の液晶表示装置の補助容量およびスイ
ッチング用ＴＦＴの部分の構造を図５に示す。従来の液
晶表示装置は、ガラスのような材料からなる透明基板５
０１上に絶縁コート５０２が形成され、その上にスイッ
チング用ＴＦＴ５０４のゲート電極５０５および補助容
量５０６の第１の電極５０７が形成され、それらを覆う
ように絶縁材料層５０８が形成されてスイッチング用Ｔ
ＦＴ５０４の領域においてはゲート絶縁層５０９、補助
容量５０６の領域においては誘電体層５１０がそれぞれ
形成されている。そしてその上に画素領域および補助容
量５０６の領域を覆うように透明導電膜からなる画素電
極５１１が形成されている。またスイッチング用ＴＦＴ
５０４にはドレイン領域５１２、チャネル領域５１３、
ソース領域５１４を有する活性層５１５が形成され、こ
の活性層５１５を覆うようにコンタクト層５１６が形成
されて、このコンタクト層５１６をそれぞれ介してドレ
イン領域５１２にはドレイン電極５１７が接続されソー
ス領域５１４にはソース電極５１８が接続されるように
それぞれ形成されている。そしてチャネル領域５１３上
を覆うようにチャネル保護層５１９が形成されている。
また補助容量５０６には誘電体層５１０上に画素電極５
１１の一部が重なるように形成されてその部分が第２の
電極５２０として形成されている。FIG. 5 shows a structure of a storage capacitor and a switching TFT of a conventional liquid crystal display device. The conventional liquid crystal display device has a transparent substrate 5 made of a material such as glass.
01, an insulating coat 502 is formed, a gate electrode 505 of a switching TFT 504 and a first electrode 507 of an auxiliary capacitance 506 are formed on the insulating coat 502, and an insulating material layer 508 is formed so as to cover them, and a switching T
A gate insulating layer 509 is formed in the region of the FT 504, and a dielectric layer 510 is formed in the region of the auxiliary capacitance 506. Then, a pixel electrode 511 made of a transparent conductive film is formed thereon so as to cover the pixel region and the region of the auxiliary capacitance 506. In addition, switching TFT
504 includes a drain region 512, a channel region 513,
An active layer 515 having a source region 514 is formed, a contact layer 516 is formed so as to cover the active layer 515, a drain electrode 517 is connected to the drain region 512 through the contact layer 516, and a source region 514 is formed. Are formed so as to be connected to the source electrode 518. Then, a channel protective layer 519 is formed so as to cover the channel region 513.
In addition, the auxiliary capacitor 506 includes a pixel electrode 5 on the dielectric layer 510.
Part of 11 is formed so as to overlap, and that part is formed as the second electrode 520.
【０００５】近年、このような液晶表示装置のさらなる
高精細化、高輝度及び高コントラスト化を実現する試み
がなされている。その手法の主なものの一つとして、画
素の開口率を向上することが有効であることが知られて
いる。In recent years, attempts have been made to realize higher definition, higher brightness and higher contrast of such a liquid crystal display device. As one of the main methods, it is known that it is effective to improve the aperture ratio of pixels.
【０００６】そのような画素の開口率を向上するために
は、ブラックマトリックスと呼ばれる遮光膜（図示省
略）から露出させる画素電極５１１の有効表示面積をさ
らに大きくすることが必要である。In order to improve the aperture ratio of such a pixel, it is necessary to further increase the effective display area of the pixel electrode 511 exposed from a light shielding film (not shown) called a black matrix.
【０００７】あるいは、アクティブマトリックス型液晶
表示装置において駆動電圧保持に必要な補助容量５０６
の容量値を変えることなく、むしろさらに向上させなが
ら、補助容量５０６の占有面積を小型化することが必要
である。Alternatively, in the active matrix type liquid crystal display device, a storage capacitor 506 required for holding a driving voltage is provided.
It is necessary to reduce the area occupied by the auxiliary capacitance 506 without changing the capacitance value of 1), and further improving it.
【０００８】このうち、遮光膜の開口率の向上について
は、すでにかなりの技術的な開発成果が得られており、
これ以上の開口率の向上は、遮光膜の形成時の位置合わ
せ精度の限界の関係上（製造上の誤差等の点から）すで
に限界に達しており、従って補助容量の占有面積をさら
に小型化することが有効であると考えられる。Of these, considerable technical development results have already been obtained for improving the aperture ratio of the light-shielding film.
Further improvement of the aperture ratio has already reached the limit due to the limit of the alignment accuracy when forming the light-shielding film (from the viewpoint of manufacturing error etc.), and therefore the occupation area of the auxiliary capacitor can be further reduced. It is considered effective to do so.
【０００９】しかしながら、そのような補助容量５０６
の占有面積を単純に小型化すると、補助容量５０６の容
量値が低下してしまうという問題がある。補助容量５０
６の容量値は補助容量５０６の電極面積すなわち前記の
占有面積に比例するからである。However, such a storage capacitor 506
There is a problem that the capacitance value of the auxiliary capacitance 506 is reduced if the area occupied by is simply reduced. Auxiliary capacity 50
This is because the capacitance value of 6 is proportional to the electrode area of the auxiliary capacitance 506, that is, the occupied area.
【００１０】そこで、前記の補助容量５０６の電極面積
を小型化しつつその容量値を保つ、あるいは向上するた
めには、補助容量を形成する誘電体、すなわち前記の第
１の電極５０７と第２の電極５２０との間に挟持される
誘電体層５１０の厚さを薄くすることが有効であると考
えられる。容量値は上述のように電極面積に比例する一
方、電極間距離つまり誘電体層５１０の厚さに反比例す
るからである。Therefore, in order to reduce the electrode area of the auxiliary capacitance 506 and maintain or improve the capacitance value thereof, a dielectric material forming the auxiliary capacitance, that is, the first electrode 507 and the second electrode is formed. It is considered effective to reduce the thickness of the dielectric layer 510 sandwiched between the electrodes 520. This is because the capacitance value is proportional to the electrode area as described above, but is inversely proportional to the inter-electrode distance, that is, the thickness of the dielectric layer 510.
【００１１】しかしながら、従来の非晶質シリコンを用
いた薄膜トランジスタ（ＴＦＴ；Thin Film Transisto
r、以下ＴＦＴと略称）スイッチング素子を有するアク
ティブマトリックス型の液晶表示装置においては、ａ−
ＳｉＴＦＴの形成材料を用いて、そのパターン形成プロ
セス中でパターンを変更することによって同一材料で同
一層に補助容量５０６の誘電体層５１０および第１の電
極５０７、第２の電極５２０を形成していた。従って補
助容量５０６に用いる誘電体層５１０としてはスイッチ
ング用ＴＦＴ５０４のゲート絶縁層５０９が用いられて
いたが、この場合に用いられるゲート絶縁層５０９の厚
さは一般に 200乃至 400ｎｍ程度であるため、補助容量
５０６の誘電体層５１０もこの厚さとなり、容量値の確
保が困難であるという問題があった。However, a conventional thin film transistor (TFT) using amorphous silicon is used.
r, hereinafter abbreviated as TFT) In an active matrix type liquid crystal display device having a switching element, a-
The dielectric layer 510 of the auxiliary capacitor 506, the first electrode 507, and the second electrode 520 are formed in the same layer with the same material by changing the pattern in the pattern forming process using the forming material of the SiTFT. It was Therefore, the gate insulating layer 509 of the switching TFT 504 was used as the dielectric layer 510 used for the auxiliary capacitance 506, but the thickness of the gate insulating layer 509 used in this case is generally about 200 to 400 nm, The dielectric layer 510 of the capacitor 506 also has this thickness, and there is a problem that it is difficult to secure the capacitance value.
【００１２】そこで補助容量５０６に用いる誘電体層５
１０としては、スイッチング用ａ−ＳｉＴＦＴ５０４の
ゲート絶縁膜５０９をそのまま用いるのではなく、その
ゲート絶縁膜５０９を形成する絶縁材料層５０８を二層
構造とし、その下側の一層だけを補助容量５０６に好適
な薄い誘電体層として用いるという手法が提案されてい
る。Therefore, the dielectric layer 5 used for the auxiliary capacitance 506.
As for 10, the gate insulating film 509 of the switching a-Si TFT 504 is not used as it is, but the insulating material layer 508 forming the gate insulating film 509 has a two-layer structure, and only one layer below the insulating material layer 508 is used as the auxiliary capacitor 506. Techniques have been proposed for use as a suitable thin dielectric layer.
【００１３】しかしながら、このような方法では、ゲー
ト絶縁膜５０９（絶縁材料層５０８）の形成工程が煩雑
になるという問題がある。However, such a method has a problem that the step of forming the gate insulating film 509 (insulating material layer 508) becomes complicated.
【００１４】また、補助容量５０６の誘電体層５１０だ
けをスイッチング用ＴＦＴ５０４の形成材料とは別に形
成することも、前記の場合と同様に工程の煩雑化やパタ
ーニングの誤差（パターンずれ）等に起因して、ＴＦＴ
の信頼性を低下させるという問題がある。Also, forming only the dielectric layer 510 of the auxiliary capacitor 506 separately from the material for forming the switching TFT 504 is caused by the complicated process and patterning error (pattern shift) as in the above case. And TFT
There is a problem of reducing the reliability of.
【００１５】[0015]
【発明が解決しようとする課題】このように、従来の液
晶表示装置においては、開口率を向上するために補助容
量を小型化しようとすると、補助容量の容量値が低下し
てしまうという問題があった。As described above, in the conventional liquid crystal display device, there is a problem that the capacitance value of the auxiliary capacitance is reduced when the auxiliary capacitance is downsized in order to improve the aperture ratio. there were.
【００１６】そしてそれを解消するために補助容量の誘
電体の厚さを薄くしようとすると、その製造工程が煩雑
化し、さらには製作されたＴＦＴの動作特性や信頼性の
低下が生じるという問題があった。If the thickness of the dielectric of the auxiliary capacitor is reduced in order to solve the problem, the manufacturing process is complicated, and further, the operating characteristics and reliability of the manufactured TFT are deteriorated. there were.
【００１７】本発明はこのような問題を解決するために
成されたもので、その目的は、製造工程を煩雑化するこ
となく、また得られたＴＦＴの信頼性を低下することな
く、小型化された容量値の高い補助容量を有して、画素
の開口率が良好で表示品位の高い液晶表示装置を提供す
ることにある。The present invention has been made to solve such a problem, and its purpose is to reduce the size of the TFT without complicating the manufacturing process and reducing the reliability of the obtained TFT. An object of the present invention is to provide a liquid crystal display device having a high auxiliary capacitance having a high capacitance value, a high pixel aperture ratio, and high display quality.
【００１８】[0018]
【課題を解決するための手段】上記課題を解決するため
に、本発明の液晶表示装置は、基板上に配列形成され表
示領域を形成する画素電極と、前記画素電極に対する液
晶駆動電圧の印加を制御する第１の薄膜トランジスタで
あって前記基板上にゲート電極とゲート絶縁膜と活性層
とがこの順で形成されかつ前記活性層の両側にソース領
域、ドレイン領域が形成された第１の薄膜トランジスタ
と、前記表示領域の周辺部に配置され、前記薄膜トラン
ジスタを制御する液晶駆動回路であって、前記基板上に
形成された活性層と該活性層を覆うように形成されたゲ
ート絶縁膜と前記ゲート絶縁膜上に形成されたゲート電
極とがこの順に形成されかつ前記活性層の両側にソース
領域、ドレイン領域が形成された第２の薄膜トランジス
タを用いて形成された液晶駆動回路と、前記基板上に第
１の電極と誘電体と第２の電極とがこの順で形成され、
前記第２の電極が前記画素電極に接続され、前記第１の
電極が前記第２の薄膜トランジスタの前記ソース領域或
いは前記ドレイン領域と同一材料で同一層に形成され、
前記誘電体が前記第２の薄膜トランジスタの前記ゲート
絶縁層と同一材料で同一層に形成され、前記第２の電極
が前記画素電極に電気的に接続された補助容量とを具備
することを特徴としている。In order to solve the above problems, a liquid crystal display device according to the present invention comprises a pixel electrode arrayed and formed on a substrate to form a display region, and a liquid crystal drive voltage applied to the pixel electrode. A first thin film transistor for controlling, wherein a gate electrode, a gate insulating film, and an active layer are formed in this order on the substrate, and a source region and a drain region are formed on both sides of the active layer. A liquid crystal driving circuit arranged in the peripheral portion of the display region for controlling the thin film transistor, the active layer formed on the substrate, the gate insulating film formed to cover the active layer, and the gate insulating film. A gate electrode formed on the film and a second thin film transistor in which a source region and a drain region are formed on both sides of the active layer are formed in this order. A liquid crystal driver circuit, a first electrode dielectric and the second electrode are formed in this order on the substrate,
The second electrode is connected to the pixel electrode, the first electrode is formed of the same material as the source region or the drain region of the second thin film transistor in the same layer,
The dielectric may be formed of the same material as the gate insulating layer of the second thin film transistor in the same layer, and the second electrode may include an auxiliary capacitance electrically connected to the pixel electrode. There is.
【００１９】なお、画素スイッチング用として用いられ
る上記の第１の薄膜トランジスタのゲート絶縁膜の膜厚
としては、逆スタガ型のＴＦＴとして一般的に用いられ
るような半導体材料を用いる場合、 200〜 400ｎｍに設
定することが望ましい。また、液晶駆動回路のＴＦＴの
ゲート絶縁膜の膜厚としては、コプラナ型のＴＦＴとし
て一般的に用いられるような半導体材料を用いる場合、
30〜 100ｎｍに設定することが望ましい。このような膜
厚に設定することにより、スイッチング用ＴＦＴ、液晶
駆動回路用ＴＦＴ、補助容量のそれぞれの電気的特性を
良好なものとすることができ、かつ簡易な製造方法によ
ってそれらを実現することができるからである。The thickness of the gate insulating film of the first thin film transistor used for pixel switching is 200 to 400 nm when a semiconductor material generally used for an inverted stagger type TFT is used. It is desirable to set. Further, as the film thickness of the gate insulating film of the TFT of the liquid crystal drive circuit, when using a semiconductor material generally used as a coplanar TFT,
It is desirable to set it to 30 to 100 nm. By setting such a film thickness, it is possible to improve the electrical characteristics of the switching TFT, the liquid crystal drive circuit TFT, and the auxiliary capacitance, and to realize them by a simple manufacturing method. Because you can
【００２０】また、上記のスイッチング用の第１の薄膜
トランジスタとしては非晶質シリコンを用いたＴＦＴで
形成し、上記の液晶駆動回路用の第２の薄膜トランジス
タとしては多結晶シリコンを用いたＴＦＴで形成するこ
とが、それぞれに要求される動作特性に対して好適なも
のとなるので望ましい。ただし、それぞれの形成材料と
してはこれのみには限定しないことは言うまでもない。Further, the first thin film transistor for switching is formed by a TFT using amorphous silicon, and the second thin film transistor for the liquid crystal drive circuit is formed by a TFT using polycrystalline silicon. Is preferable because it is suitable for the operating characteristics required for each. However, it goes without saying that the respective forming materials are not limited to these.
【００２１】[0021]
【作用】本発明によれば、同一基板上に液晶駆動回路を
薄膜トランジスタとして作り込んでいるので、液晶ディ
スプレイパネルのさらなる小型化、高集積化を実現する
ことができる。According to the present invention, since the liquid crystal drive circuit is formed as a thin film transistor on the same substrate, further miniaturization and high integration of the liquid crystal display panel can be realized.
【００２２】そして、画素電極に接続される補助容量の
誘電体として、膜厚の薄い液晶駆動回路側に設けられた
コプラナ型のＴＦＴのゲート絶縁膜を用いているので、
従来の製造手法におけるパターニングのみを変更するだ
けで本発明に係る補助容量を形成することができ、製造
工程の煩雑化を引き起こすことがなく厚さの薄い誘電体
を得ることができる。従って補助容量の容量値を維持あ
るいは向上させつつその占有面積を小型化することがで
き、画素電極の開口率を向上することができる。しかも
それを簡易な製造方法によって簡易な構造で実現でき
る。Since the gate insulating film of the thin coplanar TFT provided on the liquid crystal driving circuit side is used as the dielectric of the auxiliary capacitor connected to the pixel electrode,
The auxiliary capacitor according to the present invention can be formed only by changing the patterning in the conventional manufacturing method, and a thin dielectric material can be obtained without complicating the manufacturing process. Therefore, the occupied area can be reduced while maintaining or improving the capacitance value of the auxiliary capacitor, and the aperture ratio of the pixel electrode can be improved. Moreover, it can be realized with a simple structure by a simple manufacturing method.
【００２３】また、補助容量の基板寄りの層の第１の電
極をコプラナ型の液晶駆動回路のＴＦＴのソース領域及
びドレイン領域と同じ層の同じ材料から形成しているの
で、プロセス整合性が良好で、製造不良の発生を解消し
信頼性の高い液晶表示装置を高歩留まりで製造すること
が可能となる。Further, since the first electrode of the layer of the storage capacitor near the substrate is formed of the same material as the source layer and the drain region of the TFT of the coplanar type liquid crystal drive circuit, the process matching is good. Thus, it becomes possible to eliminate the occurrence of manufacturing defects and manufacture a highly reliable liquid crystal display device with a high yield.
【００２４】[0024]
【実施例】以下、本発明に係る液晶表示装置の一実施例
を、図面に基づいて詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the liquid crystal display device according to the present invention will be described below in detail with reference to the drawings.
【００２５】図１は本発明に係る液晶表示装置の構造を
示す図である。この液晶表示装置は、ＴＦＴ基板１とこ
れに間隙を有して対向配置される対向電極が形成された
対向基板（図示省略）と、これら基板間の間隙に周囲を
封止して封入される液晶組成物（図示省略）とからその
主要部が構成されている。なお以降の説明では、説明の
簡潔化のためにＴＦＴ基板１を中心として説明する。FIG. 1 is a diagram showing the structure of a liquid crystal display device according to the present invention. In this liquid crystal display device, a TFT substrate 1 and a counter substrate (not shown) formed with a counter electrode facing the TFT substrate 1 with a gap therebetween, and the gap between these substrates are sealed and sealed. Its main part is composed of a liquid crystal composition (not shown). In the following description, the TFT substrate 1 will be mainly described for simplification of the description.
【００２６】この液晶表示装置のＴＦＴ基板１には、絶
縁コート２が表面に形成されたガラス基板３上に画素電
極４と、補助容量５と、ａ−Ｓｉを活性層に用いたスイ
ッチング用の第１のＴＦＴとしての逆スタガ型ＴＦＴ６
と、液晶駆動回路を形成する多結晶シリコンを活性層に
用いた、液晶駆動回路を形成する第２のＴＦＴとしての
コプラナ型ＴＦＴ７とを有する。前記のガラス基板３の
他にも、基板の材料としては例えば合成石英基板などを
用いることもできる。In the TFT substrate 1 of this liquid crystal display device, a pixel electrode 4, an auxiliary capacitance 5, and a-Si are used as an active layer for switching on a glass substrate 3 having an insulating coat 2 formed on the surface thereof. Inverted stagger type TFT 6 as the first TFT
And a coplanar TFT 7 as a second TFT for forming a liquid crystal drive circuit, which uses polycrystalline silicon for forming a liquid crystal drive circuit as an active layer. In addition to the glass substrate 3 described above, a synthetic quartz substrate or the like can be used as the material of the substrate.
【００２７】そしてＴＦＴ基板１上にマトリックス状に
配列された画素電極４同士の間隙に、図示は省略したが
走査線及び信号線が形成されて、逆スタガ型ＴＦＴ６に
それぞれ接続されている。そして上記の画素電極４を除
いた各部を覆うように、保護膜（図１においては図示省
略）が形成されており、さらにこのようなＴＦＴ基板１
のほぼ全面を覆うように配向膜（図示省略）が形成され
ている。Although not shown, scanning lines and signal lines are formed in the gaps between the pixel electrodes 4 arranged in a matrix on the TFT substrate 1 and are connected to the inverted staggered TFTs 6, respectively. A protective film (not shown in FIG. 1) is formed so as to cover each part except the above-mentioned pixel electrode 4, and further such a TFT substrate 1 is formed.
An alignment film (not shown) is formed so as to cover almost the entire surface of.
【００２８】逆スタガ型ＴＦＴ６は、ガラス基板３の絶
縁コート２上に設けられた導電性の良好な金属膜のよう
な材料からなるゲート電極８と、そのゲート電極８を覆
うように設けられたゲート絶縁層９と、その上に設けら
れた活性層１０と、その活性層１０のチャネル領域１１
を覆うように形成されたチャネル保護層１２と、このチ
ャネル保護層１２を隔てて活性層１０のドレイン領域１
３上及びソース領域１４上にそれぞれ形成されたコンタ
クト層１５と、コンタクト層１５を介してそれぞれドレ
イン領域１３、ソース領域１４上に接続するように形成
されたドレイン電極１６、ソース電極１７とから主要部
が構成される逆スタガ構造のＴＦＴである。この逆スタ
ガ型ＴＦＴ６のゲート絶縁層９の膜厚は 200〜 400ｎｍ
で、その形成材料としては例えばシリコン酸化膜を用い
ている。またゲート電極８の形成材料としては，例えば
クロームのような金属材料を用いることができる。また
活性層１０の形成材料としてはａ−Ｓｉを用いている。The inverted stagger type TFT 6 is provided so as to cover the gate electrode 8 made of a material such as a metal film having good conductivity provided on the insulating coat 2 of the glass substrate 3, and the gate electrode 8. Gate insulating layer 9, active layer 10 provided thereon, and channel region 11 of the active layer 10.
And the drain region 1 of the active layer 10 with the channel protection layer 12 separated from each other.
3, a contact layer 15 formed on the source region 14, and a drain electrode 16 and a source electrode 17 formed so as to be connected to the drain region 13 and the source region 14 via the contact layer 15, respectively. It is a TFT having an inverted stagger structure in which a part is constituted. The film thickness of the gate insulating layer 9 of the inverted stagger type TFT 6 is 200 to 400 nm.
For example, a silicon oxide film is used as the forming material. As a material for forming the gate electrode 8, for example, a metal material such as chrome can be used. Further, a-Si is used as a material for forming the active layer 10.
【００２９】このような構造の逆スタガ型ＴＦＴ６は、
走査線（図示省略）からゲート電極８に入力される走査
パルスに基づいて、ドレイン電極１６側に入力された信
号電圧のソース電極１７側の画素電極４への導通を制御
する。The inverted staggered TFT 6 having such a structure is
The conduction of the signal voltage input to the drain electrode 16 side to the pixel electrode 4 on the source electrode 17 side is controlled based on the scanning pulse input from the scanning line (not shown) to the gate electrode 8.
【００３０】一方、液晶駆動回路のコプラナ型ＴＦＴ７
は、ガラス基板３の絶縁コート２上に形成された多結晶
シリコン（ｐ−Ｓｉ）から形成された活性層１８と、そ
の活性層１８のチャネル領域１９をゲート絶縁膜２０を
介して覆うように形成されたゲート電極２１と、活性層
１８のドレイン領域２２、ソース領域２３に接続するよ
うにそれぞれ形成されたドレイン電極２４、ソース電極
２５と、ドレイン電極２４及びソース電極２５と、層間
絶縁膜２６とを有するコプラナ型のＴＦＴ構造に形成さ
れている。ここで、コプラナ型ＴＦＴ７の動作特性を良
好なものとするために、上記のゲート絶縁膜２０の膜厚
は30〜 100ｎｍ程度に設定することが望ましい。30ｎｍ
より薄い場合にはゲート耐圧が極端に低下してＴＦＴの
正常な動作が得られなくなる。一方、 100ｎｍよりも厚
い場合にはイオン注入のプロファイルを所望の形状にす
ることが実際上困難となってソース領域やドレイン領域
の形成ができなくなる。On the other hand, the coplanar TFT 7 of the liquid crystal drive circuit
Covers the active layer 18 made of polycrystalline silicon (p-Si) formed on the insulating coat 2 of the glass substrate 3 and the channel region 19 of the active layer 18 via the gate insulating film 20. The formed gate electrode 21, the drain electrode 24, the source electrode 25, the drain electrode 24 and the source electrode 25, which are formed so as to be connected to the drain region 22 and the source region 23 of the active layer 18, respectively, and the interlayer insulating film 26. And a coplanar type TFT structure having Here, in order to improve the operating characteristics of the coplanar type TFT 7, it is desirable to set the film thickness of the gate insulating film 20 to about 30 to 100 nm. 30 nm
When the thickness is thinner, the gate breakdown voltage is extremely lowered and normal operation of the TFT cannot be obtained. On the other hand, when the thickness is thicker than 100 nm, it is practically difficult to form the ion implantation profile into a desired shape, and the source region and the drain region cannot be formed.
【００３１】そして補助容量５は、ガラス基板３の絶縁
コート２上にコプラナ型ＴＦＴ７の活性層１８のドレイ
ン領域２２、ソース領域２３と同一材料で同一層に形成
された第１の電極２７と、コプラナ型ＴＦＴ７のゲート
絶縁膜２０と同一材料で同一層に形成された誘電体層２
８と、この誘電体層２８を覆うように形成された透明導
電膜からなる第２の電極２９とでその主要部が形成され
ている。その第２の電極２９は画素電極４を延長させて
一体に形成したもので、逆スタガ型ＴＦＴ６のソース電
極１７に接続されるとともに、画素電極４と一体形成さ
れて電気的に接続されている。The auxiliary capacitor 5 has a first electrode 27 formed on the insulating coat 2 of the glass substrate 3 and made of the same material as the drain region 22 and the source region 23 of the active layer 18 of the coplanar TFT 7 in the same layer. Dielectric layer 2 made of the same material as the gate insulating film 20 of the coplanar TFT 7 and formed in the same layer
8 and a second electrode 29 made of a transparent conductive film formed so as to cover the dielectric layer 28, a main part thereof is formed. The second electrode 29 is formed by extending the pixel electrode 4 and is integrally formed. The second electrode 29 is connected to the source electrode 17 of the inverted stagger type TFT 6 and is integrally formed and electrically connected to the pixel electrode 4. .
【００３２】補助容量５の第１の電極２７は、コプラナ
型ＴＦＴ７のドレイン領域２２やソース領域２３と同様
に、高抵抗なｐ−Ｓｉ材料にドーパント（不純物）を添
加することで低抵抗化させて、良好な導電性を得てい
る。Like the drain region 22 and the source region 23 of the coplanar type TFT 7, the first electrode 27 of the auxiliary capacitance 5 is made to have a low resistance by adding a dopant (impurity) to a high resistance p-Si material. Therefore, good conductivity is obtained.
【００３３】また補助容量５の誘電体層２８は、コプラ
ナ型ＴＦＴ７のゲート絶縁膜２０と同材料で同一層に形
成されており、その膜厚は前述のゲート絶縁膜２０と同
様に30〜 100ｎｍ程度の膜厚であるので、補助容量５の
誘電体層として好適な膜厚に形成されている。また第２
の電極２９は画素電極４と一体形成されているので、パ
ターニングの変更だけで形成することができ、極めて簡
易かつプロセス整合性が良好である。The dielectric layer 28 of the auxiliary capacitor 5 is formed of the same material as the gate insulating film 20 of the coplanar type TFT 7 in the same layer, and its film thickness is 30 to 100 nm like the above-mentioned gate insulating film 20. Since the film thickness is about the same, the film thickness is formed to be suitable for the dielectric layer of the auxiliary capacitor 5. The second
Since the electrode 29 is integrally formed with the pixel electrode 4, it can be formed only by changing the patterning, which is extremely simple and has good process consistency.
【００３４】上記の活性層１８のドレイン領域２２、ソ
ース領域２３、第１の電極２７に添加する不純物として
は、Ｐ（燐）やＢ（ボロン）などをドーパントとして用
いることができる。As the impurities added to the drain region 22, the source region 23 and the first electrode 27 of the active layer 18, P (phosphorus), B (boron) or the like can be used as a dopant.
【００３５】また、コプラナ型ＴＦＴ７の活性層１８に
レーザ光線を照射してアニール処理を施してある。この
ようにして活性層１８の結晶粒径の成長を促進して、Ｔ
ＦＴとしての良好な動作特性を得ている。Further, the active layer 18 of the coplanar type TFT 7 is irradiated with a laser beam to be annealed. In this way, the growth of the crystal grain size of the active layer 18 is promoted, and T
Good operating characteristics as FT are obtained.
【００３６】また、逆スタガ型ＴＦＴ６のゲート絶縁層
９とコプラナ型ＴＦＴの層間絶縁膜２６とは同一材料か
ら同一層で形成されたもので、ＳｉＯx またはＳｉＮx
等から形成されている。その形成方法としては、ＥＣＲ
−ＣＶＤ法、プラズマＣＶＤ法、光ＣＶＤ法等によって
形成することができる。このように逆スタガ型ＴＦＴ６
のゲート絶縁層９とコプラナ型ＴＦＴ７の層間絶縁膜２
６とを一度に形成することができるので、本発明に係る
液晶表示装置はそのパターニングのパターンのみを変更
することで製作することができるのでプロセス整合性が
良好で、工程の煩雑化を引き起こすことなく実現するこ
とができる。Further, the gate insulating layer 9 of the inverted stagger type TFT 6 and the interlayer insulating film 26 of the coplanar type TFT are formed of the same material in the same layer, and are made of SiO x or SiN x.
Etc. The formation method is ECR
It can be formed by a CVD method, a plasma CVD method, an optical CVD method, or the like. In this way, the inverted staggered TFT 6
Gate insulating layer 9 and interlayer insulating film 2 of coplanar TFT 7
Since 6 and 6 can be formed at a time, the liquid crystal display device according to the present invention can be manufactured by changing only the patterning pattern, so that the process consistency is good and the process is complicated. Can be realized without.
【００３７】また、逆スタガ型ＴＦＴ６のゲート電極８
とコプラナ型ＴＦＴ７のゲート電極２１とは同一材料で
同一層に形成されている。その材料としては、例えばＭ
ｏ−Ｔａ合金、Ａｌ、Ｔａ、Ａｌ−Ｔａ合金、Ｗあるい
はそれらのシリサイド等を好適に用いることができる。
あるいはその表面に陽極酸化等を用いて酸化処理を施し
てもよい。このようにゲート電極８とゲート電極２１と
を同一材料から同一層に形成しているので製造プロセス
の煩雑化を引き起こすことがなく、簡易に製造すること
ができる。In addition, the gate electrode 8 of the inverted stagger type TFT 6
And the gate electrode 21 of the coplanar TFT 7 are formed of the same material in the same layer. As the material, for example, M
O-Ta alloy, Al, Ta, Al-Ta alloy, W, or silicide thereof can be preferably used.
Alternatively, the surface may be subjected to an oxidation treatment by using anodic oxidation or the like. Since the gate electrode 8 and the gate electrode 21 are formed of the same material in the same layer in this manner, the manufacturing process is not complicated and the manufacturing can be performed easily.
【００３８】また従来の液晶表示装置の補助容量のよう
に逆スタガ型ＴＦＴのゲート絶縁層の形成材料を用いて
誘電体層を形成する場合では、補助容量の誘電体層の膜
厚を十分に薄くすることができず、補助容量としての容
量値を大きくすることが実際上不可能であった。このよ
うな従来の場合、逆に補助容量の誘電体層として好適な
膜厚を得ようとすると、ゲート絶縁層としての膜厚とし
ては今度は薄くなりすぎて、ＴＦＴとして十分良好な動
作特性が得られなかった。しかしこのような従来の問題
は、本発明によれば補助容量の誘電体層を十分薄くする
ことができるので解消することができる。When the dielectric layer is formed by using the material for forming the gate insulating layer of the inverted stagger type TFT like the auxiliary capacitance of the conventional liquid crystal display device, the thickness of the dielectric layer of the auxiliary capacitance should be sufficient. It could not be made thin, and it was practically impossible to increase the capacity value as the auxiliary capacity. In the case of such a conventional case, conversely, if an attempt is made to obtain a suitable film thickness as the dielectric layer of the auxiliary capacitance, the film thickness as the gate insulating layer becomes too thin this time, and a sufficiently good operating characteristic as a TFT is obtained. I couldn't get it. However, according to the present invention, such a conventional problem can be solved because the dielectric layer of the auxiliary capacitance can be made sufficiently thin.
【００３９】次に、本発明に係る液晶表示装置のＴＦＴ
基板の製造方法を述べる。図２、図３、図４は、その製
造工程を示す図である。Next, the TFT of the liquid crystal display device according to the present invention
A method of manufacturing the substrate will be described. 2, 3, and 4 are views showing the manufacturing process.
【００４０】表面に絶縁コート２が形成されたガラス基
板３の表面上に、Ｓｉ膜をプラズマＣＶＤ法、あるいは
ＬＰＣＶＤ法等によって形成し、このＳｉ膜をパターニ
ングしてこの 1つのＳｉ膜から同じ層にコプラナ型ＴＦ
Ｔ７の活性層１８及び補助容量５の第１の電極２７をパ
ターン形成する（図２（ａ））。An Si film is formed on the surface of the glass substrate 3 having the insulating coating 2 formed thereon by plasma CVD method or LPCVD method, and the Si film is patterned to form the same layer from the same Si film. Coplanar TF
The active layer 18 of T7 and the first electrode 27 of the auxiliary capacitance 5 are patterned (FIG. 2A).
【００４１】次いて、それらを含む基板上ほぼ全体を覆
うように、コプラナ型ＴＦＴ７のゲート絶縁膜２０及び
補助容量５の誘電体層２８となる絶縁膜（例えばＳｉＯ
x 膜）２０１を、ＥＣＲ−ＣＶＤ法、プラズマＣＶＤ法
等により形成する。そして前述したコプラナ型ＴＦＴ７
の活性層１８及び補助容量５の第１の電極２７にエキシ
マレーザ等の高エネルギービームを照射してアニール処
理を施し結晶化（単結晶もしくは多結晶）する（図２
（ｂ））。Next, an insulating film (eg, SiO 2) which will be the gate insulating film 20 of the coplanar TFT 7 and the dielectric layer 28 of the auxiliary capacitor 5 is formed so as to cover almost the entire substrate including them.
The x film) 201 is formed by the ECR-CVD method, the plasma CVD method, or the like. And the above-mentioned coplanar TFT 7
The active layer 18 and the first electrode 27 of the auxiliary capacitor 5 are irradiated with a high energy beam such as an excimer laser and annealed to be crystallized (single crystal or polycrystal) (FIG. 2).
(B)).
【００４２】続いて、逆スタガ型ＴＦＴ６のゲート電極
８及びコプラナ型ＴＦＴ７のゲート電極２１を、例えば
Ｍｏ−Ｔａ合金をスパッタ法等により形成した膜をケミ
カルドライエッチング等によりパターニングして形成す
る。続いてコプラナ型ＴＦＴ７のゲート電極２１をセル
フアラインマスクとして用いて活性層１８にＰ（燐）、
Ｂ（ボロン）等の不純物を例えばイオン打ち込み法等に
より投入してその部分を低抵抗化し、ドレイン領域２２
及びソース領域２３を形成する。またゲート電極２１で
被覆された部分にはチャネル領域１９が形成される。一
方、このとき補助容量５の第１の電極２７に対しても前
記のＰあるいはＢ等の不純物を投入して低抵抗化し、補
助容量５の電極として好適な導電性を得る（図２
（ｃ））。このとき、ソース領域、ドレイン領域の不純
物活性化及び補助容量電極の好適な導電性を得るために
は、エキシマレーザ等の高エネルギビームを照射するこ
とが望ましい。Subsequently, the gate electrode 8 of the inverted stagger type TFT 6 and the gate electrode 21 of the coplanar type TFT 7 are formed by patterning a film formed of, for example, a Mo-Ta alloy by a sputtering method by chemical dry etching or the like. Then, using the gate electrode 21 of the coplanar TFT 7 as a self-alignment mask, P (phosphorus) is formed in the active layer 18,
Impurities such as B (boron) are introduced by, for example, an ion implantation method to reduce the resistance of the portion, and the drain region 22
And the source region 23 are formed. A channel region 19 is formed in the portion covered with the gate electrode 21. On the other hand, at this time, the resistance of the first electrode 27 of the auxiliary capacitance 5 is reduced by introducing the impurities such as P or B to obtain a conductivity suitable for the electrode of the auxiliary capacitance 5 (FIG. 2).
(C)). At this time, it is desirable to irradiate a high energy beam such as an excimer laser in order to activate the impurities in the source region and the drain region and obtain suitable conductivity of the auxiliary capacitance electrode.
【００４３】続いてＩＴＯのような透明導電膜を成膜し
これを画素領域及び補助容量を覆うようなパターンにパ
ターニングして、画素電極４を形成する（図２
（ｄ））。Subsequently, a transparent conductive film such as ITO is formed and patterned into a pattern covering the pixel region and the auxiliary capacitance to form the pixel electrode 4 (FIG. 2).
(D)).
【００４４】次に、コプラナ型ＴＦＴ７の層間絶縁膜２
６及び逆スタガ型ＴＦＴ６のゲート絶縁層９を形成する
ための絶縁材料層３００を、例えばＳｉＯx 膜あるいは
ＳｉＮx 膜あるいはそれらの積層膜等の材料を用いて同
じ層に、前述のゲート電極２１、ゲート電極８、画素電
極４等を含む基板上ほぼ全面を覆うように形成する。さ
らにこのＳｉＯx などからなる絶縁材料層３００の上
に、高抵抗半導体層を例えばプラズマＣＶＤ法、光ＣＶ
Ｄ法等により成膜する。そしてチャネル保護層１２を形
成し、さらにその上を含む前記の高抵抗半導体層上を覆
うように低抵抗半導体層をプラズマＣＶＤ法、光ＣＶＤ
法等により形成し、これらの高抵抗半導体層及び低抵抗
半導体層を島状にパターニングして、活性層１０及びそ
の上にコンタクト層１５を形成する。Next, the interlayer insulating film 2 of the coplanar type TFT 7 is formed.
6 and the gate insulating layer 300 for forming the gate insulating layer 9 of the inverted staggered TFT 6 are formed on the same layer by using a material such as a SiO x film or a SiN x film or a laminated film thereof, and the above-mentioned gate electrode 21. The gate electrode 8, the pixel electrode 4 and the like are formed so as to cover almost the entire surface of the substrate. Further, a high-resistance semiconductor layer is formed on the insulating material layer 300 made of SiO x or the like by, for example, plasma CVD method or optical CV method.
A film is formed by the D method or the like. Then, the channel protection layer 12 is formed, and the low resistance semiconductor layer is covered with the plasma CVD method and the photo CVD so as to cover the high resistance semiconductor layer including the channel protection layer 12.
Then, the high resistance semiconductor layer and the low resistance semiconductor layer are patterned into an island shape to form the active layer 10 and the contact layer 15 thereon.
【００４５】そしてコンタクトホール３０１、３０２を
絶縁材料層３００に穿設してドレイン領域２２、ソース
領域２３を露出させるとともに、画素電極４を表面に露
出させるように画素電極４上の絶縁材料層３００を除去
しておく（図２（ｆ））。Then, contact holes 301 and 302 are formed in the insulating material layer 300 to expose the drain region 22 and the source region 23, and the insulating material layer 300 on the pixel electrode 4 is exposed so as to expose the pixel electrode 4 on the surface. Are removed (FIG. 2 (f)).
【００４６】続いて、コプラナ型ＴＦＴ７のドレイン領
域２２、ソース電極２３にそれぞれ接続するようにドレ
イン電極２４、ソース電極２５を形成する。またこのと
き同じ成膜及びパターニング工程で、逆スタガ型ＴＦＴ
６のドレイン領域１３、ソース領域１４にコンタクト層
１５を介してそれぞれ接続するようにドレイン電極１
６、ソース電極１７を形成する。またこのときチャネル
保護層１２上のコンタクト層１５をエッチング除去して
分離しておく。これらのドレイン電極２４、ソース電極
２５、ドレイン電極１６、ソース電極１７は、同じ金属
膜（例えばＭｏ、Ａｌ等）をスパッタ法等により成膜し
これをパターニングして形成することができる（図２
（ｇ））。Subsequently, a drain electrode 24 and a source electrode 25 are formed so as to be connected to the drain region 22 and the source electrode 23 of the coplanar TFT 7, respectively. Further, at this time, in the same film forming and patterning process, the inverted stagger type TFT
The drain electrode 1 so as to be connected to the drain region 13 and the source region 14 of FIG.
6, the source electrode 17 is formed. At this time, the contact layer 15 on the channel protection layer 12 is removed by etching and separated. The drain electrode 24, the source electrode 25, the drain electrode 16, and the source electrode 17 can be formed by forming the same metal film (for example, Mo, Al, etc.) by a sputtering method or the like and patterning the same (FIG. 2).
(G)).
【００４７】そして、コプラナ型ＴＦＴ７及び逆スタガ
型ＴＦＴ６ほぼ全体を覆うように、例えばＳｉＮx 膜、
ＳｉＯx 膜、あるいはそれらの積層膜等をプラズマＣＶ
Ｄ法、光ＣＶＤ法等により成膜し、これをパターニング
して、保護膜４００を形成する（図２（ｈ））。Then, for example, a SiN x film, so as to cover almost the entire coplanar type TFT 7 and the inverted stagger type TFT 6,
A plasma CV is applied to the SiO x film or a laminated film of these
A film is formed by the D method, the photo CVD method, or the like, and this is patterned to form the protective film 400 (FIG. 2H).
【００４８】このようにして本発明に係る液晶表示装置
のＴＦＴ基板１を製作することができる。そしてこのよ
うなＴＦＴ基板１と対向電極が形成された対向基板（図
示省略）とを間隙を有して対向配置し、基板周囲を封止
しその基板間隙に液晶組成物（図示省略）を注入・挟持
させて、本発明に係る液晶表示装置が完成する。In this way, the TFT substrate 1 of the liquid crystal display device according to the present invention can be manufactured. Then, such a TFT substrate 1 and a counter substrate (not shown) on which a counter electrode is formed are arranged to face each other with a gap, the periphery of the substrate is sealed, and a liquid crystal composition (not shown) is injected into the substrate gap. -The liquid crystal display device according to the present invention is completed by sandwiching.
【００４９】このようにして製造された本発明に係る液
晶表示装置は、コプラナ型ＴＦＴ７及び逆スタガ型ＴＦ
Ｔ６の動作特性が良好で、かつ補助容量５はその誘電体
層２８を薄く形成することができるので、電気容量値を
高くすることができ、かつ補助容量５の占有面積をさら
に小型化することができる。The liquid crystal display device according to the present invention manufactured as described above includes the coplanar type TFT 7 and the inverted stagger type TF.
Since the operating characteristic of T6 is good and the dielectric layer 28 of the auxiliary capacitance 5 can be formed thin, the electric capacitance value can be increased and the area occupied by the auxiliary capacitance 5 can be further reduced. You can
【００５０】また本発明によれば補助容量５の第１の電
極２７として前記のコプラナ型ＴＦＴ７の活性層１８と
同じ材料を同じ層に用いて形成しているので、簡易かつ
高品質に形成することができる。Further, according to the present invention, since the same material as the active layer 18 of the coplanar TFT 7 is used as the first electrode 27 of the auxiliary capacitor 5 in the same layer, it is formed easily and with high quality. be able to.
【００５１】なお以上の実施例では、スイッチング用の
逆スタガ型ＴＦＴ６としてａ−ＳｉＴＦＴを用いるとと
もに、液晶駆動回路用のコプラナ型ＴＦＴ７として多結
晶シリコンＴＦＴを用いる場合について述べたが、本発
明はこれのみには限定せず、その他の半導体材料を用い
たＴＦＴにも本発明は適用可能である。In the above embodiments, the case where the a-Si TFT is used as the reverse stagger type TFT 6 for switching and the polycrystalline silicon TFT is used as the coplanar type TFT 7 for the liquid crystal drive circuit has been described. The present invention is not limited to this, and the present invention can be applied to TFTs using other semiconductor materials.
【００５２】コプラナ型ＴＦＴ７のゲート絶縁膜２０と
補助容量５の誘電体層２８とを同じ材料で同じ層に形成
するが、このときＴＦＴ７のゲート絶縁膜２０としての
特性と補助容量５の誘電体層２８としての膜厚の薄さと
の両立が可能な材料を好適に用いることができる。The gate insulating film 20 of the coplanar type TFT 7 and the dielectric layer 28 of the auxiliary capacitor 5 are formed of the same material in the same layer. At this time, the characteristics as the gate insulating film 20 of the TFT 7 and the dielectric of the auxiliary capacitor 5 are formed. A material that is compatible with the thin film thickness of the layer 28 can be preferably used.
【００５３】また、スイッチング用のＴＦＴ（上記実施
例では逆スタガ型ＴＦＴ６）は、自己整合型（セルフア
ライン）で形成したＴＦＴを用いることもできる。ま
た、上記のコプラナ型ＴＦＴ７としては、ゲート電極２
１を各ＴＦＴごとに 2つ有するいわゆるダブルゲート構
造のＴＦＴや、ドレイン領域に低濃度で不純物を添加し
たＬＤＤ構造のＴＦＴを用いることなどもできる。As the switching TFT (inverted stagger type TFT 6 in the above embodiment), a self-aligned TFT can be used. In addition, as the coplanar TFT 7 described above, the gate electrode 2
It is also possible to use a so-called double-gate structure TFT having two 1s for each TFT, or an LDD structure TFT in which an impurity is added to the drain region at a low concentration.
【００５４】その他、本発明の要旨を逸脱しない範囲で
本発明に係る液晶表示装置の各構成部位の形成材料の変
更が種々可能であることは言うまでもない。In addition, it goes without saying that various changes can be made to the forming material of each component of the liquid crystal display device according to the present invention without departing from the scope of the present invention.
【００５５】[0055]
【発明の効果】以上、詳細な説明で明示したように、製
造工程を煩雑化あるいは得られたＴＦＴの信頼性を低下
することなく、小型化された容量値の高い補助容量を有
して、画素の開口率が良好で表示品位の高い液晶表示装
置を提供することにある。As is clear from the detailed description above, the auxiliary capacitor having a high capacity and a reduced size can be provided without complicating the manufacturing process or lowering the reliability of the obtained TFT. An object of the present invention is to provide a liquid crystal display device having a good pixel aperture ratio and high display quality.
【図１】本発明に係る液晶表示装置を示す図である。FIG. 1 is a diagram showing a liquid crystal display device according to the present invention.
【図２】本発明に係る液晶表示装置の製造工程を示す図
である。FIG. 2 is a diagram showing a manufacturing process of a liquid crystal display device according to the present invention.
【図３】本発明に係る液晶表示装置の製造工程を示す図
である。FIG. 3 is a diagram showing a manufacturing process of a liquid crystal display device according to the present invention.
【図４】本発明に係る液晶表示装置の製造工程を示す図
である。FIG. 4 is a diagram showing a manufacturing process of a liquid crystal display device according to the present invention.
【図５】従来の液晶表示装置を示す図である。FIG. 5 is a diagram showing a conventional liquid crystal display device.
１………ＴＦＴ基板 ２………絶縁コート ３………ガラス基板 ４………画素電極 ５………補助容量 ６………逆スタガ型ＴＦＴ ７………コプラナ型ＴＦＴ ８………ゲート電極 ９………ゲート絶縁層 １０………活性層 １１………チャネル領域 ２７………第１の電極 ２８………誘電体層 ２９………第１の電極 1 ………… TFT substrate 2 ………… Insulation coat 3 ………… Glass substrate 4 ………… Pixel electrode 5 ………… Auxiliary capacitance 6 ………… Inverse stagger type TFT 7 ………… Coplanar type TFT 8 ………… Gate Electrode 9 ... Gate insulating layer 10 ... Active layer 11 ... Channel region 27 ... First electrode 28 ... Dielectric layer 29 ... First electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 川久 慶人 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝研究開発センター内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Keito Kawakyu 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center
Claims (1)
る画素電極と、 前記画素電極に対する液晶駆動電圧の印加を制御する第
１の薄膜トランジスタであって前記基板上にゲート電極
とゲート絶縁膜と活性層とがこの順で形成されかつ前記
活性層の両側にソース領域、ドレイン領域が形成された
第１の薄膜トランジスタと、 前記表示領域の周辺部に配置され、前記第１の薄膜トラ
ンジスタを制御する液晶駆動回路であって、前記基板上
に形成された活性層と該活性層を覆うように形成された
ゲート絶縁膜と前記ゲート絶縁膜上に形成されたゲート
電極とがこの順に形成されかつ前記活性層の両側にソー
ス領域、ドレイン領域が形成された第２の薄膜トランジ
スタを用いて形成された液晶駆動回路と、 前記基板上に第１の電極と誘電体と第２の電極とがこの
順で形成され、前記第２の電極が前記画素電極に接続さ
れ、前記第１の電極が前記第２の薄膜トランジスタの前
記ソース領域或いは前記ドレイン領域と同一材料で同一
層に形成され、前記誘電体が前記第２の薄膜トランジス
タの前記ゲート絶縁層と同一材料で同一層に形成され、
前記第２の電極が前記画素電極に電気的に接続された補
助容量とを具備することを特徴とする液晶表示装置。1. A pixel electrode arrayed and formed on a substrate to form a display region, and a first thin film transistor for controlling application of a liquid crystal driving voltage to the pixel electrode, the gate electrode and a gate insulating film on the substrate. A first thin film transistor in which an active layer is formed in this order and a source region and a drain region are formed on both sides of the active layer, and a liquid crystal which is disposed in the peripheral portion of the display region and controls the first thin film transistor. In the drive circuit, an active layer formed on the substrate, a gate insulating film formed so as to cover the active layer, and a gate electrode formed on the gate insulating film are formed in this order and the active layer is formed. A liquid crystal drive circuit formed by using a second thin film transistor in which a source region and a drain region are formed on both sides of the layer; and a first electrode, a dielectric and a second electrode on the substrate. An electrode is formed in this order, the second electrode is connected to the pixel electrode, and the first electrode is formed of the same material as the source region or the drain region of the second thin film transistor in the same layer. , The dielectric is formed of the same material and in the same layer as the gate insulating layer of the second thin film transistor,
A liquid crystal display device, wherein the second electrode comprises an auxiliary capacitor electrically connected to the pixel electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22916693A JPH0784285A (en) | 1993-09-14 | 1993-09-14 | Liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22916693A JPH0784285A (en) | 1993-09-14 | 1993-09-14 | Liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0784285A true JPH0784285A (en) | 1995-03-31 |
Family
ID=16887827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22916693A Withdrawn JPH0784285A (en) | 1993-09-14 | 1993-09-14 | Liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0784285A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6933996B2 (en) | 1996-10-22 | 2005-08-23 | Seiko Epson Corporation | Liquid crystal panel substrate, liquid crystal panel, and electronic device and projection display device using the same |
| KR100692672B1 (en) * | 1998-08-24 | 2008-11-19 | 비오이 하이디스 테크놀로지 주식회사 | Manufacturing method of liquid crystal display device |
| US7704859B2 (en) | 2006-05-23 | 2010-04-27 | Epson Imaging Devices Corporation | Electro-optical apparatus, electronic apparatus, and method of manufacturing electro-optical apparatus |
| US7872728B1 (en) | 1996-10-22 | 2011-01-18 | Seiko Epson Corporation | Liquid crystal panel substrate, liquid crystal panel, and electronic device and projection display device using the same |
| JP2011242745A (en) * | 2010-05-17 | 2011-12-01 | Samsung Mobile Display Co Ltd | Organic light-emitting display device and manufacturing method thereof |
-
1993
- 1993-09-14 JP JP22916693A patent/JPH0784285A/en not_active Withdrawn
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6933996B2 (en) | 1996-10-22 | 2005-08-23 | Seiko Epson Corporation | Liquid crystal panel substrate, liquid crystal panel, and electronic device and projection display device using the same |
| US7158205B2 (en) | 1996-10-22 | 2007-01-02 | Seiko Epson Corporation | Liquid crystal panel substrate, liquid crystal panel, and electronic device and projection display device using the same |
| US7184105B2 (en) | 1996-10-22 | 2007-02-27 | Seiko Epson Corporation | Liquid crystal panel substrate, liquid crystal panel, and electronic device and projection display device having the same |
| US7324171B2 (en) | 1996-10-22 | 2008-01-29 | Seiko Epson Corporation | Liquid crystal panel substrate, liquid crystal panel, and electronic device and projection display device using the same |
| US7532292B2 (en) | 1996-10-22 | 2009-05-12 | Seiko Epson Corporation | Liquid crystal panel substrate, liquid crystal panel, and electronic device and projection display device using the same |
| US7868961B2 (en) | 1996-10-22 | 2011-01-11 | Seiko Epson Corporation | Liquid crystal panel substrate, liquid crystal panel, and electronic device and projection display device using the same |
| US7872728B1 (en) | 1996-10-22 | 2011-01-18 | Seiko Epson Corporation | Liquid crystal panel substrate, liquid crystal panel, and electronic device and projection display device using the same |
| KR100692672B1 (en) * | 1998-08-24 | 2008-11-19 | 비오이 하이디스 테크놀로지 주식회사 | Manufacturing method of liquid crystal display device |
| US7704859B2 (en) | 2006-05-23 | 2010-04-27 | Epson Imaging Devices Corporation | Electro-optical apparatus, electronic apparatus, and method of manufacturing electro-optical apparatus |
| JP2011242745A (en) * | 2010-05-17 | 2011-12-01 | Samsung Mobile Display Co Ltd | Organic light-emitting display device and manufacturing method thereof |
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| Date | Code | Title | Description |
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| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20001128 |