JPH0590579A - Power field-effect transistor - Google Patents
Power field-effect transistorInfo
- Publication number
- JPH0590579A JPH0590579A JP3250084A JP25008491A JPH0590579A JP H0590579 A JPH0590579 A JP H0590579A JP 3250084 A JP3250084 A JP 3250084A JP 25008491 A JP25008491 A JP 25008491A JP H0590579 A JPH0590579 A JP H0590579A
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- electrode
- semiconductor substrate
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 230000008878 coupling Effects 0.000 claims abstract description 11
- 238000010168 coupling process Methods 0.000 claims abstract description 11
- 238000005859 coupling reaction Methods 0.000 claims abstract description 11
- 238000010030 laminating Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、大電流容量のパワー電
界効果トランジスタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power field effect transistor having a large current capacity.
【０００２】[0002]
【従来の技術】半導体基板に不純物選択拡散で形成され
たパワー電界効果トランジスタ（パワーＭＯＳＦＥＴ）
の従来構造例を図２に示し、これを説明する。図２はＮ
チャネル型電界効果トランジスタで、Ｐ+型サブストレ
ート（20ａ）上にＮ-型エピタキシャル成長層（20ｂ）
を積層形成した半導体基板（20）を有する。半導体基板
（20）の表面側にＰ+型サブストレート（20ａ）につな
がる深さで形成された低濃度Ｐ- 型不純物の選択拡散で
バックゲート領域（21）と、高濃度Ｎ+ 型不純物の選択
拡散でドレイン領域（22）が形成され、バックゲート領
域（22）の表面中央部に高濃度Ｎ+ 型不純物の選択拡散
でソース領域（23）が形成される。半導体基板（20）の
表面側に酸化膜（24）、ゲート電極（25）、ドレイン電
極（26）、ソース電極（27）が形成される。ゲート電極
（25）は、ドレイン領域（26）とソース領域（27）の間
のチャネル部（28）上の酸化膜（24）に埋設された形で
形成される。ドレイン電極（26）はドレイン領域（22）
と導通させてその上に、ソース電極（27）はソース領域
（23）と導通させてその上に形成される。ドレイン電極
（26）とソース電極（23）は、アルミニウム等の金属を
半導体基板（20）に蒸着するなどして、所定の配線パタ
ーンで一括して形成される。2. Description of the Related Art A power field effect transistor (power MOSFET) formed on a semiconductor substrate by selective diffusion of impurities.
An example of the conventional structure is shown in FIG. 2 and will be described. 2 is N
Channel type field effect transistor, N − type epitaxial growth layer (20b) on P + type substrate (20a)
A semiconductor substrate (20) having a laminated structure. On the surface side of the semiconductor substrate (20) is formed at a depth which leads to P + -type substrate (20a) a low concentration P - a back gate region in the selective diffusion of impurity (21), the high-concentration N + -type impurity The drain region (22) is formed by selective diffusion, and the source region (23) is formed by selective diffusion of the high-concentration N + -type impurity in the center of the surface of the back gate region (22). An oxide film (24), a gate electrode (25), a drain electrode (26) and a source electrode (27) are formed on the surface side of the semiconductor substrate (20). The gate electrode (25) is formed so as to be buried in the oxide film (24) on the channel portion (28) between the drain region (26) and the source region (27). The drain electrode (26) is the drain region (22)
The source electrode (27) is electrically connected to the source region (23) and is formed thereon. The drain electrode (26) and the source electrode (23) are collectively formed in a predetermined wiring pattern by evaporating a metal such as aluminum on the semiconductor substrate (20).
【０００３】ソース電極（27）を低電位にして、ゲート
電極（25）に所定の電流制御電圧を印加する。すると、
チャネル部（28）がＮ+ チャネルとなり、ドレイン電極
（26）からドレイン領域（22）、チャネル部（28）、ソ
ース領域（23）、ソース電極（27）の経路で電流が流れ
る。The source electrode (27) is set to a low potential and a predetermined current control voltage is applied to the gate electrode (25). Then,
The channel portion (28) becomes an N + channel, and current flows from the drain electrode (26) to the drain region (22), the channel portion (28), the source region (23), and the source electrode (27).
【０００４】[0004]
【発明が解決しようとする課題】パワー電界効果トラン
ジスタは、図２に示す電界効果トランジスタの複数を同
一の半導体基板に形成し、それぞれのドレイン電極同
士、ソース電極同士を接続して、大電流が流れるように
構成される。このパワー電界効果トランジスタの電流容
量は、半導体基板上にパターン配線されるドレイン電極
とソース電極の面積の大小で大きく左右される。ところ
で、パワー電界効果トランジスタは、他の半導体素子同
様に小形化が要望され、小面積の半導体基板に高密度で
電界効果トランジスタを形成して、それぞれをパターン
配線しているが、小面積の半導体基板上に形成されるド
レイン電極とソース電極の両者のパターン面積は既に限
界に達している。すなわち、半導体基板上でドレイン電
極とソース電極の幅を広げて面積増大化を図ると、両電
極間の耐圧が低化したり、両電極間が短絡する可能性が
大となる。また、ドレイン電極とソース電極間の耐圧低
下、短絡の心配無く、両電極を半導体基板上に面積大に
してパターン配線しようとすると、どうしても半導体基
板が大形化する。その結果、パワー電界効果トランジス
タは、小形では大電流容量化が難しく、大電流容量化す
るには大形化せざるを得ないのが現状である。In the power field effect transistor, a plurality of field effect transistors shown in FIG. 2 are formed on the same semiconductor substrate, and the drain electrodes and source electrodes of the field effect transistors are connected to each other so that a large current can flow. Configured to flow. The current capacity of the power field effect transistor is greatly influenced by the size of the area of the drain electrode and the source electrode which are patterned on the semiconductor substrate. By the way, the power field effect transistor is required to be miniaturized like other semiconductor elements, and field effect transistors are formed at a high density on a semiconductor substrate having a small area, and pattern wiring is performed for each of them. The pattern areas of both the drain electrode and the source electrode formed on the substrate have already reached their limits. That is, if the widths of the drain electrode and the source electrode are widened on the semiconductor substrate to increase the area, the breakdown voltage between the two electrodes may be reduced, or the two electrodes may be short-circuited. Further, if pattern wiring is performed with a large area of both electrodes on the semiconductor substrate without fear of reduction in breakdown voltage between the drain electrode and the source electrode or short circuit, the size of the semiconductor substrate is inevitably increased. As a result, it is difficult to increase the current capacity of the power field effect transistor in a small size, and it is the current situation that the power field effect transistor must be increased in size to increase the current capacity.
【０００５】本発明は、かかる小形化と大電流容量化の
相反する問題点に鑑みてなされたもので、小形化かつ大
電流容量化が容易なパワー電界効果トランジスタを提供
することを目的とする。The present invention has been made in view of the contradictory problems of miniaturization and large current capacity, and it is an object of the present invention to provide a power field effect transistor which can be easily downsized and large in current capacity. ..
【０００６】[0006]
【課題を解決するための手段】本発明は、裏面側にソー
ス電極が形成された半導体基板の表面側にドレイン領域
とバックゲート領域を、さらにバックゲート領域にソー
ス領域を形成し、このソース領域と前記ソース電極間に
両者を結合するソース結合領域を前記バックゲート領域
を貫通させて形成し、かつ、半導体基板の表面全域に、
ゲート電極を埋設した酸化膜を形成し、この酸化膜上に
前記ドレイン領域に導通させてドレイン電極を形成した
構造により、上記目的を達成するものである。According to the present invention, a drain region and a back gate region are formed on the front surface side of a semiconductor substrate having a source electrode formed on the back surface side, and a source region is further formed on the back gate region. And a source coupling region that couples the two between the source electrode and the source electrode are formed so as to penetrate the back gate region, and the entire surface of the semiconductor substrate,
The above object is achieved by a structure in which an oxide film with a buried gate electrode is formed, and the drain electrode is formed on the oxide film so as to be electrically connected to the drain region.
【０００７】[0007]
【作用】半導体基板裏面のソース電極を低電位にして、
半導体基板表面の酸化膜に埋設されたゲート電極に電流
制御電圧を印加すると、半導体基板表面のドレイン電極
から半導体基板表面側のドレイン領域、チャネル、ソー
ス領域、ソース結合領域の経路で、半導体基板表裏面を
貫通する電流が流れる。半導体基板の表面の酸化膜上に
はドレイン電極とゲート電極が、半導体基板裏面にはソ
ース電極だけが形成され、従って、ドレイン電極とソー
ス電極は共に、小面積半導体基板により大面積パターン
で形成でき、上記目的が達成される。[Function] The source electrode on the back surface of the semiconductor substrate is set to a low potential,
When a current control voltage is applied to the gate electrode embedded in the oxide film on the semiconductor substrate surface, the semiconductor substrate surface is routed from the drain electrode on the semiconductor substrate surface to the drain region, channel, source region, and source coupling region on the semiconductor substrate surface side. An electric current flows through the back surface. A drain electrode and a gate electrode are formed on the oxide film on the surface of the semiconductor substrate, and only a source electrode is formed on the back surface of the semiconductor substrate.Therefore, both the drain electrode and the source electrode can be formed in a large area pattern by a small area semiconductor substrate. The above object is achieved.
【０００８】[0008]
【実施例】図１に本発明の一実施例を示し、これを説明
する。図１の実施例はＮチャネル型パワー電界効果トラ
ンジスタを示し、これの半導体基板（１）は、Ｐ型のソ
ースコンタクト領域（２）となるＰ+ 型サブストレート
（１ａ）上にＮ- 型エピタキシャル成長層（１ｂ）を積
層形成している。半導体基板（１）の表面側に高濃度Ｐ
+ 型不純物の選択拡散でバックゲート領域（４）と、高
濃度Ｎ+ 型不純物の選択拡散でドレイン領域（３）が形
成され、バックゲート領域（４）の表面中央部に高濃度
Ｎ+ 型不純物の選択拡散でソース領域（５）が形成され
る。さらにソースコンタクト領域（２）からバックゲー
ト領域（４）とソース領域（５）の中央部を貫通する縦
方向にＰ++型不純物の拡散でソース結合領域（６）が形
成される。このソース結合領域（６）は、ソース領域
（５）とソースコンタクト領域（２）をＰＮ短絡電極
（10）で結合して、ここにドレイン−ソース電流が流れ
る。ソース結合領域（６）は、例えばソースコンタクト
領域（２）の表層部に埋め込んだＰ型不純物を上方に拡
散させたＰ型領域（６ａ）と、半導体基板（１）の表面
から下方〔基板内部〕に向ってＰ型不純物を拡散させた
Ｐ型領域（６ｂ）とを結合させた領域である。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention is shown in FIG. 1 and will be described. The embodiment of FIG. 1 shows an N-channel type power field effect transistor, the semiconductor substrate (1) of which is N − type epitaxial growth on a P + type substrate (1a) which becomes a P type source contact region (2). The layers (1b) are laminated. High concentration P on the surface side of the semiconductor substrate (1)
+ In selective diffusion of impurity back gate region (4), the drain region (3) is formed by selective diffusion of a high concentration N + -type impurity, a high concentration N + -type surface central portion of the back gate region (4) A source region (5) is formed by selective diffusion of impurities. Further, a source coupling region (6) is formed by diffusion of P + + -type impurities in the vertical direction penetrating from the source contact region (2) through the central portions of the back gate region (4) and the source region (5). In the source coupling region (6), the source region (5) and the source contact region (2) are coupled by the PN short circuit electrode (10), and a drain-source current flows there. The source coupling region (6) is, for example, a P-type region (6a) in which a P-type impurity buried in the surface layer portion of the source contact region (2) is diffused upward, and a region below the surface of the semiconductor substrate (1) [inside the substrate]. ] And a P-type region (6b) in which P-type impurities are diffused.
【０００９】以上の半導体基板（１）に対して、その表
面側に酸化膜（７）、ＰＮ短絡電極（10）、ゲート電極
（８）、ドレイン電極（９）が形成され、裏面側にソー
ス電極（11）が形成される。ＰＮ短絡電極（10）は、半
導体基板（１）表面に形成されたＮ型ソース領域（５）
とＰ型ソース結合領域（６）を短絡して、ドレイン−ソ
ース間の電流の電流経路を作る。ゲート電極（８）は、
ドレイン領域（３）とソース領域（５）の間のチャネル
部（12）上の酸化膜（７）に埋設される。ドレイン電極
（９）は、半導体基板（１）表面に露出させたドレイン
領域（３）上と、その周辺の酸化膜（７）上にアルミニ
ウム蒸着法などで形成される。ソース電極（11）は、半
導体基板（１）の裏面全域にアルミニウム蒸着法などで
形成される。An oxide film (7), a PN short-circuit electrode (10), a gate electrode (8) and a drain electrode (9) are formed on the front surface side of the semiconductor substrate (1) described above, and a source is formed on the back surface side. An electrode (11) is formed. The PN short-circuit electrode (10) is an N-type source region (5) formed on the surface of the semiconductor substrate (1).
And the P-type source coupling region (6) are short-circuited to form a current path of current between the drain and the source. The gate electrode (8) is
It is buried in the oxide film (7) on the channel part (12) between the drain region (3) and the source region (5). The drain electrode (9) is formed on the drain region (3) exposed on the surface of the semiconductor substrate (1) and the oxide film (7) around the drain region by an aluminum deposition method or the like. The source electrode (11) is formed on the entire back surface of the semiconductor substrate (1) by an aluminum vapor deposition method or the like.
【００１０】ソース電極（11）を低電位にし、ゲート電
極（８）に電流制御電圧を印加すると、ドレイン電極
（９）から電流がドレイン領域（３）、チャネル部（1
2）を通り、ソース領域（５）からＰＮ短絡電極（1
0）、ソース結合領域（６）を流れ、ソースコンタクト
領域（２）からソース電極（11）へと流れる。このよう
な電流経路を備えた電界効果トランジスタの複数を半導
体基板（１）に形成して、それぞれのドレイン電極
（９）をパターン配線することで、大電流容量のパワー
電界効果トランジスタが得られる。図１実施例の場合、
半導体基板（１）の表面の酸化膜（７）上にはドレイン
電極（９）だけが形成されているので、半導体基板
（１）が小面積のものでも、その上にドレイン電極
（９）は十分に大面積パターンで、しかも自由なパター
ンで形成できる。このことはソース電極（11）にしても
同じである。従って、半導体基板（１）を大形化するこ
となく、ドレイン電極（９）とソース電極（11）のパタ
ーン面積を増大化して、大電流容量化することが可能と
なる。When the source electrode (11) is set to a low potential and a current control voltage is applied to the gate electrode (8), a current flows from the drain electrode (9) to the drain region (3) and the channel portion (1).
2) through the source region (5) to the PN shorting electrode (1
0), flowing through the source coupling region (6) and flowing from the source contact region (2) to the source electrode (11). By forming a plurality of field effect transistors having such a current path on the semiconductor substrate (1) and patterning the drain electrodes (9) thereof, a power field effect transistor having a large current capacity can be obtained. In the case of the embodiment shown in FIG.
Since only the drain electrode (9) is formed on the oxide film (7) on the surface of the semiconductor substrate (1), even if the semiconductor substrate (1) has a small area, the drain electrode (9) is formed thereon. It can be formed in a sufficiently large area pattern and in a free pattern. This also applies to the source electrode (11). Therefore, it is possible to increase the pattern area of the drain electrode (9) and the source electrode (11) and increase the current capacity without increasing the size of the semiconductor substrate (1).
【００１１】なお、本発明は上記実施例に限らず、例え
ばＰチャネル型パワー電界効果トランジスタにおいても
上記同様に適用できる。The present invention is not limited to the above embodiment, but can be applied to a P channel type power field effect transistor in the same manner as above.
【００１２】[0012]
【発明の効果】以上説明したように、本発明によれば、
半導体基板の表面の酸化膜上にはドレイン電極だけを形
成し、半導体基板裏面にはソース電極だけを形成すれば
よく、その結果、半導体基板を大形化することなく、ド
レイン電極とソース電極を大面積パターンで形成して、
大電流容量化を図ることが容易に可能となり、パワー電
界効果トランジスタの小形化が図れる効果がある。ま
た、半導体基板にドレイン電極やソース電極は、他の異
なる電極で邪魔されることなく自由な配線パターンで形
成されるので、そのパターン設計、製造が容易となる効
果もある。As described above, according to the present invention,
It is sufficient to form only the drain electrode on the oxide film on the front surface of the semiconductor substrate and only the source electrode on the back surface of the semiconductor substrate. As a result, the drain electrode and the source electrode can be formed without increasing the size of the semiconductor substrate. Form with a large area pattern,
The large current capacity can be easily achieved, and the power field effect transistor can be downsized. In addition, since the drain electrode and the source electrode are formed on the semiconductor substrate in a free wiring pattern without being disturbed by other different electrodes, there is also an effect that the pattern design and manufacture can be facilitated.
【図１】本発明の一実施例を示す部分断面図FIG. 1 is a partial sectional view showing an embodiment of the present invention.
【図２】従来のパワー電界効果トランジスタの部分断面
図FIG. 2 is a partial sectional view of a conventional power field effect transistor.
１ 半導体基板 ２ ソースコンタクト領域 ３ ドレイン領域 ４ バックゲート領域 ５ ソース領域 ６ ソース結合領域 ７ 酸化膜 ８ ゲート電極 ９ ドレイン電極 1 semiconductor substrate 2 source contact region 3 drain region 4 back gate region 5 source region 6 source coupling region 7 oxide film 8 gate electrode 9 drain electrode
Claims (1)
電界効果トランジスタにおいて、裏面側にソース電極が
形成された半導体基板の表面側にドレイン領域とバック
ゲート領域を、さらにバックゲート領域にソース領域を
形成し、このソース領域と裏面側の前記ソース電極間に
両者を結合するソース結合領域を前記バックゲート領域
を貫通させて形成したこと、および、前記半導体基板の
表面全域に、ゲート電極を埋設した酸化膜を形成し、こ
の酸化膜上に前記ドレイン領域に導通させてドレイン電
極を形成し、基板表面からドレイン電極、裏面からソー
ス電極を導出したことを特徴とするパワー電界効果トラ
ンジスタ。1. In a power field effect transistor in which a drain electrode is taken out from the front surface, a drain region and a back gate region are formed on the front surface side of a semiconductor substrate having a source electrode formed on the back surface side, and a source region is further formed on the back gate region. A source coupling region that couples the source region and the source electrode on the back side is formed through the back gate region, and an oxide film having a gate electrode embedded in the entire front surface of the semiconductor substrate. And a drain electrode is formed on the oxide film so as to be electrically connected to the drain region, and the drain electrode is led out from the front surface of the substrate and the source electrode is led out from the back surface thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3250084A JPH0590579A (en) | 1991-09-30 | 1991-09-30 | Power field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3250084A JPH0590579A (en) | 1991-09-30 | 1991-09-30 | Power field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0590579A true JPH0590579A (en) | 1993-04-09 |
Family
ID=17202573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3250084A Pending JPH0590579A (en) | 1991-09-30 | 1991-09-30 | Power field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0590579A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5760440A (en) * | 1995-02-21 | 1998-06-02 | Fuji Electric Co., Ltd. | Back-source MOSFET |
| EP0862223A2 (en) * | 1997-02-28 | 1998-09-02 | Nec Corporation | Power high-frequency field effect transistor |
| JP2005236252A (en) * | 2003-10-22 | 2005-09-02 | Marvell World Trade Ltd | Efficient transistor structure |
| US7960833B2 (en) | 2003-10-22 | 2011-06-14 | Marvell World Trade Ltd. | Integrated circuits and interconnect structure for integrated circuits |
| EP2339637A1 (en) * | 2009-12-28 | 2011-06-29 | STMicroelectronics S.r.l. | Power MOSFET device and method of making the same |
-
1991
- 1991-09-30 JP JP3250084A patent/JPH0590579A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5760440A (en) * | 1995-02-21 | 1998-06-02 | Fuji Electric Co., Ltd. | Back-source MOSFET |
| EP0862223A2 (en) * | 1997-02-28 | 1998-09-02 | Nec Corporation | Power high-frequency field effect transistor |
| EP0862223A3 (en) * | 1997-02-28 | 1999-03-24 | Nec Corporation | Power high-frequency field effect transistor |
| JP2005236252A (en) * | 2003-10-22 | 2005-09-02 | Marvell World Trade Ltd | Efficient transistor structure |
| JP4667788B2 (en) * | 2003-10-22 | 2011-04-13 | マーベル ワールド トレード リミテッド | Efficient transistor structure |
| US7960833B2 (en) | 2003-10-22 | 2011-06-14 | Marvell World Trade Ltd. | Integrated circuits and interconnect structure for integrated circuits |
| US7982280B2 (en) | 2003-10-22 | 2011-07-19 | Marvell World Trade Ltd. | Integrated circuits and interconnect structure for integrated circuits |
| US7989852B2 (en) | 2003-10-22 | 2011-08-02 | Marvell World Trade Ltd. | Integrated circuits and interconnect structure for integrated circuits |
| US8026550B2 (en) | 2003-10-22 | 2011-09-27 | Marvell World Trade Ltd. | Integrated circuits and interconnect structure for integrated circuits |
| EP2339637A1 (en) * | 2009-12-28 | 2011-06-29 | STMicroelectronics S.r.l. | Power MOSFET device and method of making the same |
| CN102136497A (en) * | 2009-12-28 | 2011-07-27 | 意法半导体股份有限公司 | Power MOSFET device and method of making the same |
| US8436428B2 (en) | 2009-12-28 | 2013-05-07 | Stmicroelectronics S.R.L. | Integrated common source power MOSFET device, and manufacturing process thereof |
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