JPH0579956B2 - - Google Patents
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- Publication number
- JPH0579956B2 JPH0579956B2 JP60040091A JP4009185A JPH0579956B2 JP H0579956 B2 JPH0579956 B2 JP H0579956B2 JP 60040091 A JP60040091 A JP 60040091A JP 4009185 A JP4009185 A JP 4009185A JP H0579956 B2 JPH0579956 B2 JP H0579956B2
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- 238000001514 detection method Methods 0.000 claims description 16
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- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 3
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 101100272235 Mus musculus Bcar3 gene Proteins 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
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Description
本発明は、パルス光を投射し、このパルス光に
同期した受信信号を取出して検出動作を行う光電
スイツチに関する。
The present invention relates to a photoelectric switch that projects pulsed light and performs a detection operation by extracting a received signal synchronized with the pulsed light.
光を利用して物体の検出を行う場合、パルス変
調形の光電スイツチを用い、投光パルスに同期し
た受光入力だけを取出し、その他の期間に入つた
受光入力を禁止すれば外部から入射する非連続的
な光に対しては誤動作を防止することができる。
しかしながら、光電スイツチの投光部とこの投光
部に対する受光部とは、光軸が互いに多少ずれて
も光学的結合に支障のないように投光部における
光の投射範囲が広くされているために、複数個の
光電スイツチを並置した場合には隣接する光電ス
イツチの影響を受けることがある。
例えば第５図に示すように２個の光電スイツチ
の投光部１ａ，１ｂを並置し、このそれぞれのほ
ぼ光軸上にそれぞれの受光部２ａ，２ｂを置いた
場合、受光部２ａは投光部１ａからの光が被検出
物体３によつて遮断されているにもかかわらず投
光部１ｂからの光を受けることになる。この場合
当然それぞれの投光部１ａ，１ｂからはそれぞれ
異なる周期のパルス光を投射するようにされてい
るが、パルス光の周期は似通つている場合が多
く、特に光電スイツチが多数の場合はこの傾向が
大きい。このため両投光部１ａ，１ｂのパルス光
のタイミングが全く重なることもあり、他の光電
スイツチの投射光の影響は従来のこのような同期
ゲート方式だけでは排除できないという欠点があ
る。
また、第６図に示すように２個の光電スイツチ
の両投光部１ａ，１ｂと両受光部２ａ，２ｂとを
交互に配置することも考えられているが、被検出
物体３の表面反射率が良好な場合、例えば投光部
１ａの光は完全に遮断されて受光部２ａには達し
ないが、投光部１ｂの光が被検出物体３から反射
して受光部２ａがこれを受光してしまうという欠
点がある。
さらに光電スイツチを複数個並置した場合、こ
れらの投光部が同時に投光しないように投光タイ
ミングをずらして順次投光し、対応したタイミン
グの受光信号だけを選択通過させるようなゲート
回路を設けて相互に影響を避けようという考えも
ある。しかしながら、投光タイミングをずらして
順次投光するためにはそのための制御回路が必要
となり、かつ、この制御回路からそれぞれの投・
受光回路に同期信号を伝えるための電気的接続が
必要になるため構成が複雑化し、結線作業が煩雑
になるほか、それぞれの光電スイツチを単独に使
用できないという欠点がある。
When detecting objects using light, use a pulse modulation type photoelectric switch to extract only the light receiving input synchronized with the light emitting pulse, and prohibiting the light receiving input during other periods. Malfunctions can be prevented against continuous light.
However, the light projecting area of the photoelectric switch and the light receiving part for this light projecting part are designed so that the light projection range in the light projecting part is wide so that even if the optical axes of the light projecting part are slightly shifted from each other, there is no problem in optical coupling. In addition, when a plurality of photoelectric switches are arranged side by side, they may be affected by the neighboring photoelectric switches. For example, as shown in FIG. 5, when the light emitting parts 1a and 1b of two photoelectric switches are placed side by side and the respective light receiving parts 2a and 2b are placed approximately on the respective optical axes, the light receiving part 2a emits light. Even though the light from the portion 1a is blocked by the object to be detected 3, the light from the light projecting portion 1b is received. In this case, of course, each of the light projectors 1a and 1b projects pulsed light with a different period, but the periods of the pulsed light are often similar, especially when there are a large number of photoelectric switches. This trend is significant. For this reason, the timings of the pulsed lights from the two light projectors 1a and 1b may completely overlap, and there is a drawback that the influence of the projected light from other photoelectric switches cannot be eliminated by the conventional synchronization gate method alone. Furthermore, as shown in FIG. 6, it has been considered to alternately arrange both the light emitting parts 1a, 1b and both the light receiving parts 2a, 2b of the two photoelectric switches. When the rate is good, for example, the light from the light emitter 1a is completely blocked and does not reach the light receiver 2a, but the light from the light emitter 1b is reflected from the object to be detected 3 and is received by the light receiver 2a. There is a drawback that it does. Furthermore, when multiple photoelectric switches are arranged side by side, a gate circuit is provided that shifts the light emission timing and sequentially emits light so that these light emitters do not emit light at the same time, and selectively passes only the light reception signal at the corresponding timing. There is also the idea of avoiding mutual influence. However, in order to shift the light emission timing and emit light sequentially, a control circuit is required, and this control circuit can control each emission and
Electrical connections are required to transmit the synchronization signal to the photodetector circuit, which complicates the configuration and makes wiring work complicated.In addition, each photoelectric switch cannot be used independently.
本発明は多数の光電スイツチを並置した場合、
光軸調整を必要とせず、検出領域の確保に必要な
投・受光範囲を損なうことなく、他の光電スイツ
チからの投射光の影響を除去してこの投射光によ
る誤動作を防止し、かつ相互の電気的な接続を必
要としない光電スイツチを提供することを目的と
する。
In the present invention, when a large number of photoelectric switches are arranged side by side,
This eliminates the need for optical axis adjustment, eliminates the influence of projected light from other photoelectric switches, prevents malfunctions caused by this projected light, and prevents mutual interference without compromising the light emitting/receiving range necessary to secure the detection area. The purpose is to provide a photoelectric switch that does not require electrical connection.
本発明は周期的にパルスを発生するパルス発生
回路と、該パルス発生回路のパルスに応じてパル
ス点灯する投光部と、該投光部の光を受けて受光
信号を発生する受光部と、前記受光部からの受光
信号を記憶する受光信号記憶回路と、前記受光信
号の連続回数を計数し、受光信号が非連続のとき
クリアされるカウンタ回路と、該カウンタ回路の
連続計数値が第１の所定値に達すると前記パルス
発生回路を制御して次のパルスの発生時刻を変え
るパルス制御回路と、前記カウンタ回路の連続計
数値が第２の所定値に達すると検出信号を送出す
る検出回路とを備えてなるもので、カウンタ回路
が受光信号を第１の所定値まで連続計数するとパ
ルス制御回路が次の投光パルスの発生時刻を変え
て（一般には早める）外部からの不必要な投光パ
ルスとのタイミングをずらし、カウンタが第２の
所定値まで計数したときはじめて検出回路から検
出信号を送出させて誤動作を防止しようという構
成できる。
The present invention includes a pulse generating circuit that periodically generates pulses, a light projecting section that lights up pulses in response to the pulses of the pulse generating circuit, and a light receiving section that receives light from the light projecting section and generates a light reception signal. a light-receiving signal storage circuit that stores the light-receiving signal from the light-receiving section; a counter circuit that counts the number of consecutive light-receiving signals and is cleared when the light-receiving signal is discontinuous; a pulse control circuit that controls the pulse generation circuit to change the generation time of the next pulse when a second predetermined value is reached; and a detection circuit that sends out a detection signal when the continuous count value of the counter circuit reaches a second predetermined value. When the counter circuit continuously counts the light reception signal up to a first predetermined value, the pulse control circuit changes (generally advances) the generation time of the next light emission pulse to prevent unnecessary light emission from the outside. A configuration can be constructed in which the timing with the optical pulse is shifted and the detection signal is sent out from the detection circuit only when the counter counts up to a second predetermined value, thereby preventing malfunction.
以下本発明の実施例を第１図ないし第４図に基
づいて詳細に説明する。第１図において、光電ス
イツチは、投光部１、受光部２、パルス発生回路
６、受光信号記憶回路８、カウンタ回路９、パル
ス制御回路１０、検出回路１１を備えている。
パルス発生回路６は発振器１２、３個のＴ形フ
リツプフロツプ（以下フリツプフロツプをFFと
略称する）１３，１４，１５からなり発振器１２
の出力がFF１３のＴ端子に接続され、FF１３の
Ｑ端子はFF１４のＴ端子に、FF１４の端子は
次のFF１５のＴ端子にそれぞれ接続されて３個
のFF１３，１４，１５は、発振器１２のパルス
を順次1/2，1/4，1/8と逓降し、いわゆる分周器
として動作する。
パルス制御回路１０はインバータ１６、３個の
ANDゲート１７，１８，１９、NANDゲート２
０からなり、３個のANDゲート１７，１８，１
９のそれぞれのａ入力端子には発振器１２の出力
端がインバータ１６を介して接続され、それぞれ
のｄ端子にはFF１５の端子が接続されている。
また、ANDゲート１７とNANDゲート２０のそ
れぞれのｂ入力端子にはFF１３のＱ端子が接続
され、２個のANDゲート１８，１９のそれぞれ
のｂ端子にはFF１３の端子が接続されている。
２個のANDゲート１７，１８のそれぞれのｃ入
力端子とNANDゲート２０のｃ入力端子にはFF
１４の端子が接続され、NANDゲート２０の
ａ入力端子にはFF１５のＱ端子が接続され、
NANDゲート２０の出力端子は３個のFF１３，
１４，１５のそれぞれのリセツト端子に接続され
ている。NANDゲート２０の入力端子には後に
述べるカウンタ３５の“４”カウント端子が接続
されている。
投光部１は電流制御抵抗２１と発光ダイオード
２２との直列回路でANDゲート１７の出力端子
に接続されて、発光ダイオード２２はこの出力パ
ルスでパルス発光する。
受光部２はホトトランジスタ２３、コンデンサ
２４、増幅器２５、比較回路２６からなり、ホト
トランジスタ２３が受光したパルス光の交流分を
増幅器２５で増幅し、この出力が動作レベルを超
えると完全な矩形波に整形された受光信号を発生
する。
受光信号記憶回路８は、ANDゲート２７，FF
２８からなり、ANDゲート２７は、一方の入力
端子がANDゲート１７の出力端子に接続され、
他方の入力端子は受光部２の出力端子に接続さ
れ、この出力端子はFF２８のセツト端子Ｓに接
続され、FF２８のリセツト端子ＲにはANDゲー
ト１８の出力端子が接続されている。したがつて
FF２８は、ANDゲート１８の出力パルスでリセ
ツトされ、投光パルス期間に受光信号があると
ANDゲート２７が開いてセツトされ、受光信号
が受光部から送出されたことを記憶する。
カウンタ回路９は、排他的論理回路（以下EX
−ORゲートと略称する）３１、インバータ３
２、２個のANDゲート３３，３４、カウンタ３
５からなり、EX−ORゲート３１は、一方の入
力端子がFF２８のＱ端子に、他方の入力端子が
後で説明する検出回路１１の出力端子３９がそれ
ぞれ接続され、出力端子がANDゲート３３の一
方の入力端子と、インバータ３２を介してAND
ゲート３４の一方の入力端子に接続されている。
この２個のANDゲート３３，３４の他方の入力
端子はANDゲート１９の出力端子に接続されて
いる。また、ANDゲート３３の出力端子はカウ
ンタ３５の入力端子Ｉに、ANDゲート３４の出
力端子はカウンタ３５のクリヤ端子Ｃにそれぞれ
接続されている。カウンタ３５は、その入力端子
に４個のパルスが連続入力すると信号を送出する
“４”カウント端子と、パルスが連続７個入力す
ると信号を送出する“７”カウント端子とを有
し、“４”カウント端子は既に述べたNAND回路
２０のｄ入力端子に、“７”カウント端子は次に
説明する検出回路１１の２個のANDゲート３６，
３７の一方の入力端子に接続されている。
検出回路１１は、２個のANDゲート３６，３
７とFF３８を備え、この両ANDゲート３６，３
７の他方の入力端子にはFF２８のＱ，両端子
がそれぞれ接続され、それぞれの一方の入力端子
には既に述べたカウンタ３５の“７”カウント端
子が共通に接続されている。そしてFF３８のセ
ツト端子ＳにANDゲート３６の出力端子がリセ
ツト端子ＲにANDゲート３７の出力端子がそれ
ぞれ接続され、Ｑ端子がこの光電スイツチの出力
端子３９とされている。
次に第２図ないし第４図は第１図各主要部の出
力波形を示すタイムチヤートである。第２図にお
いて発振器１２の出力Ｇ１２がFF１３のＴ端子
に印加されるとFF１３の端子の出力Ｇ１３は
Ｇ１２が次のハイレベル（以下このハイレベルを
Ｈと称する）になるとき同時にＨになり、さらに
次のＨになるときにＬになる。そして次のFF１
４のＴ端子に印加され、FF１４の端子の出力
Ｑ１４は、Ｑ１３がローレベル（以下このローレ
ベルをＬと称する）になるとＬとなり、次にＬに
なるときにＨになる。そしてFF１５のＴ端子に
印加され、FF１５の端子の出力Ｑ１５はＱ１
４がＬになるとＬになり、次のＬになるときにＨ
になる。かくしてFF１３，FF１４，FF１５の
周期は発振器１２の周期が1/2，1/4，1/8と分周
される。そしてANDゲート１７の総ての入力が
Ｈのときだけその出力AND１７がＨになり、
ANDゲート１８の総ての入力がＨのときだけそ
の出力AND１８がＨになる。勿論ANDゲート１
９の総ての入力がＨとなつたときだけその出力
AND１９がＨになる。このようにしてAND１
７，AND１８，AND１９の各パルス波形はそれ
ぞれパルス発生回路６が発生したパルスをパルス
制御回路１０の３個のANDゲート１７，１８，
１９から互いに重ならないように同じ周期で順次
送出される。そして第３図に示すようにパルス
AND１８がFF２８をリセツトした後、発光部１
の発光ダイオード２２がパルスAND１７で発光
し投光する。はじめ時刻t0に投光部１と受光部２
が図示しない被検出体で遮断されていると、受光
部２は受光しないから増幅器２５の出力波形
Amp２５、比較器２６の出力波形Comp２６はロ
ーレベル（以下ローレベルをＬと略称する）であ
る。またComp２６がＬであるからANDゲート
２７は閉じ、FF２８のＱ出力波形FO２８もＬで
ある。従つてEX−ORゲート３１の出力もＬで
あるからANDゲート３３は閉じ、その出力波形
AND３３もＬである。このときインバータ３２
の出力は反転してハイレベル（以下ハイレベルを
Ｈと略称する）となるから、カウンタ３５はパル
スAND１９がANDゲート３４を通過したパルス
AND３４でクリヤされる。勿論カウンタ３５の
“７”カウント端子の出力はＬであるから出力端
子３９の出力はＬである。
次に時刻t1に投光部１と受光部２との間の被検
出体が除去されるとホトダイオード２３が受光
し、増幅器２５の出力はコンデンサ２４を充放電
する三日月状のパルスAmp２５を送出し、比較
器２６で整形されてパルスAND１７と同じ波形、
同じ周期のパルスComp２６になり、FF２８の
出力FO２８は、２個のパルスAND１７，Comp
２６でＨになり、パルスAND１８でＬになる。
この出力FO２８の波形の幅は広い。こうしてEX
−ORゲート３１の出力がＨになり、ANDゲート
１９の出力パルスAND１９がANDゲート３３を
介してパルスAND３３としてカウンタ３５に出
力する。パルスAND３３にそれぞれ記入された
数値はカウンタ３５の計数値である。このように
してカウンタ３５はパルスAND１９言い換えれ
ばパルスAND３３を４個まで計数し、時刻t2に
“４”カウント端子がＨになる。この信号Ｈは
NANDゲート２０のｄ入力端子に印加されて
NANDゲート２０の出力Ｎ２０が３個のFF１
３，１４，１５をリセツトする（第２図参照）。
そして３個のANDゲート１７，１８，１９の最
初のパルスはその以前の１周期T1より早い１周
期T2に送出され、以後は以前と同じ周期T1のパ
ルスを繰り返す。したがつて、カウンタ３５の入
力は４カウントと５カウントの間がそれ以前の周
期T1より短くなるが以後は同じ周期T1に戻る。
そして時刻t3までに７個計数すると“７”カウン
ト端子の信号がＨになり、２個のANDゲート３
６，３７が開くから受光したことを記憶していた
FF２８の出力がこのANDゲート３６，３７を介
して時刻t3にFF３８を動作させ出力回路１１の
出力端子３９にＨの信号Ｔ３９を送出する。この
信号Ｔ３９とFF２８の信号が共にＨになればEX
−ORゲート３１の出力はＬになり、カウンタ３
５の計数を停止するとともにインバータ３２の出
力が反転してパルスAND１９、言い換えれば
ANDゲート３４のパルスAND３４でカウンタ３
５の計数をクリヤして光電スイツチの一動作が終
了する。その後時刻t4にパルスAND１８FF２８
がリセツトされると、その端子がＨになり、
FF３８がリセツトされて出力端子３９の信号は
Ｌに低下する。ここで投光部１と受光部２との間
の光が再び遮断されると、光電スイツチはタイム
チヤートの時刻t0から同じ動作を繰り返す。
ところで、もし投光部１と受光部２とが被検出
物体で遮断されているにもかかわらず、パルス発
生回路６が発生するパルスの周期とほぼ同じ周期
の投光パルスをホトトランジスタ２３が他の光源
から受光した場合、第４図に示すように３個の
FF１３，１４，１５が“４”カウント端子のＨ
信号でリセツトされた後、３個のパルスAND１
７，AND１８，AND１９はそれぞれ第１発がそ
れ以前の周期T1より短い周期T2で送出されるが、
増幅器２５の出力Amp２５の周期T1は全く変化
せず、これに従つてパルスComp２６の周期T1も
変化しないからパルスAND１７パルスComp２
６が同時にANDゲート２７に入力することがな
くFF２８はセツトされない。したがつて信号FO
２８はＬであり、勿論この時点では検出回路１１
の出力信号もＬであるからEX−ORゲート３１
の出力はＬであり、インバータ３２の出力が反転
してＨとなつてANDゲート３４はパルスAND１
９でカウンタ３５をクリヤしてしまい投光パルス
を７個までカウントすることはなく、検出回路１
１の出力端子３９にはＨの信号は送出されない。
すなわち誤動作することはない。また、もしこの
スイツチの投光部以外からの光がホトダイオード
に周期T2で入射した場合は、ANDゲート２７の
両入力が連続して一致することがないからこの出
力信号がＨになつてFF２８がセツトされること
が少なく、常時リセツトされ、カウンタ３５はパ
ルスを計数することなく、スイツチとしての誤動
作はしない。
Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 4. In FIG. 1, the photoelectric switch includes a light projecting section 1, a light receiving section 2, a pulse generation circuit 6, a received light signal storage circuit 8, a counter circuit 9, a pulse control circuit 10, and a detection circuit 11. The pulse generating circuit 6 includes an oscillator 12 and three T-type flip-flops (hereinafter referred to as FF) 13, 14, and 15.
The output of FF13 is connected to the T terminal of FF13, the Q terminal of FF13 is connected to the T terminal of FF14, and the terminal of FF14 is connected to the T terminal of the next FF15. It sequentially steps down the pulse to 1/2, 1/4, and 1/8, and operates as a so-called frequency divider. The pulse control circuit 10 includes an inverter 16 and three
AND gate 17, 18, 19, NAND gate 2
0, and three AND gates 17, 18, 1
The output terminal of the oscillator 12 is connected to each a input terminal of 9 via an inverter 16, and the terminal of FF 15 is connected to each d terminal.
Further, the Q terminal of the FF 13 is connected to the b input terminal of each of the AND gate 17 and the NAND gate 20, and the terminal of the FF 13 is connected to the b terminal of each of the two AND gates 18 and 19.
The c input terminal of each of the two AND gates 17 and 18 and the c input terminal of the NAND gate 20 are connected to FF.
14 terminals are connected, and the Q terminal of FF15 is connected to the a input terminal of the NAND gate 20.
The output terminal of the NAND gate 20 is three FF13,
It is connected to the respective reset terminals 14 and 15. An input terminal of the NAND gate 20 is connected to a "4" count terminal of a counter 35, which will be described later. The light projecting section 1 is connected to the output terminal of the AND gate 17 through a series circuit of a current control resistor 21 and a light emitting diode 22, and the light emitting diode 22 emits pulsed light in response to this output pulse. The light receiving section 2 consists of a phototransistor 23, a capacitor 24, an amplifier 25, and a comparison circuit 26. The amplifier 25 amplifies the alternating current portion of the pulsed light received by the phototransistor 23, and when this output exceeds the operating level, it becomes a complete rectangular wave. A received light signal is generated that is shaped as follows. The light reception signal storage circuit 8 includes an AND gate 27, FF
28, the AND gate 27 has one input terminal connected to the output terminal of the AND gate 17,
The other input terminal is connected to the output terminal of the light receiving section 2, this output terminal is connected to the set terminal S of the FF 28, and the output terminal of the AND gate 18 is connected to the reset terminal R of the FF 28. Therefore
The FF28 is reset by the output pulse of the AND gate 18, and if there is a light reception signal during the light emission pulse period.
The AND gate 27 is opened and set to remember that the light receiving signal has been sent out from the light receiving section. The counter circuit 9 is an exclusive logic circuit (hereinafter EX
-OR gate) 31, inverter 3
2, 2 AND gates 33, 34, counter 3
In the EX-OR gate 31, one input terminal is connected to the Q terminal of the FF 28, the other input terminal is connected to the output terminal 39 of the detection circuit 11, which will be explained later, and the output terminal is connected to the Q terminal of the AND gate 33. AND between one input terminal and the inverter 32
It is connected to one input terminal of gate 34.
The other input terminal of the two AND gates 33 and 34 is connected to the output terminal of the AND gate 19. Further, the output terminal of the AND gate 33 is connected to the input terminal I of the counter 35, and the output terminal of the AND gate 34 is connected to the clear terminal C of the counter 35. The counter 35 has a "4" count terminal that sends out a signal when four pulses are continuously input to its input terminal, and a "7" count terminal that sends out a signal when seven pulses are continuously input to the input terminal. The "7" count terminal is connected to the d input terminal of the NAND circuit 20 described above, and the "7" count terminal is connected to the two AND gates 36 of the detection circuit 11, which will be described next.
It is connected to one input terminal of 37. The detection circuit 11 includes two AND gates 36, 3
7 and FF38, both AND gates 36, 3
The Q and both terminals of the FF 28 are connected to the other input terminal of the FF 28, and the "7" count terminal of the counter 35 mentioned above is commonly connected to one input terminal of each. The output terminal of the AND gate 36 is connected to the set terminal S of the FF 38, the output terminal of the AND gate 37 is connected to the reset terminal R, and the Q terminal is used as the output terminal 39 of this photoelectric switch. Next, FIGS. 2 to 4 are time charts showing output waveforms of each main part in FIG. 1. In FIG. 2, when the output G12 of the oscillator 12 is applied to the T terminal of FF13, the output G13 of the terminal of FF13 becomes H at the same time when G12 becomes the next high level (hereinafter this high level is referred to as H). Furthermore, it becomes L when it becomes the next H. And the next FF1
The output Q14 from the terminal of the FF 14 becomes L when Q13 becomes a low level (hereinafter this low level is referred to as L), and becomes H when it becomes L next. Then, it is applied to the T terminal of FF15, and the output Q15 of the terminal of FF15 is Q1
When 4 becomes L, it becomes L, and when it becomes the next L, it becomes H.
become. Thus, the periods of FF13, FF14, and FF15 are the periods of the oscillator 12 divided into 1/2, 1/4, and 1/8. Then, only when all the inputs of AND gate 17 are H, its output AND17 becomes H,
Only when all the inputs of AND gate 18 are H, its output AND18 becomes H. Of course AND gate 1
The output only when all inputs of 9 become H.
AND19 becomes H. In this way AND1
Each pulse waveform of 7, AND18, AND19 is a pulse generated by the pulse generation circuit 6, and the three AND gates 17, 18, of the pulse control circuit 10, respectively.
From No. 19 onwards, they are sent out sequentially at the same cycle so as not to overlap each other. Then, as shown in Figure 3, the pulse
After AND18 resets FF28, light emitting section 1
The light emitting diode 22 emits light and projects light with the pulse AND17. At the initial time t 0 , the light emitter 1 and the light receiver 2
is blocked by an object to be detected (not shown), the light receiving section 2 does not receive light, so the output waveform of the amplifier 25
The output waveform Comp26 of Amp25 and comparator 26 is at a low level (hereinafter, low level will be abbreviated as L). Also, since Comp26 is at L, AND gate 27 is closed, and Q output waveform FO28 of FF28 is also at L. Therefore, since the output of EX-OR gate 31 is also L, AND gate 33 is closed, and its output waveform is
AND33 is also L. At this time, the inverter 32
Since the output of is inverted and becomes a high level (hereinafter, high level is abbreviated as H), the counter 35 receives the pulse AND19 which has passed through the AND gate 34.
Cleared by AND34. Of course, since the output of the "7" count terminal of the counter 35 is L, the output of the output terminal 39 is L. Next, at time t 1 , when the object to be detected between the light emitter 1 and the light receiver 2 is removed, the photodiode 23 receives the light, and the output of the amplifier 25 sends out a crescent-shaped pulse Amp 25 that charges and discharges the capacitor 24. Then, it is shaped by the comparator 26 and has the same waveform as the pulse AND17,
The pulse Comp26 has the same period, and the output FO28 of FF28 is the two pulses AND17, Comp
It becomes H at 26, and becomes L at pulse AND18.
The width of the waveform of this output FO28 is wide. In this way EX
- The output of the OR gate 31 becomes H, and the output pulse AND19 of the AND gate 19 is outputted to the counter 35 as a pulse AND33 via the AND gate 33. The numerical values written in each pulse AND33 are the counted values of the counter 35. In this way, the counter 35 counts up to four pulses AND19, in other words, pulses AND33, and the "4" count terminal becomes H at time t2 . This signal H is
Applied to the d input terminal of the NAND gate 20
The output N20 of the NAND gate 20 is three FF1
3, 14, and 15 (see Figure 2).
The first pulse of the three AND gates 17, 18, 19 is sent out in one period T2 earlier than the previous one period T1 , and thereafter the pulses of the same period T1 as before are repeated. Therefore, the input to the counter 35 is shorter between the 4th count and the 5th count than the previous cycle T1 , but thereafter returns to the same cycle T1 .
When 7 items are counted by time t3 , the signal at the "7" count terminal becomes H, and the two AND gates 3
6,37 opened, so I remembered that it received light.
The output of the FF 28 operates the FF 38 via the AND gates 36 and 37 at time t3, and sends an H signal T39 to the output terminal 39 of the output circuit 11. If both the signals T39 and FF28 become H, EX
-The output of OR gate 31 becomes L, and counter 3
5 is stopped and the output of the inverter 32 is inverted to produce a pulse AND19, in other words.
Counter 3 with pulse AND34 of AND gate 34
When the count of 5 is cleared, one operation of the photoelectric switch is completed. After that, at time t 4 , pulse AND18FF28
When is reset, that terminal becomes H,
The FF 38 is reset and the signal at the output terminal 39 drops to L. When the light between the light emitter 1 and the light receiver 2 is cut off again, the photoelectric switch repeats the same operation from time t0 on the time chart. Incidentally, even if the light emitting section 1 and the light receiving section 2 are blocked by an object to be detected, if the phototransistor 23 transmits a light emitting pulse with approximately the same period as that of the pulse generated by the pulse generating circuit 6, When receiving light from a light source, three
FF13, 14, 15 are “4” count terminal H
After being reset with a signal, three pulses AND1
7, AND18, and AND19, the first one of which is sent out at a cycle T2 shorter than the previous cycle T1 ,
The period T1 of the output Amp25 of the amplifier 25 does not change at all, and accordingly the period T1 of the pulse Comp26 also does not change, so the pulse AND17 pulse Comp2
6 are not input to the AND gate 27 at the same time, and the FF 28 is not set. Therefore the signal FO
28 is L, and of course at this point the detection circuit 11
Since the output signal of is also L, EX-OR gate 31
The output of the inverter 32 is inverted and becomes H, and the AND gate 34 outputs the pulse AND1.
9, the counter 35 is cleared and the emitted light pulses are not counted up to 7, and the detection circuit 1
No H signal is sent to the output terminal 39 of No. 1.
In other words, there will be no malfunction. Also, if light from a source other than the light projecting section of this switch is incident on the photodiode with a period of T 2 , the output signal becomes H because the two inputs of the AND gate 27 do not match continuously. The counter 35 is rarely set and is always reset, so the counter 35 does not count pulses and does not malfunction as a switch.
以上述べたように本発明によれば、カウンタ回
路の連続計数値が第１の所定値に達するとパルス
発生回路は次のパルスの発生時刻を変えるから、
たとえ外部から初めの周期に同期したパルス光が
受光部に入射していてもここで同期が破られカウ
ンタ回路は以後の計数を停止し、第２の所定値ま
で計数しないから、検出回路はスイツチの動作信
号を発することがなく、受光部に入射するパルス
光が外乱光であるか否かを何ら判断することなく
外乱光による誤動作を防止して自己のパルス光を
確実に検出することができ、他の光電スイツチと
の連携接続なしに光電スイツチとの相互干渉が防
止できる。
As described above, according to the present invention, when the continuous count value of the counter circuit reaches the first predetermined value, the pulse generation circuit changes the generation time of the next pulse.
Even if pulsed light synchronized with the first cycle is incident on the light receiving section from the outside, the synchronization is broken and the counter circuit stops counting from then on and does not count up to the second predetermined value, so the detection circuit does not switch. It is possible to reliably detect the own pulsed light without emitting any operating signal, and without making any judgments as to whether or not the pulsed light incident on the light receiving section is ambient light, preventing malfunctions caused by ambient light. , Mutual interference with photoelectric switches can be prevented without cooperative connection with other photoelectric switches.
第１図は本発明による光電スイツチの一実施例
を示す結線図、第２図はパルス発生回路とパルス
制御回路の動作を示すタイムチヤート、第３図は
第１図に示す光電スイツチの平常動作を示すタイ
ムチヤート、第４図は第１図に示す光電スイツチ
の受光部が他の光源からの光を受光した場合の動
作を示すタイムチヤート、第５図、第６図は複数
の光電スイツチを並置した場合、隣接投光部の影
響を受ける例を示し、第５図は互いに対向する投
光部と受光部を並置した場合、第６図は互いに対
向する投光部と受光部を交互に入れ換えて並置し
た場合を示す。
１……投光部、２……受光部、６……パルス発
生回路、８……受光信号記憶回路、９……カウン
タ回路、１０……パルス制御回路、１１……検出
回路。
Fig. 1 is a wiring diagram showing one embodiment of the photoelectric switch according to the present invention, Fig. 2 is a time chart showing the operation of the pulse generation circuit and pulse control circuit, and Fig. 3 is a normal operation of the photoelectric switch shown in Fig. 1. Figure 4 is a time chart showing the operation when the light receiving section of the photoelectric switch shown in Figure 1 receives light from another light source. Figures 5 and 6 are time charts showing the operation of multiple photoelectric switches. Figure 5 shows an example in which the opposite light emitters and light receivers are juxtaposed, and Figure 6 shows the example in which the opposite light emitters and light receivers are alternately arranged. This shows the case where they are swapped and placed side by side. DESCRIPTION OF SYMBOLS 1...Light emitter, 2...Light receiver, 6...Pulse generation circuit, 8...Light reception signal storage circuit, 9...Counter circuit, 10...Pulse control circuit, 11...Detection circuit.
Claims (1)
と、該パルス発生回路のパルスに応じてパルス点
灯する投光部と、該投光部の光を受けて受光信号
を発生する受光部と、前記受光部からの受光信号
を記憶する受光信号記憶回路と、前記受光信号の
連続回数を計数し、受光信号が非連続のときクリ
アされるカウンタ回路と、該カウンタ回路の連続
計数値が第１の所定値に達すると前記パルス発生
回路を制御して次のパルスの発生時刻を変えるパ
ルス制御回路と、前記カウンタ回路の連続計数値
が第２の所定値に達すると検出信号を送出する検
出回路とを備えてなることを特徴とする光電スイ
ツチ。1. A pulse generating circuit that periodically generates pulses, a light projecting section that lights up pulses in response to the pulses of the pulse generating circuit, a light receiving section that receives light from the light projecting section and generates a light reception signal, and the light receiving section. a light reception signal storage circuit that stores the light reception signal from the unit; a counter circuit that counts the number of consecutive light reception signals and is cleared when the light reception signal is discontinuous; a pulse control circuit that controls the pulse generation circuit to change the generation time of the next pulse when the value reaches a second predetermined value; and a detection circuit that sends out a detection signal when the continuous count value of the counter circuit reaches a second predetermined value. A photoelectric switch characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60040091A JPS61198094A (en) | 1985-02-28 | 1985-02-28 | Photoelectric switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60040091A JPS61198094A (en) | 1985-02-28 | 1985-02-28 | Photoelectric switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61198094A JPS61198094A (en) | 1986-09-02 |
| JPH0579956B2 true JPH0579956B2 (en) | 1993-11-05 |
Family
ID=12571213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60040091A Granted JPS61198094A (en) | 1985-02-28 | 1985-02-28 | Photoelectric switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61198094A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2553806B2 (en) * | 1992-09-11 | 1996-11-13 | サンクス株式会社 | Photoelectric switch |
| EP0675376B1 (en) * | 1993-10-12 | 1998-01-07 | The Nippon Signal Co. Ltd. | Fail-safe multiple optical-axis light beam sensor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5642632U (en) * | 1979-09-08 | 1981-04-18 | ||
| JPS5873888A (en) * | 1982-09-18 | 1983-05-04 | Omron Tateisi Electronics Co | Photoelectric switch |
| JPS5836382B2 (en) * | 1980-04-11 | 1983-08-09 | パナフアコム株式会社 | Shared bus control method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5836382U (en) * | 1981-09-02 | 1983-03-09 | 日本信号株式会社 | Optical level crossing obstacle detection device |
-
1985
- 1985-02-28 JP JP60040091A patent/JPS61198094A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5642632U (en) * | 1979-09-08 | 1981-04-18 | ||
| JPS5836382B2 (en) * | 1980-04-11 | 1983-08-09 | パナフアコム株式会社 | Shared bus control method |
| JPS5873888A (en) * | 1982-09-18 | 1983-05-04 | Omron Tateisi Electronics Co | Photoelectric switch |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61198094A (en) | 1986-09-02 |
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