JPH0577190B2 - - Google Patents
Info
- Publication number
- JPH0577190B2 JPH0577190B2 JP25021785A JP25021785A JPH0577190B2 JP H0577190 B2 JPH0577190 B2 JP H0577190B2 JP 25021785 A JP25021785 A JP 25021785A JP 25021785 A JP25021785 A JP 25021785A JP H0577190 B2 JPH0577190 B2 JP H0577190B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- anode
- diode
- cathode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 5
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
Landscapes
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路の構造に関し、特にバ
イポーラ型素子を含む集積回路におけるダイオー
ドの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor integrated circuit, and particularly to the structure of a diode in an integrated circuit including bipolar elements.
この種のダイオードとして以下に述べる2種の
構造を用いるのが一般的である。
Two types of structures described below are generally used as this type of diode.
第4図に第1の種類のダイオードをその等価回
路図で示す。即ち、この種のダイオードは、集積
回路に用いられるNPNトランジスタのコレクタ
とベースを短絡させてアノード電極とし、NPN
トランジスタのエミツタ電極をカソード電極とし
ている。通常、バイボーラ型集積回路において
は、NPNトランジスタが最も高性能となるよう
に、構造及び製造プロセスが作られている為に、
このエミツタ・ベース(EB)接合を用いたダイ
オードも高性能となり従つて多く用いられる。但
し通常高性能のNPNトランジスタにおいては、
高速化を目的としてEB接合が浅く、高不純物濃
度領域に形成されている為に、逆方向耐圧が低
く、3V以下となる場合が一般的である。半導体
集積回路は5V以上の電源電圧で動作させる場合
が多く、時としてダイオードの逆方向耐圧として
3V以上が要求される場合がある。このように高
逆方向耐圧が必要な場合には通常以下に説明する
コレクタ・ベース(CB)接合を用いたダイオー
ドが用いられる。 FIG. 4 shows an equivalent circuit diagram of the first type of diode. In other words, this type of diode shorts the collector and base of an NPN transistor used in integrated circuits to serve as an anode electrode.
The emitter electrode of the transistor is used as the cathode electrode. Normally, in bibolar integrated circuits, the structure and manufacturing process are designed so that NPN transistors have the highest performance.
Diodes using this emitter-base (EB) junction also have high performance and are therefore widely used. However, in normal high-performance NPN transistors,
Because the EB junction is shallow and formed in a high impurity concentration region for the purpose of high speed, the reverse breakdown voltage is low, typically 3V or less. Semiconductor integrated circuits are often operated with a power supply voltage of 5V or higher, and sometimes the reverse breakdown voltage of a diode is
3V or more may be required. When such a high reverse breakdown voltage is required, a diode using a collector-base (CB) junction, which will be described below, is usually used.
第5図はCB接合を用いたダイオードの断面図
を示す。P型基板51上に高濃度n型埋込み領域
52とn型エピタキシヤル領域53とを形成して
カソード領域とし、n型エピタキシヤル領域53
の表面に形成されたP型領域54をアノード領域
とし、カソード領域の周囲にP型絶縁領域55を
設ける。そして、表面を絶縁層57で被つた後、
カソード電極およびアノード電極取り出し用のコ
ンタクトが開口され、Al等の金属膜によるアノ
ード電極58、カソード電極59が取り付けられ
る。通常NPNトランジスタのCB接合の逆方向耐
圧は10V以上ある為に、高逆方向耐圧を要するダ
イオードとしては、第5図で示したCB接合ダイ
オードが適していることになる。 FIG. 5 shows a cross-sectional view of a diode using a CB junction. A heavily doped n-type buried region 52 and an n-type epitaxial region 53 are formed on a P-type substrate 51 to serve as a cathode region.
A P-type region 54 formed on the surface of the substrate is used as an anode region, and a P-type insulating region 55 is provided around the cathode region. After covering the surface with an insulating layer 57,
Contacts for taking out the cathode electrode and anode electrode are opened, and an anode electrode 58 and a cathode electrode 59 made of a metal film such as Al are attached. Since the reverse breakdown voltage of the CB junction of an NPN transistor is usually 10 V or more, the CB junction diode shown in Figure 5 is suitable as a diode that requires a high reverse breakdown voltage.
第5図を用いて説明したCB接合ダイオードに
は構造上、ダイオードのP型領域54をエミツ
タ、n型領域53をベース、P型基板51及びP
型絶縁領域55をコレクタとした寄生PNPトラ
ンジスタが形成されることになる。この寄生
PNP動作によつて、ダイオードに流れる電流の
一部は基板に流入することになる。このことは無
駄な電力の消費という問題以外に、基板電位の上
昇に起因するラツチアツプ等の寄生現象を伴う場
合もあり好ましくない。従つてCB接合ダイオー
ドにおいては、上記寄生PNPトランジスタのhFE
を十分に低くする必要がある。第5図で示す従来
のCB接合ダイオードの場合乗直方向のPNPトラ
ンジスタのhFEはn型埋込み領域52が存在する
為に十分に低いが、P型絶縁領域55をコレクタ
領域とする横方向のhFEはかなり高くなるという
欠点がある。
The CB junction diode explained using FIG.
A parasitic PNP transistor is formed with the type insulating region 55 as the collector. This parasitism
Due to PNP operation, a portion of the current flowing through the diode will flow into the substrate. This is undesirable because not only is there a problem of wasteful power consumption, but also parasitic phenomena such as latch-up due to an increase in substrate potential are caused. Therefore, in the CB junction diode, h FE of the above parasitic PNP transistor
needs to be sufficiently low. In the case of the conventional CB junction diode shown in FIG. 5, the h FE of the PNP transistor in the vertical direction is sufficiently low due to the presence of the n-type buried region 52, but the h FE has the disadvantage of being quite high.
そこで第3図に示すようにP型アノード領域3
4とP型絶縁領域35との間のN型エピタキシヤ
ル領域33内に、高濃度N型領域36を設けるこ
ともできる。この場合、P型アノード領域34を
エミツタ、N型エピタキシヤル領域33をベー
ス、P型絶縁領域35をコレクタとする寄生トラ
ンジスタは、そのベース領域が高濃度N型領域3
6により遮断されhFEが低下するが、基板への電
流の流入を十分小さくするには高濃度N型領域3
6を大きく形成しなければならない。 Therefore, as shown in FIG.
A heavily doped N-type region 36 can also be provided in the N-type epitaxial region 33 between the P-type insulating region 35 and the P-type insulating region 35 . In this case, a parasitic transistor having the P-type anode region 34 as an emitter, the N-type epitaxial region 33 as a base, and the P-type insulating region 35 as a collector has a base region that is connected to the heavily doped N-type region 3.
6, and h FE decreases, but in order to sufficiently reduce the flow of current into the substrate, the high concentration N-type region 3
6 must be formed large.
本発明の目的は寄生のhFEの十分に低いCB接合
ダイオードを提供することにある。 An object of the present invention is to provide a CB junction diode with sufficiently low parasitic h FE .
本発明の半導体装置は、P型基板に形成された
高濃度n型埋込領域とこの基板上に成長したn型
エピタキシヤル領域とをn型カソード領域とし、
n型エピタキシヤル表面に形成されたP型領域を
アノード領域とし、カソード領域の周囲がP型絶
縁領域で囲まれた構造を有する半導体集積回路に
おいて、アノード領域と、P型絶縁領域との間に
カソード領域を囲む不純物領域を設けたことを特
徴とする。
In the semiconductor device of the present invention, a heavily doped n-type buried region formed in a p-type substrate and an n-type epitaxial region grown on this substrate are used as an n-type cathode region,
In a semiconductor integrated circuit having a structure in which a P-type region formed on an n-type epitaxial surface is an anode region and a cathode region is surrounded by a P-type insulating region, there is a region between the anode region and the P-type insulating region. It is characterized by providing an impurity region surrounding the cathode region.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の第一の実施例を示す断面図で
ある。P型基板11上に高濃度n型埋込み領域1
2とn型エピタキシヤル領域13とを形成してn
型カソード領域とし、n型エピタキシヤル領域1
3の表面に形成されたP型領域をP型アノード領
域14とし、カソード領域の周囲をP型絶縁領域
15で囲み、アノード領域とP型絶縁領域15と
の間に、アノード領域を囲む形でP型領域16を
設ける。P型領域16はP型アノード領域14と
同時に形成が可能である。表面を絶縁膜17で被
つた後、コンタクトが開口されアノード電極1
8、カソード電極19として各々金属電極を設け
る。P型領域16には金属電極は設けない。即
ち、P型領域16は電気的に浮遊状態にある。 FIG. 1 is a sectional view showing a first embodiment of the present invention. High concentration n-type buried region 1 on P-type substrate 11
2 and an n-type epitaxial region 13 are formed.
type cathode region, and n-type epitaxial region 1.
The P-type region formed on the surface of 3 is used as a P-type anode region 14, the cathode region is surrounded by a P-type insulating region 15, and a region surrounding the anode region is provided between the anode region and the P-type insulating region 15. A P-type region 16 is provided. P-type region 16 can be formed simultaneously with P-type anode region 14. After covering the surface with an insulating film 17, a contact is opened and the anode electrode 1
8. A metal electrode is provided as each cathode electrode 19. No metal electrode is provided in the P-type region 16. That is, the P-type region 16 is in an electrically floating state.
第1図で示した構造におけるP型アノード領域
14とn型エピタキシヤル領域13とP型絶縁領
域15とP型領域16によつて構成される等価回
路を第2図に示す。P型アノード領域14をエミ
ツタ、n型エピタキシヤル領域13をベース、P
型領域16をコレクタとして構成されるPNPト
ランジスタのベース接地電流増幅率をα1、P型領
域16をエミツタ、n型エピタキシヤル領域13
をベース、P型絶縁領域15をエミツタとして構
成されるPNPトランジスタのベース接地電流増
幅率をα2とすると、アノードに注入される電流の
α1×α2倍の電流がP型絶縁領域に流れることにな
る。ベース接地電流増幅率は1より小さい値であ
り、寄生PNPトランジスタのベース領域の不純
物濃度が低い場合には、エミツタ効率で決定され
る。従つてP型領域16が存在しない第5図の従
来例の場合におけるP型アノード領域54をエミ
ツタ、n型エピタキシヤル領域53をベース、P
型絶縁領域55をコレクタとした場合のPNPト
ランジスタのベース接地電流増幅率α0及びα1,α2
は同程度の値となる。従つてα0>α1×α2となり、
P型領域16を設けることにより、実効的に寄生
のPNPトランジスタのhFEを著しく低減すること
が出来、CB接合ダイオードのアノード電流から、
P型基板領域に流入する電流の割合を少くするこ
とが可能となる。 FIG. 2 shows an equivalent circuit constituted by the P-type anode region 14, the n-type epitaxial region 13, the P-type insulating region 15, and the P-type region 16 in the structure shown in FIG. P type anode region 14 is emitter, n type epitaxial region 13 is base, P
The common base current amplification factor of a PNP transistor configured with the type region 16 as the collector is α 1 , the P-type region 16 is the emitter, and the n-type epitaxial region 13
Assuming that the base-grounded current amplification factor of a PNP transistor configured with the base and the P-type insulating region 15 as the emitter is α 2 , a current that is α 1 × α 2 times the current injected into the anode flows into the P-type insulating region. It turns out. The common base current amplification factor has a value smaller than 1, and is determined by the emitter efficiency when the impurity concentration in the base region of the parasitic PNP transistor is low. Therefore, in the case of the conventional example shown in FIG. 5 in which the P-type region 16 does not exist, the P-type anode region 54 is used as the emitter, the n-type epitaxial region 53 is used as the base, and the P-type anode region 54 is used as the base.
Common base current amplification factors α 0 , α 1 , α 2 of the PNP transistor when the type insulating region 55 is used as the collector
have similar values. Therefore, α 0 > α 1 × α 2 ,
By providing the P-type region 16, it is possible to effectively significantly reduce the hFE of the parasitic PNP transistor, and from the anode current of the CB junction diode,
It becomes possible to reduce the proportion of current flowing into the P-type substrate region.
以上説明したように本発明は、P型基板上に高
濃度n型埋込み領域とn型エピタキシヤル領域と
を形成してカソード領域とし、n型エピタキシヤ
ル領域の表面に形成されたP型領域をアノード領
域とし、カソード領域の周囲がP型絶縁領域で囲
まれたダイオード構造において、アノード領域と
P型絶縁領域の間に、アノード領域を囲む形で不
純物を設けることにより、アノード領域をエミツ
タ、カソード領域をベース、P型絶縁領域をコレ
クタとする寄生PNPトランジスタのhFEを十分に
低くすることが出来、ダイオードアノード電流の
P型基板への流出に伴う消費電力の浪費、及びラ
ツチアツプ等の異常動作を防ぐ効果がある。
As explained above, the present invention forms a high concentration n-type buried region and an n-type epitaxial region on a P-type substrate to form a cathode region, and a P-type region formed on the surface of the n-type epitaxial region. In a diode structure in which the anode region is an anode region and the cathode region is surrounded by a P-type insulating region, impurities are provided between the anode region and the P-type insulating region in a manner surrounding the anode region. The h FE of the parasitic PNP transistor, which has a P-type insulation region as a base and a P-type insulating region as a collector, can be made sufficiently low, thereby eliminating wasted power consumption due to diode anode current flowing to the P-type substrate, and abnormal operations such as latch-up. It has the effect of preventing
第1図は本発明の第1の実施例を示す断面図、
第2図は第1図の構造における寄生PNPトラン
ジスタを示す等価回路図、第3図は本発明を説明
するための従来技術に対する改良例を示す断面
図、第4図は従来の第1の種類のダイオードを示
す等価回路図、第5図は従来の第2の種類のダイ
オードを示す断面図を各々示す。
11,31,51……P型基板、12,32,
52……高濃度n型埋込み領域、13,33,5
3……n型エピタキシヤル領域、14,34,5
4……P型アノード領域、15,35,55……
P型絶縁領域、16……P型領域、36……高濃
度n型領域、17,37,57……絶縁膜、1
8,38,58……アノード電極、19,39,
59……カソード電極。
FIG. 1 is a sectional view showing a first embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram showing a parasitic PNP transistor in the structure of FIG. 1, FIG. 3 is a cross-sectional view showing an example of improvement over the prior art for explaining the present invention, and FIG. 4 is a conventional first type. FIG. 5 is an equivalent circuit diagram showing a diode of this type, and FIG. 5 is a cross-sectional view showing a conventional second type diode. 11, 31, 51...P type substrate, 12, 32,
52...High concentration n-type buried region, 13, 33, 5
3...n-type epitaxial region, 14, 34, 5
4...P-type anode region, 15, 35, 55...
P-type insulating region, 16... P-type region, 36... High concentration n-type region, 17, 37, 57... Insulating film, 1
8,38,58...Anode electrode, 19,39,
59...Cathode electrode.
Claims (1)
該基板上に成長したN型エピタキシヤル領域とを
カソード領域とし、該N型エピタキシヤル領域表
面部分に形成されたP型領域をアノード領域と
し、該カソード領域の周囲がP型絶縁領域で囲ま
れた構造を有する半導体集積回路において、該ア
ノード領域と該P型絶縁領域との間に該アノード
領域を囲み電気的に浮遊状態にあるP型不純物領
域を設けたことを特徴とする半導体集積回路。1 The high concentration N-type buried region formed on the P-type substrate and the N-type epitaxial region grown on the substrate are used as the cathode region, and the P-type region formed on the surface portion of the N-type epitaxial region is used as the anode. In a semiconductor integrated circuit having a structure in which the cathode region is surrounded by a P-type insulating region, the anode region is surrounded by an electrically floating state between the anode region and the P-type insulating region. A semiconductor integrated circuit characterized in that a P-type impurity region is provided.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25021785A JPS62109353A (en) | 1985-11-07 | 1985-11-07 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25021785A JPS62109353A (en) | 1985-11-07 | 1985-11-07 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62109353A JPS62109353A (en) | 1987-05-20 |
JPH0577190B2 true JPH0577190B2 (en) | 1993-10-26 |
Family
ID=17204569
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25021785A Granted JPS62109353A (en) | 1985-11-07 | 1985-11-07 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62109353A (en) |
-
1985
- 1985-11-07 JP JP25021785A patent/JPS62109353A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS62109353A (en) | 1987-05-20 |
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