JPH0222545B2 - - Google Patents
Info
- Publication number
- JPH0222545B2 JPH0222545B2 JP55107288A JP10728880A JPH0222545B2 JP H0222545 B2 JPH0222545 B2 JP H0222545B2 JP 55107288 A JP55107288 A JP 55107288A JP 10728880 A JP10728880 A JP 10728880A JP H0222545 B2 JPH0222545 B2 JP H0222545B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- region
- emitter
- collector
- base region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 238000002513 implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特にIIL
（Integrated Injection Logic；集積注入論理回
路）素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly an IIL
(Integrated Injection Logic) devices.
IILはキヤリア注入素子として横方向PNPトラ
ンジスタとキヤリア増幅素子としての縦方向逆動
作NPNトランジスタが一体となり、しかもPNP
インジエクタ用トランジスタのコレクタとNPN
増幅インバータ用トランジスタのベースが共通に
形成されている。このIILはリニア回路の通常の
接合分離トランジスタより小さくできること、
IIL回路は他の論理回路形式より簡単であること
等の優れた特長がある。 The IIL is a combination of a horizontal PNP transistor as a carrier injection element and a vertical reverse-operating NPN transistor as a carrier amplification element.
Injector transistor collector and NPN
The bases of the amplifier inverter transistors are formed in common. This IIL can be smaller than a normal junction-isolated transistor in a linear circuit;
IIL circuits have superior features such as being simpler than other logic circuit formats.
従来のIILの基本インバータ（マルチコレク
タ・インバータ）の構造例を第１図（平面図）及
び第２図（断面図）に示す。両図において、１は
インジエクタ・トランジスタ（横方向PNPトラ
ンジスタ）のエミツタ領域、２はインジエクタ・
トランジスタのコレクタ領域であるとともにイン
バータ・トランジスタ（縦方向逆動作NPNトラ
ンジスタ）の共通ベース領域、３はインバータ・
トランジスタのコレクタ領域、４はインバータ・
トランジスタのＮ形エミツタ領域、５はインバー
タ・トランジスタの高濃度Ｎ形のエミツタ電極接
続（エミツタ・コンタクト）部をそれぞれ示す。
そしてこれらの各領域はＰ形半導体基板７上のＮ
形エピタキシヤル層８に形成される。また、１４
はＮ形高濃度埋込層である。また、両図から分る
ように、IILのNPNトランジスタの各コレクタ領
域３は共通ベース領域２に囲まれたマルチコレク
タ構造になつていて、ベース端子は１個である。
なお、両図において表面を被覆する絶縁膜及い電
極ないし配線は省略してある。 Examples of the structure of a conventional IIL basic inverter (multi-collector inverter) are shown in FIG. 1 (plan view) and FIG. 2 (cross-sectional view). In both figures, 1 is the emitter region of the injector transistor (lateral PNP transistor), and 2 is the injector transistor.
3 is the collector region of the transistor and the common base region of the inverter transistor (vertical reverse operation NPN transistor).
The collector area of the transistor, 4 is the inverter.
The N-type emitter region of the transistor, and 5 indicate the highly doped N-type emitter electrode connection (emitter contact) portion of the inverter transistor.
Each of these regions is N on the P-type semiconductor substrate 7.
A shaped epitaxial layer 8 is formed. Also, 14
is an N-type high concentration buried layer. Further, as can be seen from both figures, each collector region 3 of the IIL NPN transistor has a multi-collector structure surrounded by a common base region 2, and has one base terminal.
Note that in both figures, an insulating film covering the surface, electrodes, and wiring are omitted.
ここで、IILのもう一つの特長として、前記第
１図及び第２図に示すように、Ｎ形エピタキシヤ
ル層８をＰ形分離領域１３で分離して、NPNバ
イポーラ・トランジスタ（ベース領域９、エミツ
タ領域１０、コレクタ領域１１、Ｎ形コレクタ電
極接続（コレクタ・コンタクト）部１２及びＮ形
高濃度埋込層１５で構成されている）を同一基板
上に共存させることができる。 Another feature of IIL is that, as shown in FIGS. 1 and 2, the N-type epitaxial layer 8 is separated by the P-type isolation region 13 to form an NPN bipolar transistor (base region 9, (composed of an emitter region 10, a collector region 11, an N-type collector electrode connection (collector contact) portion 12, and an N-type high concentration buried layer 15) can coexist on the same substrate.
しかし、このような構造にした場合、IILでは、
逆動作トランジスタのベース領域２の不純物濃度
がエミツタ領域４より高濃度である為、エミツタ
の注入効率が低くなる。これを改善する為、Ｎ形
不純物の高濃度埋込層１４をベース領域２に近づ
けて形成すると、同時に形成されるバイポーラ・
トランジスタ側の高濃度埋込層１５もベース領域
９に近づくことになる。従つて、バイポーラ・ト
ランジスタの耐圧が小さくなり、従来は使用電源
電圧範囲が７〜9V程度までに限られていた。し
たがつて、このままではリニア混載IILの適用範
囲が狭くなつてしまうので、高耐圧化の為に種々
の工夫がなされている。たとえば、第３図の様
に、IIL素子側に選択的に厚い高濃度埋込層１
４′を設ければ、バイポーラ・トランジスタの耐
圧を下げないで逆動作NPNトランジスタのエミ
ツタ注入効率を上げることができる。しかし、こ
れでは、製造工程の増加をまぬがれない。 However, with this structure, in IIL,
Since the impurity concentration in the base region 2 of the reverse operation transistor is higher than that in the emitter region 4, the emitter injection efficiency becomes low. In order to improve this, if the buried layer 14 with a high concentration of N-type impurity is formed close to the base region 2, the bipolar layer 14 formed at the same time
High concentration buried layer 15 on the transistor side also approaches base region 9. Therefore, the withstand voltage of the bipolar transistor becomes small, and the power supply voltage range used heretofore has been limited to approximately 7 to 9V. Therefore, if things continue as they are, the scope of application of linear mixed IIL will be narrowed, so various efforts have been made to increase the withstand voltage. For example, as shown in Figure 3, there is a selectively thick high concentration buried layer 1 on the IIL element side.
By providing 4', it is possible to increase the emitter injection efficiency of the reverse operation NPN transistor without lowering the withstand voltage of the bipolar transistor. However, this does not avoid increasing the manufacturing process.
本発明は、これら従来構造の欠点を解決するも
ので、何ら製造工程を増加させることなく逆動作
トランジスタのエミツタ注入効率を上げることを
目的とする。 The present invention solves these drawbacks of the conventional structure, and aims to increase the emitter injection efficiency of a reverse operation transistor without increasing the number of manufacturing steps.
以下、実施例に基づき本発明を詳細に説明す
る。 Hereinafter, the present invention will be explained in detail based on Examples.
第４図及び第５図はそれぞれ本発明の一実施例
を示す平面図及び断面図である。各部の符号は第
１図ないし第２図と共通であるので同様に理解す
ることができる。上記の目的を達成する為に、本
実施例では、Ｎ型不純物の高濃度エミツタ領域６
を基板表面に設け、しかも、ベース領域２の一部
で重なる様に形成し、横方向トランジスタ構造に
したことを特徴とする。 FIGS. 4 and 5 are a plan view and a sectional view, respectively, showing an embodiment of the present invention. Since the reference numerals of each part are the same as those in FIGS. 1 and 2, they can be understood in the same way. In order to achieve the above object, in this embodiment, the emitter region 6 with high concentration of N-type impurity
is provided on the surface of the substrate, and is formed so as to partially overlap with the base region 2, resulting in a lateral transistor structure.
従来は高濃度埋込層１４からの縦方向の注入が
主であつたが、上記構造では、高濃度埋込層１４
を介さないで、前記高濃度エミツタ領域６からの
直接の注入が主となつている。したがつて、高濃
度埋込層１４をベース領域２から遠ざけることが
できる為、共存するバイポーラ・トランジスタの
耐圧を下げることなく、トランジスタのエミツタ
効率を下げることができる。 Conventionally, injection was mainly performed in the vertical direction from the heavily doped buried layer 14, but in the above structure, the heavily doped buried layer 14
Direct injection from the high concentration emitter region 6 is the main method. Therefore, since the heavily doped buried layer 14 can be moved away from the base region 2, the emitter efficiency of the transistor can be lowered without lowering the withstand voltage of the coexisting bipolar transistor.
本発明による他の実施例として第６図及び第７
図にそれぞれ平面図及び断面図を示す。なお、両
図においてバイポーラ・トランジスタ側は省略し
てあるが、前記第４図及び第５図と同様の構造に
なる。本実施例では、エミツタ領域６がコレクタ
領域３の全周をおおつている為、コレクタ領域の
周縁の全域が有効に働き、さらに、エミツタ効率
を上げることができる。 6 and 7 as other embodiments according to the present invention.
The figures show a plan view and a sectional view, respectively. Although the bipolar transistor side is omitted in both figures, the structure is similar to that of FIGS. 4 and 5. In this embodiment, since the emitter region 6 covers the entire circumference of the collector region 3, the entire periphery of the collector region works effectively, further increasing the emitter efficiency.
又、本発明による更に他の実施例として、共存
するバイポーラトランジスタの耐圧が高く要求さ
れない場合には、第８図の様に、高濃度埋込層４
をベース領域２に近づけることにより、領域５か
らの注入に、領域４からの注入が加わり、さらに
エミツタ効率を上げることができる。 Furthermore, as a further embodiment of the present invention, when the coexisting bipolar transistors are not required to have a high breakdown voltage, as shown in FIG.
By bringing the region closer to the base region 2, the implantation from the region 4 is added to the implantation from the region 5, and the emitter efficiency can be further increased.
なお、上記各実施例においては、特定の極性形
の場合に基づいて説明したが、本発明をそれらと
逆の極性形の場合に適用できることは明白であ
る。 Although each of the above embodiments has been explained based on the case of a specific polarity type, it is obvious that the present invention can be applied to cases of the opposite polarity type.
以上詳細に説明したように、本発明によれば、
共存するバイポーラ・トランジスタの耐圧を下げ
ないで、トランジスタのエミツタ効率を上げるこ
とができる。又、従来のプロセスを何ら変更する
ことなく本発明を実施することができる。 As explained in detail above, according to the present invention,
It is possible to increase the emitter efficiency of the transistor without lowering the withstand voltage of the coexisting bipolar transistor. Furthermore, the present invention can be practiced without any changes to conventional processes.
第１図及び第２図はそれぞれ従来装置の一例を
示す平面図及び断面図、第３図は従来装置の他の
例を示す断面図、第４図及び第５図はそれぞれ本
発明装置の一実施例を示す平面図及び断面図、第
６図及び第７図はそれぞれ本発明装置の他の実施
例を示す平面図及び断面図、第８図は本発明装置
の更に他の実施例を示す断面図である。
１……インジエクタ・トランジスタのエミツタ
領域、２……インジエクタ・トランジスタのコレ
クタ領域であるとともにインバータ・トランジス
タの共通ベース領域、３……インバータ・トラン
ジスタのコレクタ領域、４……インバータ・トラ
ンジスタのエミツタ領域、５……インバータ・ト
ランジスタのエミツタ電極接続（エミツタコンタ
クト）部、６……インバータ・トランジスタの高
濃度エミツタ領域、７……半導体基板、８……エ
ピタキシヤル層、９……バイポーラ・トランジス
タのベース領域、１０……バイポーラ・トランジ
スタのエミツタ領域、１１……バイポーラ・トラ
ンジスタのコレクタ領域、１２……バイポーラ・
トランジスタのコレクタ電極接続（コレクタコン
タクト）部、１３……分離領域、１４，１４′，
１５……高濃度埋込層。
1 and 2 are a plan view and a sectional view showing an example of a conventional device, respectively, FIG. 3 is a sectional view showing another example of a conventional device, and FIGS. A plan view and a sectional view showing an embodiment, FIGS. 6 and 7 are a plan view and a sectional view showing another embodiment of the device of the present invention, and FIG. 8 shows still another embodiment of the device of the present invention. FIG. 1... Emitter region of the injector transistor, 2... Collector region of the injector transistor and common base region of the inverter transistor, 3... Collector region of the inverter transistor, 4... Emitter region of the inverter transistor, 5... Emitter electrode connection (emitter contact) part of inverter transistor, 6... High concentration emitter region of inverter transistor, 7... Semiconductor substrate, 8... Epitaxial layer, 9... Base of bipolar transistor region, 10... emitter region of bipolar transistor, 11... collector region of bipolar transistor, 12... bipolar transistor;
Collector electrode connection (collector contact) portion of transistor, 13... Separation region, 14, 14',
15...High concentration buried layer.
Claims (1)
イポーラ・トランジスタを備え、前記集積注入論
理回路のインバータを構成する縦型逆トランジス
タがマルチコレクタを有する半導体集積回路装置
において、前記縦型逆トランジスタのベース領域
のインジエクタとは反対側にベース領域と一部重
なるように前記基板表面に高不純物濃度のエミツ
タ領域を設け、前記エミツタ領域並びに前記縦型
逆トランジスタのベース領域およびコレクタ領域
により横型トランジスタを構成することを特徴と
する半導体集積回路装置。1. In a semiconductor integrated circuit device comprising an integrated injection logic circuit and a bipolar transistor on the same semiconductor substrate, and in which a vertical inverse transistor constituting an inverter of the integrated injection logic circuit has a multi-collector, a base region of the vertical inverse transistor is An emitter region with a high impurity concentration is provided on the surface of the substrate so as to partially overlap with the base region on the opposite side from the injector, and a lateral transistor is formed by the emitter region and the base region and collector region of the vertical inverse transistor. Features of semiconductor integrated circuit devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10728880A JPS5732664A (en) | 1980-08-05 | 1980-08-05 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10728880A JPS5732664A (en) | 1980-08-05 | 1980-08-05 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5732664A JPS5732664A (en) | 1982-02-22 |
| JPH0222545B2 true JPH0222545B2 (en) | 1990-05-18 |
Family
ID=14455286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10728880A Granted JPS5732664A (en) | 1980-08-05 | 1980-08-05 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5732664A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH056617U (en) * | 1991-06-27 | 1993-01-29 | ナイルス部品株式会社 | Vehicle actuator control device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5784162A (en) * | 1980-11-13 | 1982-05-26 | Toshiba Corp | Semiconductor device |
-
1980
- 1980-08-05 JP JP10728880A patent/JPS5732664A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH056617U (en) * | 1991-06-27 | 1993-01-29 | ナイルス部品株式会社 | Vehicle actuator control device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5732664A (en) | 1982-02-22 |
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