JPH056672Y2 - - Google Patents
Info
- Publication number
- JPH056672Y2 JPH056672Y2 JP1986113290U JP11329086U JPH056672Y2 JP H056672 Y2 JPH056672 Y2 JP H056672Y2 JP 1986113290 U JP1986113290 U JP 1986113290U JP 11329086 U JP11329086 U JP 11329086U JP H056672 Y2 JPH056672 Y2 JP H056672Y2
- Authority
- JP
- Japan
- Prior art keywords
- surge
- surge absorbing
- terminal
- protected
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000010521 absorption reaction Methods 0.000 claims description 8
- 230000002457 bidirectional effect Effects 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000001629 suppression Effects 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Emergency Protection Circuit Devices (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は、ICカード或いは他の装置に実装さ
れる集積回路（IC）を保護するのに好適なサー
ジ吸収用半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a surge absorbing semiconductor device suitable for protecting an integrated circuit (IC) mounted on an IC card or other device.
従来、サージ吸収用防護素子としては種々な文
献から知られているように、避***（例えば、黒
沢、上條、根岸：通信用ガス入避***、日本電信
電話公社電気通信研究所研究実用化報告、
vol.30，No.５，p.1229〜1242，1981）、酸化亜鉛
バリスタ、ツエナーダイオード、アバランシエダ
イオード、ダイオードバリスタ（平岡、佐野、金
森：サージ防護用半導体素子、日本電信電話公
社、電気通信研究所研究実用化報告、vol.30，No.
５，p.1257〜1267，1981）などがある。
Conventionally, as a surge absorbing protective element, as known from various documents, there are detonators (for example, Kurosawa, Kamijo, Negishi: Gas entry detonator for communication, Nippon Telegraph and Telephone Public Corporation Telecommunication Research Institute Research and Practical Application Report). ,
vol.30, No.5, p.1229-1242, 1981), zinc oxide varistor, Zener diode, avalanche diode, diode varistor (Hiraoka, Sano, Kanamori: Semiconductor device for surge protection, Nippon Telegraph and Telephone Public Corporation, Telecommunications Laboratory research practical application report, vol.30, No.
5, p.1257-1267, 1981).
避***は電極間のギヤツプの距離、封入ガス圧
力などを調整することにより、そのサージ抑圧電
圧の大きさが決められる。 The magnitude of the surge suppression voltage of a detonator is determined by adjusting the gap distance between the electrodes, the pressure of the sealed gas, etc.
酸化亜鉛バリスタがその厚さなどを調整するこ
とにより、そのサージ抑圧電圧の大きさが決めら
れる。 By adjusting the thickness of the zinc oxide varistor, the magnitude of its surge suppression voltage is determined.
ダイオードバリスタはシリコンのバルク内に形
成される１個のPN接合の順方向特性を利用する
ものであり、１個のPN接合の１次ブレークダウ
ン電圧が約0.8V程度であるので、サージ抑圧電
圧の調整はPN接合の多層化により実現できる。 A diode varistor utilizes the forward characteristics of a single PN junction formed in the bulk of silicon, and the primary breakdown voltage of a single PN junction is approximately 0.8V, so the surge suppression voltage This adjustment can be achieved by multilayering PN junctions.
ツエナーダイオード、アバランシエダイオード
等では、PN接合近傍の不純物濃度勾配の調整に
よつて所要の１次ブレークダウン電圧を実現でき
る。 In Zener diodes, avalanche diodes, etc., the required primary breakdown voltage can be achieved by adjusting the impurity concentration gradient near the PN junction.
ところで、例えばICカードに搭載するための
防護素子に要求される主な電気的特性は１次ブレ
ークダウン電圧が６〜7V、しかも正極性、負極
性のいずれのサージに対しても確実に動作する双
方向特性を有していること、また静電容量は制御
信号に対し十分に小さい値であることなどであ
る。斯かる従来のサージ吸収用半導体装置として
第３図に示すようなものがある。これは設定サー
ジ抑圧電圧を有する４組の一対のサージ吸収素子
D1とD5、D2とD6、D3とD7、D4とD8を夫々背中
合せにして直列接続したものを、保護すべきIC
の接地端子のような基準端子に接続される第１の
端子Ａと前記ICの被保護端子に夫々接続される
複数の第２の端子Ｂ，Ｃ，Ｄ，Ｅ間に接続した形
になつている。 By the way, the main electrical characteristics required for a protective element to be mounted on an IC card, for example, are a primary breakdown voltage of 6 to 7V, and the ability to operate reliably against both positive and negative polarity surges. It must have bidirectional characteristics, and its capacitance must be sufficiently small with respect to the control signal. Such a conventional surge absorbing semiconductor device is shown in FIG. 3. This consists of four pairs of surge absorbing elements each having a set surge suppression voltage.
The IC to be protected is the series connection of D 1 and D 5 , D 2 and D 6 , D 3 and D 7 , and D 4 and D 8 back to back.
A first terminal A is connected to a reference terminal such as a ground terminal of the IC, and a plurality of second terminals B, C, D, and E are connected to protected terminals of the IC. There is.
第３図に示すサージ吸収用半導体装置の場合、
第１の端子Ａと第２の端子Ｂ〜Ｅ間の夫々の双方
向のサージ抑圧電圧をすべく等しくするために
は、８個のサージ吸収素子D1〜D8の特性をすべ
く等しく揃えねばならず、また個別のサージ吸収
素子が必要な場合には８個のサージ吸収素子を必
要とし、同一の半導体基板に形成する場合にもサ
ージ吸収素子８個分の半導体領域が必要になるの
で小型化できない。
In the case of the surge absorbing semiconductor device shown in FIG.
In order to equalize the bidirectional surge suppression voltages between the first terminal A and the second terminals B to E, the characteristics of the eight surge absorbing elements D 1 to D 8 should be made equal to each other. In addition, if individual surge absorbing elements are required, eight surge absorbing elements are required, and even if they are formed on the same semiconductor substrate, a semiconductor area equivalent to eight surge absorbing elements is required. Cannot be downsized.
従つてこの考案に係るサージ吸収用半導体装置
は、サージ吸収素子を背中合わせに接続すること
により双方向のサージ抑圧電圧をもつ半導体装置
であつて、保護すべき集積回路の基準端子に接続
される第１の端子に電気的に結合されたサージ吸
収素子を共通として備えると共に、前記集積回路
の複数の被保護端子に夫々接続される複数の第２
の端子に夫々電気的に結合されるサージ吸収素子
を備えている。
Therefore, the surge absorbing semiconductor device according to the present invention is a semiconductor device that has a bidirectional surge suppression voltage by connecting surge absorbing elements back to back, and has a surge absorbing element connected to a reference terminal of an integrated circuit to be protected. a plurality of second surge absorbing elements electrically coupled to one terminal, and a plurality of second surge absorption elements each connected to a plurality of protected terminals of the integrated circuit
A surge absorbing element is electrically coupled to each terminal of the terminal.
この考案によれば、保護すべき集積回路の基準
端子に接続される第１の端子に電気的に結合され
るサージ吸収素子を共通としているので、従来に
比べ必要とするサージ吸収素子の数が少なくて済
み、従つて第１の端子と複数の第２の端子間の
夫々のブレークダウン電圧を等しくし易く、また
半導体装置を小型化でき、経済性も向上できる。
According to this invention, since the surge absorbing elements electrically coupled to the first terminal connected to the reference terminal of the integrated circuit to be protected are common, the number of required surge absorbing elements is reduced compared to the conventional method. Therefore, it is easy to equalize the breakdown voltages between the first terminal and the plurality of second terminals, and the semiconductor device can be downsized and economic efficiency can be improved.
第１図により本考案の一実施例を説明すると、
従来と異なる点は、保護される集積回路の被保護
端子（図示せず）にボンデングなどにより接続さ
れる第２の端子Ｂ，Ｃ，Ｄ，Ｅの夫々に一方の端
子が電気的に結合されるサージ吸収素子D1，D2，
D3，D4の他端が共通点Ｎに接続され、その共通
点Ｎと保護される集積回路の接地端子のような基
準端子（図示せず）に接続される第１の端子Ａと
の間に共通のサージ吸収素子D5が備えられてい
るところにある。
An embodiment of the present invention will be explained with reference to FIG.
The difference from the conventional method is that one terminal is electrically coupled to each of the second terminals B, C, D, and E, which are connected to the protected terminal (not shown) of the integrated circuit to be protected by bonding or the like. surge absorption elements D 1 , D 2 ,
The other ends of D 3 , D 4 are connected to a common point N, and the common point N is connected to a first terminal A, which is connected to a reference terminal (not shown), such as a ground terminal of the integrated circuit to be protected. A common surge absorbing element D5 is provided between them.
斯かるサージ吸収半導体装置では、第１の端子
Ａに対し第２の端子Ｂ〜Ｅのいずれかが正となる
ようなサージ電圧の生じた場合、そのサージ電圧
はサージ吸収素子D5のアバランシエブレークダ
ウン電圧のようなサージ抑圧電圧とサージ吸収素
子D1〜D4の相当するものの順方向ドロツプとの
和に等しい電圧に制限される。ここでサージ吸収
素子D1〜D4の順方向ドロツプは等しいので、第
１の端子Ａに対し第２の端子Ｂ〜Ｅを正とするサ
ージ電圧はサージ吸収素子D5のサージ抑圧電圧
で一義的に決定される。従つて、第１の端子Ａに
関して第２の端子Ｂ〜Ｅが正となる帯電々圧など
についてはすべて等しいサージ抑圧電圧に制限で
きる。 In such a surge absorbing semiconductor device, when a surge voltage occurs such that one of the second terminals B to E is positive with respect to the first terminal A, the surge voltage is caused by the avalanche of the surge absorbing element D5 . It is limited to a voltage equal to the sum of the surge suppression voltage, such as the breakdown voltage, and the forward drop of the corresponding surge absorbing elements D1 - D4 . Here, since the forward drops of the surge absorbing elements D1 to D4 are equal, the surge voltage that makes the second terminals B to E positive with respect to the first terminal A is uniquely determined by the surge suppression voltage of the surge absorbing element D5 . determined. Therefore, the charging voltages and the like that are positive at the second terminals B to E with respect to the first terminal A can all be limited to the same surge suppression voltage.
そしてこのようなサージ吸収素子を１チツプで
製作した場合の一実施例としては第２図Ａ，Ｂに
示すようなものがある。同図において、１は厚さ
が400μm程度以下のＮ導電型のシリコン半導体基
板、２ａ，２ｂ，２ｃ，２ｄ，２ｅは比較的不純
物濃度の高いＰ導電型の半導体領域、３ａ，３
ｂ，３ｃ，３ｄ，３ｅはそれぞれ対応するＰ導電
型の半導体領域２ａ〜２ｅとオーミツクコンタク
トを形成し、絶縁膜４上まで延在する電極であ
る。ここで電極３ａは第１の端子Ａに接続され、
また電極３ａ〜３ｅは夫々対応する第２の端子Ｂ
〜Ｅに接続される。 An example of such a surge absorbing element manufactured in one chip is shown in FIGS. 2A and 2B. In the figure, 1 is an N conductivity type silicon semiconductor substrate with a thickness of about 400 μm or less, 2a, 2b, 2c, 2d, and 2e are P conductivity type semiconductor regions with relatively high impurity concentration, and 3a, 3
Reference numerals b, 3c, 3d, and 3e are electrodes that form ohmic contact with the corresponding P conductivity type semiconductor regions 2a to 2e, and extend to the top of the insulating film 4. Here, the electrode 3a is connected to the first terminal A,
Further, the electrodes 3a to 3e are connected to the corresponding second terminal B.
~ Connected to E.
そしてこの実施例の１つの特徴は、保護される
ICの基準端子に電気的に結合される電極３ａと
オーミツクコンタクトで結合される半導体領域２
ａを中心にして、ICの被保護端子に接続される
端子Ｂ〜Ｃに夫々結合される半導体領域２ａ〜２
ｅを半導体領域２ａからほぼ等しい距離に配置し
たところにある。このような構成にすることによ
り、ICの被保護端子に接続されるサージ吸収素
子がすべてほぼ等しい特性をもつよう形成するこ
とが出来る。 And one feature of this embodiment is that it is protected
Semiconductor region 2 coupled by ohmic contact with electrode 3a electrically coupled to the reference terminal of the IC
Semiconductor regions 2a to 2 are connected to terminals B to C connected to protected terminals of the IC, respectively, with center a.
e are arranged at approximately equal distances from the semiconductor region 2a. With this configuration, all the surge absorbing elements connected to the protected terminals of the IC can be formed to have substantially the same characteristics.
なお、これら実施例において、Ｐ導電型とＮ導
電型とを入れ換えてもよく、またICの被保護端
子の数に合わせてサージ吸収素子の数を調整して
も勿論よい。 In these embodiments, the P conductivity type and the N conductivity type may be interchanged, and the number of surge absorbing elements may of course be adjusted according to the number of protected terminals of the IC.
以上述べたように本考案によれば、保護すべき
ICの基準端子に接続される第１の端子側に位置
するサージ吸収素子を共通としているので、IC
の被保護端子の電圧をすべく等しいサージ抑圧電
圧以下に制限することが出来、しかもサージ吸収
用半導体装置を小型化できると同時に経済性を向
上出来るなど実用上の効果は大きい。
As mentioned above, according to the present invention, the
Since the surge absorption element located on the first terminal side connected to the reference terminal of the IC is common, the IC
This has great practical effects, such as being able to limit the voltage at the protected terminal to a voltage equal to or less than the same surge suppression voltage, and also being able to downsize the surge absorbing semiconductor device and improve economic efficiency.
第１図及び第２図は夫々本考案の一実施例を示
す図であり、第２図Ａは平面を示す図、ＢはＡに
おける−′での断面を示す図、第３図は従来
例を示す図である。
D1〜D8……サージ吸収素子、Ａ……第１の端
子、Ｂ〜Ｅ……第２の端子、１……半導体基板、
２ａ〜２ｅ……半導体領域、３ａ〜３ｅ……電
極、４……絶縁膜。
1 and 2 are views showing one embodiment of the present invention, respectively. FIG. 2 A is a plan view, B is a cross-sectional view taken at -' in A, and FIG. 3 is a conventional example. FIG. D1 to D8 ...Surge absorption element, A...First terminal, B to E...Second terminal, 1...Semiconductor substrate,
2a to 2e... semiconductor region, 3a to 3e... electrode, 4... insulating film.
Claims (1)
より双方向のサージ吸収機能を有する半導体装置
において、保護すべき対象の基準端子に接続され
るべき第１の電極に電気的に結合された第１のサ
ージ吸収素子を共通として備えると共に、前記保
護すべき対象の複数の被保護端子に夫々接続され
るべき複数の第２の電極の対応するものに電気的
に結合される複数の第２のサージ吸収素子を前記
第１のサージ吸収素子の周りでこれに対しほぼ等
しく離れた位置に備え、共通の前記第１のサージ
吸収素子と複数の前記第２のサージ吸収素子とが
背中合わせになるように形成したことを特徴とす
るサージ吸収用半導体装置。 In a semiconductor device having a bidirectional surge absorption function by coupling surge absorption elements back to back, a first surge absorption element electrically coupled to a first electrode to be connected to a reference terminal of an object to be protected; A plurality of second surge absorbing elements are provided in common and are electrically coupled to corresponding ones of the plurality of second electrodes to be respectively connected to the plurality of protected terminals of the object to be protected. A common surge absorbing element and a plurality of second surge absorbing elements are provided at positions approximately equally spaced around the first surge absorbing element and are formed back to back. A surge absorption semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986113290U JPH056672Y2 (en) | 1986-07-23 | 1986-07-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986113290U JPH056672Y2 (en) | 1986-07-23 | 1986-07-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6320457U JPS6320457U (en) | 1988-02-10 |
| JPH056672Y2 true JPH056672Y2 (en) | 1993-02-19 |
Family
ID=30994954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986113290U Expired - Lifetime JPH056672Y2 (en) | 1986-07-23 | 1986-07-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH056672Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0783941B2 (en) * | 1991-12-24 | 1995-09-13 | 正 小栗 | Square pipe for steel construction or U-shaped cutting jig for column materials |
| JP6393587B2 (en) * | 2014-03-05 | 2018-09-19 | ローム株式会社 | Bidirectional Zener diode |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57154878A (en) * | 1981-03-20 | 1982-09-24 | Hitachi Ltd | Semiconductor sensor |
| JPS57154879A (en) * | 1981-02-04 | 1982-09-24 | Rca Corp | Semiconductor device |
| JPS614985B2 (en) * | 1978-02-20 | 1986-02-14 | Honda Motor Co Ltd | |
| JPS61173167A (en) * | 1985-01-28 | 1986-08-04 | Matsushita Electric Ind Co Ltd | Method for measuring resistance value of chip resistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS614985U (en) * | 1984-06-15 | 1986-01-13 | 株式会社 電制 | Composite display device |
-
1986
- 1986-07-23 JP JP1986113290U patent/JPH056672Y2/ja not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS614985B2 (en) * | 1978-02-20 | 1986-02-14 | Honda Motor Co Ltd | |
| JPS57154879A (en) * | 1981-02-04 | 1982-09-24 | Rca Corp | Semiconductor device |
| JPS57154878A (en) * | 1981-03-20 | 1982-09-24 | Hitachi Ltd | Semiconductor sensor |
| JPS61173167A (en) * | 1985-01-28 | 1986-08-04 | Matsushita Electric Ind Co Ltd | Method for measuring resistance value of chip resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6320457U (en) | 1988-02-10 |
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