JPS6132561A - Electrostatic breakdown preventive element - Google Patents
Electrostatic breakdown preventive elementInfo
- Publication number
- JPS6132561A JPS6132561A JP15495484A JP15495484A JPS6132561A JP S6132561 A JPS6132561 A JP S6132561A JP 15495484 A JP15495484 A JP 15495484A JP 15495484 A JP15495484 A JP 15495484A JP S6132561 A JPS6132561 A JP S6132561A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- region
- surge voltage
- electrostatic breakdown
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015556 catabolic process Effects 0.000 title claims abstract description 12
- 230000003449 preventive effect Effects 0.000 title abstract 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 230000002265 prevention Effects 0.000 claims description 13
- 230000006378 damage Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は静電破壊防止素子に係り、半導体集積回路にお
ける静電破壊を防止するための保護素子Ｋ１１ｌする。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an electrostatic damage prevention element, and is a protection element K11l for preventing electrostatic damage in a semiconductor integrated circuit.
。 .
（ロ）従来の技術
一般に、モノリシックバイポーラ集積回路装置は、ＮＰ
７Ｎ）ランジスタあるいはＰＮＰ）ランジスタのペース
、エミッタ、コレクタを入力側として直接集積回路の外
部に４取り出す場合、集積回路装置の静電破壊を防止す
るため保、膜素子が設けられている。例えば、第４図に
示すように、入力側に内部回路（１）と直列に保護素子
としての抵抗体（２）を接続し１、浮遊餐量（３）と抵
抗体（２）の時定数によりサージ電圧の波形を滑らかに
し、急激なサージ電圧が内部回路に入らないようにする
方法がある。(b) Conventional technology In general, monolithic bipolar integrated circuit devices are
When the pace, emitter, and collector of a 7N) transistor or PNP transistor are taken out directly to the outside of the integrated circuit as an input side, a protection film element is provided to prevent electrostatic damage to the integrated circuit device. For example, as shown in Figure 4, a resistor (2) as a protection element is connected in series with the internal circuit (1) on the input side, and the stray charge (3) and the time constant of the resistor (2) are There is a method to smooth the surge voltage waveform and prevent sudden surge voltage from entering the internal circuit.
しかしながら、この方法においては、接続する抵抗体（
２）の抵抗値が数十から数百オームでは完全な対策とは
いえず、抵抗値が数キラオーム以上必要である。ところ
が、回路上この位置に数キロオーム以上の抵抗体（２）
を設けると、パターン面積が大きくなるばかりか、通常
の入力信号の場合に、抵抗体（２）によって、減衰が生
じるため、トランジスタの動作点がずれたり回路定数が
変化するなど回路上支障をきたし好ましくない。また、
抵抗体（２）をＮ型半導体領域に形成したＰ型頭域で構
成した場合、Ｎ型半導体領域とＰ型頭域との間のＰＮ接
合に順方向にサージ電圧が加わると−きは破壊はしない
が、逆方向に大きいサージ電圧が加わったとき、ＰＮ接
合の耐圧以上の電圧であれば、抵抗体自体が破壊してし
１５゜そこで、半導体基板に擬似的に順方向動作するト
ランジスタ構造の素子を被保護回路の入力端子と並列に
接続し、順逆いずれの方向のサージ電圧が入っても、上
記素子が破壊することなくトランジスタとして動作させ
てサージ電圧を吸収するように構成した静電破壊防止素
子がある（特公昭５３−２１８３８号公報に詳しい。）
。However, in this method, the connected resistor (
2) A resistance value of several tens to hundreds of ohms is not a perfect countermeasure, and a resistance value of several kiloohms or more is required. However, there is a resistor (2) of several kiloohms or more at this position on the circuit.
Not only does this increase the pattern area, but also causes attenuation due to the resistor (2) in the case of a normal input signal, causing circuit problems such as shifting the operating point of the transistor and changing circuit constants. Undesirable. Also,
If the resistor (2) is composed of a P-type head region formed in an N-type semiconductor region, it will be destroyed if a surge voltage is applied in the forward direction to the PN junction between the N-type semiconductor region and the P-type head region. However, when a large surge voltage is applied in the reverse direction, if the voltage exceeds the withstand voltage of the PN junction, the resistor itself will be destroyed. The electrostatic capacitor is connected in parallel with the input terminal of the circuit to be protected so that even if a surge voltage is applied in either the forward or reverse direction, the element operates as a transistor and absorbs the surge voltage without being destroyed. There is a destruction prevention element (details in Japanese Patent Publication No. 53-21838).
.
（ハ）発明が解決しようとする問題点
しかしながら、この素子においては、通常の場合におい
ても、入力信号がＮ型ドープ層内を経【回路の入力側に
送られるように構成されてドープ層の内部抵抗により電
圧降下が生じ、トランジスタの動作点がずれたり回路定
数が変化するなど回路上支障をきたすなどの問題があっ
た。(c) Problems to be Solved by the Invention However, in this device, even in normal cases, the input signal is sent to the input side of the circuit through the N-type doped layer. The internal resistance causes a voltage drop, causing problems in the circuit, such as shifting the operating point of the transistor and changing circuit constants.
に）問題点を解決するための手段
本発明は上述した問題点を解決するためになされたもの
で、半導体集積回路の入力側と外部端子との間に並列に
接続される静電破壊防止素子であって、前記静電破壊防
止素子は、Ｎ（又はＰ）型の半導体領域と、この半導体
領域に設けたＰ（又はＮ）型の第１領域および第２領域
と、この第１および第２領域間に絶縁層を介して跨る第
１電極および第２電極とを具備し、前記第１電極を第１
領域にオーミック接触して接続すると共に前記第２電極
を第２領域にオーミック接触して接続したことを特徴と
する。B) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and it provides an electrostatic breakdown prevention element connected in parallel between the input side of a semiconductor integrated circuit and an external terminal. The electrostatic breakdown prevention element includes an N (or P) type semiconductor region, a P (or N) type first region and a second region provided in this semiconductor region, and the first and second regions. A first electrode and a second electrode are provided that extend between two regions via an insulating layer, and the first electrode is connected to the first electrode.
The second electrode is connected to the second region by ohmic contact, and the second electrode is connected to the second region by ohmic contact.
（ホ）作用
本発明は外部端子を介して静電破壊防止素子の第１およ
び第２電極間にサージ電圧が加わった場合に、第１およ
び第２領域間の半導体領域表面に反転層が生成して、第
１および第２電極間が導通することにより、サージ電圧
を吸収する。(E) Function The present invention provides that when a surge voltage is applied between the first and second electrodes of an electrostatic breakdown prevention element via an external terminal, an inversion layer is generated on the surface of the semiconductor region between the first and second regions. As a result, the surge voltage is absorbed by conducting between the first and second electrodes.
（へ）実施例
以下本発明の一実施例を第１図ないし第３図に従い説明
する。第１図は上面図、第２図は第１図の■−■線断面
図、第３図は入力回路図である。(f) Example An example of the present invention will be described below with reference to FIGS. 1 to 3. FIG. 1 is a top view, FIG. 2 is a sectional view taken along the line ■--■ in FIG. 1, and FIG. 3 is an input circuit diagram.
Ｐ型のシリコン半導体基板ＱＯ上にＮ−型のエピタキシ
ャル層Ｑｌ）が形成され、このエピタキシャル層（１１
）をＰ＋型の分離領域α４で島状に分離して島領域Ｑ３
）が形成される。この島領域α漕が半導体領域α説とし
て働く。この半導体領域（１３の表面ＫＰ型の第１領域
（１４）および第２領域ａ９が、他の島領域に形成され
る′ＮＰＮトランジスタのベース領域の形成と′同時に
形成される。An N-type epitaxial layer Ql) is formed on a P-type silicon semiconductor substrate QO, and this epitaxial layer (11
) is separated into islands by P+ type separation region α4 to form island region Q3.
) is formed. This island region α column works as the semiconductor region α theory. The surface KP type first region (14) and second region a9 of this semiconductor region (13) are formed at the same time as the base region of the NPN transistor formed in the other island region.
エピタキシャル層α］）表面には酸化シリコンなどから
なる絶縁層（１１が設けられ、この絶縁層（１６１上に
第１領域α４）および第２領域ａ９間を跨いで第１電極
Ｏｎおよび第２電極ａ枠がアルミ蒸着などにより設けら
れる。そして第１電極ａηは絶縁層−に設けたコンタク
トホールを介して第１領域ｔ１４にオーミック接触して
接続され、第２電極傷賠家同じくコンタクトホールを介
して第２領域（Ｉωにオーミック接触して接続されてい
る。また第１電極αη、第２電極賭は夫々外部端子と内
部回路との間に接続され、第３図に示すように内部回路
（１）と外部端子（４）（４）との間に本発明による静
電破壊防止素子（５）が並列に接続される。An insulating layer (11) made of silicon oxide or the like is provided on the surface of the epitaxial layer α]), and a first electrode On and a second electrode are formed across this insulating layer (first region α4 on 161) and second region a9. An a-frame is provided by aluminum vapor deposition, etc.The first electrode aη is connected to the first region t14 through a contact hole provided in the insulating layer in ohmic contact, and the second electrode aη is connected to the first region t14 through a contact hole. and is connected to the second region (Iω) in ohmic contact.The first electrode αη and the second electrode are connected between the external terminal and the internal circuit, respectively, and as shown in FIG. The electrostatic breakdown prevention element (5) according to the present invention is connected in parallel between the electrostatic discharge prevention device (5) and the external terminals (4) (4).
さて、本発明は、通常の場合、第１電極ａηと第２電極
α樽とは遮断されているので、静電破壊防止素手（５）
には入力信号は流れない。従って、外部端子（４１（４
１から内部回路（１）へは、入力信号は減衰せずに流れ
るため９回路動作に何ら影響を及ばすことはない。Now, in the present invention, since the first electrode aη and the second electrode α barrel are normally cut off, the electrostatic damage prevention bare hand (5)
No input signal flows through. Therefore, the external terminal (41 (4
Since the input signal flows from No. 1 to internal circuit (1) without attenuation, it does not affect the operation of No. 9 circuit in any way.
ところで、外部端子にサージ電圧が加わった場合、第１
電極αη、第２電極鱈間に加わる電圧が第１領域Ｉおよ
び第２領域（へ）を導通させる反転層が生成する閾値を
越える！そして、第１電極（１？）および第２電極α樟
に加わる電圧の正負によって、第１電極αＤの下若しく
は第２電極鱈の下のいずれかのエピタキシャル層（１１
）表面が反転電位を越えること罠より、半導体領域（１
３表面に反転層が生成し、第１電極ａηと第２電極Ｑ８
とが導通する。従って、サージ電圧は外部端子（４）か
も静電破壊防止素子（５）を通って外部端子（４）へ流
れ、サージ電圧を吸収して、内部回路（１）をサージ電
圧から保護することができる。また、順逆いずれの方向
のサージ電圧が入っても、反転層の生成する箇所が異な
るだけで、第１電極Ｃ１７］と第２電極０槌とは導通す
るので、サージ電圧を吸収することに変りわない。By the way, if a surge voltage is applied to the external terminal, the first
The voltage applied between the electrode αη and the second electrode exceeds the threshold generated by the inversion layer that makes the first region I and the second region conductive! Then, depending on the positive or negative voltage applied to the first electrode (1?) and the second electrode αD, the epitaxial layer (11?) is formed under either the first electrode αD or the second electrode αD.
) surface exceeds the reversal potential, the semiconductor region (1
3, an inversion layer is generated on the surface of the first electrode aη and the second electrode Q8.
conducts. Therefore, the surge voltage flows to the external terminal (4) either through the external terminal (4) or through the electrostatic breakdown prevention element (5), absorbs the surge voltage, and protects the internal circuit (1) from the surge voltage. can. In addition, even if a surge voltage is applied in either the forward or reverse direction, the first electrode C17 and the second electrode C17 are electrically connected, just because the location where the inversion layer is generated is different, so the surge voltage is absorbed instead. No.
尚、第１電極（ｌηと第２電極ｔｔｇｊの電極の幅は広
い方が大電流にも耐えることができる。また、第１領域
Ｈと第２領域（１５１の間隔はチャンネル幅を短くする
ために接近させた方が良い。Note that the wider the width of the first electrode (lη) and the second electrode ttgj, the more they can withstand a large current. Also, the distance between the first region H and the second region (151) is set to shorten the channel width. It is better to have it close to.
（ト）発明の詳細
な説明したように、本発明によれば、通常の回路動作に
影響を与えずに、順逆のサージ電圧に対して、半導体集
積回路装置を保蒋することができる。(G) As described in detail, according to the present invention, a semiconductor integrated circuit device can be protected against forward and reverse surge voltages without affecting normal circuit operation.
第１図ないし第３図は本発明の一実施例を示し、第１図
は上面図、第２図は第１図の■−■線断面図、蕗３図は
入力回路図である。第４図は従来の静電破壊防止用の入
力回路図である。
ｆｌ）・・・内部回路、 （４）・・・外部端子、 （
５）・・・本発明による静電破壊防止素子、 （１０１
・・・半導体基板、（１□□□・・・半導体領域（島領
域）、 ０滲・・・第１領域、＜１５１・・・第２領域
、 顛・・・絶縁層、 ａＤ・・・第１電極、（１８１
−・・第２電極。
出願人 三洋電機株式会社 外１名
代理人 弁理士 佐 野 靜 夫
第１図
■→
第２図
第３図
第４図1 to 3 show an embodiment of the present invention, in which FIG. 1 is a top view, FIG. 2 is a cross-sectional view taken along the line ■--■ in FIG. 1, and FIG. 3 is an input circuit diagram. FIG. 4 is a diagram of a conventional input circuit for preventing electrostatic damage. fl)...internal circuit, (4)...external terminal, (
5)...Electrostatic breakdown prevention element according to the present invention, (101
...Semiconductor substrate, (1□□□...Semiconductor region (island region), 0)...First region, <151...Second region, 顛...Insulating layer, aD... First electrode, (181
-...Second electrode. Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Yasuo Sano Figure 1 → Figure 2 Figure 3 Figure 4
Claims (1)
に接続される静電破壊防止素子であって、前記静電破壊
防止素子は、Ｎ（又はＰ）型の半導体領域と、この半導
体領域に設けたＰ（又はＮ）型の第１領域および第２領
域と、この第１および第２領域間に絶縁層を介して跨る
第１電極および第２電極とを具備し、前記第１電極を第
１領域にオーミック接触して接続すると共に、前記第２
電極を第２領域にオーミック接触して接続し、前記外部
端子を介して前記第１および第２電極間にサージ電圧が
加わった場合に、前記第１および第２領域間の半導体領
域表面に反転層が生成し、前記第１および第２電極間が
導通することにより、サージ電圧を吸収することを特徴
とする静電破壊防止素子。(1) An electrostatic breakdown prevention element connected in parallel between the input side of a semiconductor integrated circuit and an external terminal, the electrostatic breakdown prevention element comprising an N (or P) type semiconductor region and a A P (or N) type first region and a second region provided in a semiconductor region, and a first electrode and a second electrode extending between the first and second regions with an insulating layer interposed therebetween. one electrode is connected to the first region in ohmic contact, and the second electrode is connected to the first region in ohmic contact.
When an electrode is connected to a second region in ohmic contact and a surge voltage is applied between the first and second electrodes through the external terminal, the surface of the semiconductor region between the first and second regions is inverted. An electrostatic breakdown prevention element characterized in that a surge voltage is absorbed by forming a layer and conducting between the first and second electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15495484A JPS6132561A (en) | 1984-07-25 | 1984-07-25 | Electrostatic breakdown preventive element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15495484A JPS6132561A (en) | 1984-07-25 | 1984-07-25 | Electrostatic breakdown preventive element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6132561A true JPS6132561A (en) | 1986-02-15 |
Family
ID=15595542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15495484A Pending JPS6132561A (en) | 1984-07-25 | 1984-07-25 | Electrostatic breakdown preventive element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6132561A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5212573A (en) * | 1988-11-18 | 1993-05-18 | Seiko Instruments Inc. | Input protection circuit of electro-optical device |
| US5828106A (en) * | 1993-09-20 | 1998-10-27 | Fujitsu Limited | ESD tolerated SOI device |
-
1984
- 1984-07-25 JP JP15495484A patent/JPS6132561A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5212573A (en) * | 1988-11-18 | 1993-05-18 | Seiko Instruments Inc. | Input protection circuit of electro-optical device |
| US5828106A (en) * | 1993-09-20 | 1998-10-27 | Fujitsu Limited | ESD tolerated SOI device |
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