JPH0563740A - Phase locked loop receiver - Google Patents
Phase locked loop receiverInfo
- Publication number
- JPH0563740A JPH0563740A JP3240322A JP24032291A JPH0563740A JP H0563740 A JPH0563740 A JP H0563740A JP 3240322 A JP3240322 A JP 3240322A JP 24032291 A JP24032291 A JP 24032291A JP H0563740 A JPH0563740 A JP H0563740A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- phase
- level
- output
- controlled oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は位相同期受信機に関し、
特に信号の初期捕捉を容易に行い得る衛星通信システム
用の位相同期受信機に関する。BACKGROUND OF THE INVENTION The present invention relates to a phase locked receiver,
In particular, the present invention relates to a phase synchronization receiver for a satellite communication system that can easily perform initial acquisition of signals.
【０００２】[0002]
【従来の技術】従来、衛星通信システム用の受信機は、
衛星からの微弱な電波を受信するため、狭い帯域で高感
度の位相同期回路を用いた構成とされている。この狭帯
域の故に初期捕捉時或いは再同期時における受信信号へ
の位相同期がかかり易くなり、高感度の位相同期回路と
なっている。図２は従来の位相同期受信機のブロック図
である。受信信号は混合器１において電圧制御発振器４
の出力により中間周波数帯に周波数変換され、利得制御
増幅器２に入力される。更に、共通の基準信号発振器６
からの基準信号を受けている位相検波器３及び同期検波
器５にそれぞれ送出される。位相検波器３の出力は信号
切替器１１及び低域ろ波器（ＬＰＦ）１５を経て電圧制
御発振器４に加えられ、位相同期ループを形成する。更
に、位相同期ループを制御する信号切替器１１に掃引発
振器１３の信号を送出して掃引を行うように構成する。
尚、同期検出器１２は同期検波器５の出力から位相同期
ループの同期、非同期を判定し、判定結果に基づいて信
号切替器１１を制御する。2. Description of the Related Art Conventionally, receivers for satellite communication systems are
Since it receives weak radio waves from satellites, it is configured to use a highly sensitive phase-locked loop in a narrow band. Due to this narrow band, phase synchronization with the received signal is likely to occur at the time of initial acquisition or resynchronization, resulting in a highly sensitive phase synchronization circuit. FIG. 2 is a block diagram of a conventional phase locked receiver. The received signal is sent to the mixer 1 by the voltage controlled oscillator 4
Is converted to an intermediate frequency band by the output of the input signal and input to the gain control amplifier 2. Furthermore, a common reference signal oscillator 6
Are sent to the phase detector 3 and the synchronous detector 5, respectively. The output of the phase detector 3 is applied to the voltage controlled oscillator 4 via the signal switch 11 and the low pass filter (LPF) 15 to form a phase locked loop. Further, the signal of the sweep oscillator 13 is sent to the signal switch 11 which controls the phase locked loop to perform the sweep.
The synchronization detector 12 determines whether the phase-locked loop is synchronous or asynchronous from the output of the synchronous detector 5, and controls the signal switcher 11 based on the determination result.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来の位相同
期受信機では、受信する周波数帯域中に複数のキャリア
信号が存在するような場合に、この周波数帯域の全帯域
にわたって位相同期ループを掃引すると、目的以外のキ
ャリア信号に位相同期するおそれがある。したがって、
従来では掃引範囲をある設定値のまわりの微小範囲に制
限している。このため、複数のキャリア信号の中の任意
の信号に対して位相同期させることができなくなる。
又、時間の経過とともに受信信号がずれていった場合、
信号が欠落したときに掃引発振器がそのずれに追従でき
ず、再同期できなくなることがある。本発明の目的は、
受信機の狭帯域性及び高感度性を維持したまま周波数掃
引範囲を広くすることを可能にした位相同期受信機を提
供することにある。In the above-mentioned conventional phase locked receiver, when a plurality of carrier signals exist in the frequency band to be received, the phase locked loop is swept over the entire frequency band. , There is a risk of phase synchronization with a carrier signal other than the intended one. Therefore,
Conventionally, the sweep range is limited to a minute range around a certain set value. Therefore, it becomes impossible to synchronize the phase with an arbitrary signal of the plurality of carrier signals.
Also, if the received signal deviates over time,
When the signal is lost, the sweep oscillator may not be able to follow the shift and may not be able to resynchronize. The purpose of the present invention is to
An object of the present invention is to provide a phase-locked receiver capable of widening the frequency sweep range while maintaining the narrow band property and high sensitivity of the receiver.
【０００４】[0004]
【課題を解決するための手段】本発明の位相同期受信機
は、従来の受信機に加えて、受信信号の初期捕捉を行う
ときに電圧制御発振器の出力周波数を掃引する制御電圧
を発生するＤ／Ａ変換器と、同期検波器からの出力信号
をデジタル変換して前記電圧制御発振器の出力周波数の
掃引時におけるレベルを出力するＡ／Ｄ変換器と、この
Ａ／Ｄ変換器から出力されたレベルと、このレベルを得
たときの電圧制御発振器への制御電圧を記憶するメモリ
と、メモリに記憶されたレベルを基にして受信する所要
の信号を選択し、その信号が得られたところの前記メモ
リに記憶されている電圧制御発振器への制御電圧に基づ
いて所望の信号の近傍のみを周波数掃引する信号を前記
Ｄ／Ａ変換器に出力するマイクロプロセッサとを備えて
いる。又、位相同期ループを制御するための信号切替器
は、電圧制御発振器の入力をＤ／Ａ変換器と位相検波器
とで切り替えでき、位相同期が得られた場合に位相検波
器側に切り替えられように構成する。In addition to the conventional receiver, the phase-locked receiver of the present invention generates a control voltage that sweeps the output frequency of the voltage-controlled oscillator when the reception signal is initially captured. A / A converter, an A / D converter that digitally converts the output signal from the synchronous detector and outputs the level when the output frequency of the voltage controlled oscillator is swept, and the A / D converter that outputs the level. Select the level and the memory that stores the control voltage to the voltage-controlled oscillator when this level is obtained, and the required signal to be received based on the level stored in the memory. And a microprocessor for outputting to the D / A converter a signal for frequency sweeping only the vicinity of a desired signal based on a control voltage to a voltage controlled oscillator stored in the memory. Further, the signal switch for controlling the phase locked loop can switch the input of the voltage controlled oscillator between the D / A converter and the phase detector, and when the phase synchronization is obtained, it is switched to the phase detector side. To configure.
【０００５】[0005]
【作用】本発明によれば、メモリに記憶されたレベルと
制御電圧により周波数掃引を行うため、周波数掃引範囲
を広くしても不要信号に対して位相同期することはな
く、狭帯域及び高感度が確保される。According to the present invention, since the frequency sweep is performed by the level and the control voltage stored in the memory, even if the frequency sweep range is widened, the unnecessary signal is not phase-locked, and the narrow band and high sensitivity are achieved. Is secured.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の一実施例のブロック図である。受信
信号は混合器１において電圧制御発振器４の出力により
中間周波数に周波数変換され、利得制御増幅器２に入力
される。その出力は共通の基準信号発生器６からの基準
信号を受け入れる位相検波器３及び同期検波器５にそれ
ぞれ送出される。位相検波器３の出力は、通常は信号切
替器１１を経てＬＰＦ１５から電圧制御発振器４に加え
られ、位相同期ループ（ＰＬＬ）を形成する。一方、同
期検波器５の出力は、ＬＰＦ７を通って利得制御増幅器
２に加えられてＡＧＣループを形成する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. The received signal is frequency-converted into an intermediate frequency by the output of the voltage controlled oscillator 4 in the mixer 1 and input to the gain control amplifier 2. The output is sent to each of the phase detector 3 and the synchronous detector 5 which receive the reference signal from the common reference signal generator 6. The output of the phase detector 3 is normally applied to the voltage controlled oscillator 4 from the LPF 15 via the signal switch 11 to form a phase locked loop (PLL). On the other hand, the output of the synchronous detector 5 is applied to the gain control amplifier 2 through the LPF 7 to form an AGC loop.
【０００７】Ｄ／Ａ変換器１０は、受信信号の初期捕捉
を行うときに電圧制御発振器４の出力周波数を掃引する
ための制御電圧を発生する。又、Ａ／Ｄ変換器１４は前
記同期検波器５の出力信号をデジタル信号に変換してマ
イクロプロセッサ９に出力する。マイクロプロセッサ９
はそのレベルを計測し、かつそのレベルを得たときの電
圧制御発振器４への制御電圧をそれぞれメモリ８に記憶
させる。更に、このマイクロプロセッサ９は、メモリ８
に記憶された制御電圧に基づいて前記Ｄ／Ａ変換器１０
に所望の周波数の近傍のみを掃引するような信号を出力
させる。The D / A converter 10 generates a control voltage for sweeping the output frequency of the voltage controlled oscillator 4 when the reception signal is initially captured. Further, the A / D converter 14 converts the output signal of the synchronous detector 5 into a digital signal and outputs it to the microprocessor 9. Microprocessor 9
Measures the level and causes the memory 8 to store the control voltage to the voltage controlled oscillator 4 when the level is obtained. Further, this microprocessor 9 has a memory 8
Based on the control voltage stored in the D / A converter 10
To output a signal that sweeps only in the vicinity of the desired frequency.
【０００８】この構成によれば、マイクロプロセッサ９
はメモリ８に書き込まれている制御プログラムにより、
図４に示すフローチャートのような周波数捕捉動作を実
行する。尚、ここでは図３に示すように、受信周波数範
囲Ｄに３つのキャリア信号Ｃ１，Ｃ２，Ｃ３がある場合
で、その中の最大レベルのキャリア信号に位相同期をか
けて捕捉する例を示す。周波数掃引開始時にはＤＳから
ＤＥまでの周波数範囲Ｄの周波数掃引を開始する（ステ
ップ１０１）。そして、その周波数の掃引が終了する迄
（ステップ１０２）では、受信レベルＬを常時モニター
し、そのレベルがある基準値ＬＲ以上になるかどうかを
比較する（ステップ１０３）。そして、受信レベルＬの
最大値を順次ＬＭＡＸとしながら周波数掃引を継続する
（ステップ１０４，１０５，１０９，１１０）。According to this configuration, the microprocessor 9
Is a control program written in the memory 8,
The frequency acquisition operation as shown in the flowchart of FIG. 4 is executed. Here, as shown in FIG. 3, in the case where there are three carrier signals C1, C2, C3 in the reception frequency range D, an example is shown in which the carrier signal of the maximum level among them is acquired in phase synchronization. When the frequency sweep is started, the frequency sweep in the frequency range D from DS to DE is started (step 101). Until the sweep of the frequency is completed (step 102), the reception level L is constantly monitored, and it is compared whether or not the level exceeds a certain reference value LR (step 103). Then, the frequency sweep is continued while sequentially setting the maximum value of the reception level L to LMAX (steps 104, 105, 109, 110).
【０００９】又、受信レベルＬがＬＲより大きくなり、
次に受信レベルがＬＲより小さくなる範囲（ステップ１
０６，１０７，１０８）では、その間の受信最大レベル
をＬ（Ｉ）＝ＬＭＡＸ（Ｉ＝１）としてメモリ８へ記憶
する。このとき、（Ｉ）＝ＬＭＡＸが得られたときの電
圧制御発振器４への制御電圧をＢ（Ｉ）＝ＢＭＡＸ（Ｉ
＝１）としてメモリ８へ記憶する。この例では、キャリ
アＣ１に対しては、Ｌ（１）＝Ｌ２、Ｂ（１）＝Ｂ１が
記憶される。同様の手順にて他の２つのキャリアＣ２及
びＣ３に対するレベル及び電圧制御発振器４への制御電
圧を記憶する。結果として、この例では、Ｌ（２）＝Ｌ
１、Ｂ（２）＝Ｂ２、Ｌ（３）＝Ｌ３、Ｂ（３）＝Ｂ３
が得られる。この手順の実行中は信号切替器１１の入力
はＤ／Ａ変換器１０側に、出力は直接電圧制御発振器４
に送られるように設定されており、ＰＬＬループは所謂
オープンループが維持されている。Further, the reception level L becomes larger than LR,
Next, the range where the reception level becomes smaller than LR (step 1
06, 107, 108), the maximum reception level during that time is stored in the memory 8 as L (I) = LMAX (I = 1). At this time, the control voltage to the voltage controlled oscillator 4 when (I) = LMAX is obtained is B (I) = BMAX (I
= 1) and store it in the memory 8. In this example, L (1) = L2 and B (1) = B1 are stored for the carrier C1. In the same procedure, the levels for the other two carriers C2 and C3 and the control voltage to the voltage controlled oscillator 4 are stored. As a result, in this example, L (2) = L
1, B (2) = B2, L (3) = L3, B (3) = B3
Is obtained. During execution of this procedure, the input of the signal switch 11 is to the D / A converter 10 side and the output is the direct voltage controlled oscillator 4
Is set so that the so-called open loop is maintained in the PLL loop.
【００１０】次に、周波数の掃引が終了した後に、得ら
れた受信レベルの中から最大レベルのものを探す（ステ
ップ１１１）。本実施例ではレベルＬ１が最大であるか
ら、Ｉ＝２を得る。次に、Ｂ（２）＝Ｂ２の制御電圧を
ＬＰＦ１５を介して電圧制御発振器４へ印加し、その付
近を僅かに掃引する（ステップ１１２）。このとき信号
切替器１１は同期検出器１２からの信号を受け、位相同
期が得られた場合信号切替器１１はその設定をＤ／Ａ変
換器１０側から位相検波器３の出力側に切り替わるよう
にし、位相同期（ステップ１１３）を得る。Next, after the frequency sweep is completed, the maximum reception level is searched from the obtained reception levels (step 111). In this embodiment, the level L1 is the maximum, so that I = 2 is obtained. Next, a control voltage of B (2) = B2 is applied to the voltage controlled oscillator 4 via the LPF 15, and the vicinity thereof is slightly swept (step 112). At this time, the signal switcher 11 receives the signal from the synchronization detector 12, and when phase synchronization is obtained, the signal switcher 11 switches its setting from the D / A converter 10 side to the output side of the phase detector 3. To obtain phase synchronization (step 113).
【００１１】[0011]
【発明の効果】以上説明したように本発明は、電圧制御
発振器を掃引する制御電圧を発生するＤ／Ａ変換器と、
電圧制御発振器の掃引時におけるレベルを出力するＡ／
Ｄ変換器と、このレベルとその際の制御電圧を記憶する
メモリと、メモリに記憶されたレベルを基にして電圧制
御発振器の掃引を制御するマイクロプロセッサとを備え
ているので、周波数掃引範囲に複数のキャリア信号が存
在してもキャリア信号のレベルに応じて所望のキャリア
信号を選択して周波数捕捉を行なうことができるので、
受信機の狭帯域性及び高感度性を維持したまま周波数掃
引範囲を広くできる効果がある。As described above, the present invention provides a D / A converter for generating a control voltage for sweeping a voltage controlled oscillator,
A / which outputs the level when the voltage controlled oscillator is swept
Since the D converter, the memory that stores this level and the control voltage at that time, and the microprocessor that controls the sweep of the voltage-controlled oscillator based on the level stored in the memory are included, the frequency sweep range is Even if there are multiple carrier signals, it is possible to select a desired carrier signal according to the level of the carrier signal and perform frequency acquisition.
This has the effect of widening the frequency sweep range while maintaining the narrow bandwidth and high sensitivity of the receiver.
【図１】本発明の位相同期受信機の一実施例のブロック
図である。FIG. 1 is a block diagram of an embodiment of a phase synchronization receiver of the present invention.
【図２】従来の位相同期受信機の一例のブロック図であ
る。FIG. 2 is a block diagram of an example of a conventional phase synchronization receiver.
【図３】周波数掃引範囲にある複数のキャリア信号のス
ペクトラム図である。FIG. 3 is a spectrum diagram of a plurality of carrier signals in a frequency sweep range.
【図４】マイクロプロセッサにおける掃引実行手順を示
すフローチャートである。FIG. 4 is a flowchart showing a sweep execution procedure in a microprocessor.
１ 混合器 ２ 利得制御増幅器 ３ 位相検波器 ４ 電圧制御発振器 ５ 同期検波器 ６ 基準信号発振器 ７ ＬＰＦ ８ メモリ ９ マイクロプロセッサ １０ Ｄ／Ａ変換器 １１ 信号切替器 １２ 同期検出器 １４ Ａ／Ｄ変換器 1 Mixer 2 Gain Control Amplifier 3 Phase Detector 4 Voltage Controlled Oscillator 5 Synchronous Detector 6 Reference Signal Oscillator 7 LPF 8 Memory 9 Microprocessor 10 D / A Converter 11 Signal Switcher 12 Synchronous Detector 14 A / D Converter
Claims (2)
る混合器と、この混合器の出力信号を増幅する利得制御
増幅器と、この利得制御増幅器の出力信号の位相を検出
する位相検波器と、この位相検波器からの信号を入力し
て位相同期ループを形成し前記混合器へ局部発振信号を
供給する電圧制御発振器と、前記利得制御増幅器の出力
振幅を検出し、これを前記利得制御増幅器に加えて自動
利得制御ループを形成する同期検波器と、前記位相同期
ループを制御するための信号切替器と、受信信号の初期
捕捉を行うときに前記電圧制御発振器の出力周波数を掃
引する制御電圧を発生するＤ／Ａ変換器と、前記同期検
波器からの出力信号をデジタル変換して前記電圧制御発
振器の出力周波数の掃引時におけるレベルを出力するＡ
／Ｄ変換器と、このＡ／Ｄ変換器から出力されたレベル
と、このレベルを得たときの電圧制御発振器への制御電
圧を記憶するメモリと、メモリに記憶されたレベルを基
にして受信する所要の信号を選択し、その信号が得られ
たところの前記メモリに記憶されている電圧制御発振器
への制御電圧に基づいて所望の信号の近傍のみを周波数
掃引する信号を前記Ｄ／Ａ変換器に出力するマイクロプ
ロセッサとを備えることを特徴とする位相同期受信機。1. A mixer for frequency-converting a received signal into an intermediate frequency band, a gain control amplifier for amplifying an output signal of the mixer, and a phase detector for detecting a phase of an output signal of the gain control amplifier, A voltage-controlled oscillator that inputs a signal from this phase detector to form a phase-locked loop and supplies a local oscillation signal to the mixer, and the output amplitude of the gain-controlled amplifier are detected, and this is output to the gain-controlled amplifier. In addition, a synchronous detector that forms an automatic gain control loop, a signal switcher for controlling the phase-locked loop, and a control voltage that sweeps the output frequency of the voltage-controlled oscillator when the reception signal is initially captured. A generated D / A converter and an output signal from the synchronous detector are converted into digital signals to output a level when the output frequency of the voltage controlled oscillator is swept.
A / D converter, a level output from the A / D converter, a memory for storing the control voltage to the voltage controlled oscillator when the level is obtained, and a reception based on the level stored in the memory A desired signal to be selected is selected, and the signal for frequency sweeping only the vicinity of the desired signal is D / A converted based on the control voltage to the voltage controlled oscillator stored in the memory where the signal is obtained. A phase-locked receiver comprising a microprocessor for outputting to a receiver.
／Ａ変換器と位相検波器とで切り替えるように動作さ
れ、位相同期が得られた場合に位相検波器側に切り替え
られように構成してなる請求項１の位相同期受信機。2. The signal switch is configured so that the input of the voltage controlled oscillator is D
The phase-locked receiver according to claim 1, wherein the phase-locked receiver is configured to be switched between the A / A converter and the phase detector and switched to the phase detector side when phase synchronization is obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3240322A JP2903797B2 (en) | 1991-08-28 | 1991-08-28 | Phase locked receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3240322A JP2903797B2 (en) | 1991-08-28 | 1991-08-28 | Phase locked receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0563740A true JPH0563740A (en) | 1993-03-12 |
| JP2903797B2 JP2903797B2 (en) | 1999-06-14 |
Family
ID=17057749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3240322A Expired - Lifetime JP2903797B2 (en) | 1991-08-28 | 1991-08-28 | Phase locked receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2903797B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63156130U (en) * | 1987-03-31 | 1988-10-13 | ||
| JPH04139938A (en) * | 1990-09-29 | 1992-05-13 | Nec Corp | Data demodulator |
-
1991
- 1991-08-28 JP JP3240322A patent/JP2903797B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63156130U (en) * | 1987-03-31 | 1988-10-13 | ||
| JPH04139938A (en) * | 1990-09-29 | 1992-05-13 | Nec Corp | Data demodulator |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2903797B2 (en) | 1999-06-14 |
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