JPH05335715A - Installation structure of semiconductor package on printed wiring board - Google Patents
Installation structure of semiconductor package on printed wiring boardInfo
- Publication number
- JPH05335715A JPH05335715A JP4138189A JP13818992A JPH05335715A JP H05335715 A JPH05335715 A JP H05335715A JP 4138189 A JP4138189 A JP 4138189A JP 13818992 A JP13818992 A JP 13818992A JP H05335715 A JPH05335715 A JP H05335715A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- semiconductor package
- lead
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、表面実装型半導体パ
ッケージのプリント配線板への実装構造に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of a surface mount type semiconductor package on a printed wiring board.
【０００２】[0002]
【従来の技術】図３は、従来の半導体パッケージのプリ
ント配線板への実装構造を示したものである。2. Description of the Related Art FIG. 3 shows a conventional mounting structure of a semiconductor package on a printed wiring board.
【０００３】図において、１１は４層のガラス布エポキ
シ積層板よりなるプリント配線板で、１２はその上に設
けられたパッドである。１３，１４および１５はプリン
ト配線板１１の上に回路を形成するパターン，ランドお
よびスルーホールである。１６はリードピッチの微細な
表面実装型の半導体パッケージで、平面形状が四角形の
パッケージ本体１６ａの４つの側面部にそれぞれリード
１６ｂを並列して突設した形状になっている。パッケー
ジ本体１６ａは半導体チップをプラスチックスでパッケ
ージすることによって作られている。リード１６ｂのピ
ッチは０．３mmで、各リード１６ｂは半田付けによって
プリント配線板１１のパッド１２に電気的に接続され
て、かつ機械的に固定されている。In the figure, reference numeral 11 is a printed wiring board made of a four-layer glass cloth epoxy laminated board, and 12 is a pad provided thereon. Reference numerals 13, 14 and 15 are patterns, lands and through holes that form a circuit on the printed wiring board 11. Reference numeral 16 denotes a surface-mounting type semiconductor package having a fine lead pitch, which has a shape in which leads 16b are juxtaposed in parallel on four side surfaces of a package body 16a having a quadrangular planar shape. The package body 16a is made by packaging a semiconductor chip with plastics. The lead 16b has a pitch of 0.3 mm, and each lead 16b is electrically connected to the pad 12 of the printed wiring board 11 by soldering and is mechanically fixed.
【０００４】このように、従来の表面実装構造は、文字
通り表面実装であるため、０．３ｍｍという微細なリー
ドピッチの半導体パッケージ１６であっても、プリント
配線板１１に実装することができる。この点は、挿入実
装構造等に比べて優れているところである。As described above, since the conventional surface mounting structure is literally surface mounting, even a semiconductor package 16 having a fine lead pitch of 0.3 mm can be mounted on the printed wiring board 11. This point is superior to the insertion mounting structure and the like.
【０００５】[0005]
【発明が解決しようとする課題】しかし、半導体パッケ
ージ１６のリードピッチが上述のように０．３ｍｍまた
はそれ以下となってくると、発熱密度が高くなるので、
次のような問題があった。However, when the lead pitch of the semiconductor package 16 becomes 0.3 mm or less as described above, the heat generation density becomes high.
There were the following problems.
【０００６】すなわち、半導体パッケージ１６から発生
した熱で、同パッケージ１６とプリント配線板１１が熱
膨張し、そのときの線膨張率の差でリード１６ａがパッ
ド１２から外れてしまう。つまり、半導体パッケージ１
６に比べて線膨張率の大きいプリント配線板１１に発生
した応力で、半導体パッケージ１６とプリント配線板１
１が相対的に大きくずれて、リード１６ａとパッド１２
の半田による接続部が離れてしまう。That is, the heat generated from the semiconductor package 16 causes the package 16 and the printed wiring board 11 to thermally expand, and the lead 16a comes off the pad 12 due to the difference in linear expansion coefficient at that time. That is, the semiconductor package 1
The stress generated in the printed wiring board 11 having a higher linear expansion coefficient than that of the semiconductor package 6 causes the semiconductor package 16 and the printed wiring board 1 to
1 is relatively deviated, and lead 16a and pad 12
The connection part due to the solder is separated.
【０００７】この発明は、このような従来の問題点を解
決するためになされたもので、リードピッチの微細な半
導体パッケージを表面実装しても、そのリードがパッド
から外れるおそれのない、半導体パッケージのプリント
配線板への実装構造を提供することを目的とする。The present invention has been made in order to solve the above-mentioned conventional problems, and even if a semiconductor package having a fine lead pitch is surface-mounted, the leads are not likely to come off from the pads. It is an object of the present invention to provide a mounting structure for a printed wiring board.
【０００８】[0008]
【課題を解決するための手段】この発明が提供する半導
体パッケージのプリント配線板への実装構造は、前記半
導体パッケージのリードを、複数の、ピッチの小さいリ
ード群に分け、前記プリント配線板に、前記各リード群
に対応するリード接続用のパッド群を設け、これらパッ
ド群の間に溝を設けた点に特徴がある。According to a mounting structure of a semiconductor package on a printed wiring board provided by the present invention, the leads of the semiconductor package are divided into a plurality of lead groups having a small pitch, and the printed wiring board is provided with: It is characterized in that a pad group for lead connection corresponding to each of the lead groups is provided and a groove is provided between these pad groups.
【０００９】[0009]
【作用】この発明の実装構造においては、半導体パッケ
ージから発生した熱によって線膨張率の大きいプリント
配線板の方が線膨張率の小さい半導体パッケージより大
きく熱膨張する。しかし、このときプリント配線板に発
生する応力は、上記溝によって緩和されるので、半導体
パッケージとプリント配線板のずれが小さくなり、リー
ドがパッドから外れにくくなる。In the mounting structure of the present invention, the heat generated from the semiconductor package causes the printed wiring board having a larger linear expansion coefficient to expand more than the semiconductor package having a smaller linear expansion coefficient. However, since the stress generated in the printed wiring board at this time is relieved by the groove, the deviation between the semiconductor package and the printed wiring board becomes small, and the leads do not easily come off the pads.
【００１０】[0010]
【実施例】以下、この発明の実施例を図１と図２によっ
て説明する。図１は実施例の斜視図で、図３に対応する
ものであり、図２は図１のII−II断面を示したものであ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS. 1 is a perspective view of the embodiment, which corresponds to FIG. 3, and FIG. 2 shows a II-II cross section of FIG.
【００１１】図において、１は４層のガラス布エポキシ
積層板よりなるプリント配線板、３は同配線板１の上に
設けたパッドで、後述する半導体パッケージ６のリード
６ｂを半田付けで接続するためのもの、３，４および５
はプリント配線板１上に回路を形成するパターン，ラン
ドおよびスルーホールである。In the figure, reference numeral 1 is a printed wiring board made of a four-layer glass cloth epoxy laminated board, and 3 is a pad provided on the wiring board 1, to which leads 6b of a semiconductor package 6 to be described later are connected by soldering. For, 3, 4 and 5
Are patterns, lands and through holes that form a circuit on the printed wiring board 1.
【００１２】６はリードピッチの微細な表面実装型の半
導体パッケージで、平面形状が四角形のパッケージ本体
６ａの４つの側面部にそれぞれリード６ｂを並列して突
設した構造になっている。パッケージ本体６ａは半導体
チップをプラスチックスでパッケージすることによって
作られている。パッケージ本体の各側面部に並列して突
設したリード６ｂは、その中間部のピッチを大きくする
ことによって、８個のリード群７に分けられており、各
リード群７を構成するリード６ｂのピッチは０．３mmで
ある。Reference numeral 6 denotes a fine surface-mounting type semiconductor package having a lead pitch, which has a structure in which leads 6b are juxtaposed in parallel on four side surfaces of a package body 6a having a quadrangular planar shape. The package body 6a is made by packaging a semiconductor chip with plastics. The leads 6b projecting in parallel from the side surface portions of the package body are divided into eight lead groups 7 by increasing the pitch of the middle portion thereof. The pitch is 0.3 mm.
【００１３】８個のリード群７は、これら各リード群７
に属するリード６ｂに対応するパッド２からなる８個の
パッド群８に半田９で接続しかつ固定されている。The eight lead groups 7 are each of these lead groups 7.
Are connected to and fixed to a group of eight pads 8 composed of pads 2 corresponding to the leads 6b belonging to the same with solder 9.
【００１４】１０はプリント配線板１の上に設けた溝
で、上記８個のパッド群８の間に、これを仕切るように
配置されている。溝１０の深さは、表面の１層相当であ
る。それ以上深くすると、プリント配線板１としての強
度が不足するので、好ましくない。一般に４層以上のプ
リント配線板であれば、表層の１層だけの深さがあれば
よい。A groove 10 is provided on the printed wiring board 1 and is arranged between the eight pad groups 8 so as to partition the pad group. The depth of the groove 10 is equivalent to one layer on the surface. If the depth is further than that, the strength of the printed wiring board 1 becomes insufficient, which is not preferable. Generally, in the case of a printed wiring board having four or more layers, the depth of only one surface layer is required.
【００１５】次に、上記構成に基づく作用を説明する。Next, the operation based on the above configuration will be described.
【００１６】半導体パッケージ１の自己発熱で周囲の温
度が上昇すると、線膨張率の大きいプリント配線板１
が、線膨張率の小さい半導体パッケージ６より大きく熱
膨張する。When the ambient temperature rises due to self-heating of the semiconductor package 1, the printed wiring board 1 having a large linear expansion coefficient.
However, the thermal expansion is larger than that of the semiconductor package 6 having a small linear expansion coefficient.
【００１７】しかし、このとき、プリント配線板１に発
生する応力は、これに設けた溝１０によって緩和される
ので、半導体パッケージ６とプリント配線板１の相対的
ずれが小さくなる。その結果、リード６ｂとパッド２を
接続している半田９が剥れにくくなり、したがってリー
ド６ｂがパッド２から外れにくくなる。At this time, however, the stress generated in the printed wiring board 1 is relieved by the groove 10 provided therein, so that the relative displacement between the semiconductor package 6 and the printed wiring board 1 becomes small. As a result, the solder 9 that connects the lead 6b and the pad 2 is less likely to peel off, and thus the lead 6b is less likely to come off the pad 2.
【００１８】[0018]
【発明の効果】以上説明したように、この発明によれ
ば、半導体パッケージのリードを複数のピッチの微細な
リード群に分け、プリント配線板に各リード群に対応す
るパッド群を設け、これら各パッド群の間に溝を設けた
ので、熱膨張によってプリント配線板に発生する応力を
上記溝で緩和することができる。したがって、この発明
によれば、半導体パッケージのリードピッチが微細であ
っても、そのリードがプリント配線板のパッドから外れ
にくくなる。As described above, according to the present invention, the leads of the semiconductor package are divided into fine lead groups having a plurality of pitches, and the printed wiring board is provided with pad groups corresponding to the respective lead groups. Since the groove is provided between the pad groups, the stress generated in the printed wiring board due to the thermal expansion can be relaxed by the groove. Therefore, according to the present invention, even if the lead pitch of the semiconductor package is fine, the leads are unlikely to come off from the pads of the printed wiring board.
【図１】実施例の斜視図FIG. 1 is a perspective view of an embodiment.
【図２】図１のII−II断面図FIG. 2 is a sectional view taken along line II-II of FIG.
【図３】従来例の斜視図FIG. 3 is a perspective view of a conventional example.
１ プリント配線板 ２ パッド ６ 半導体パッケージ ６ｂ リード ７ リード群 ８ パッド群 １０ 溝 1 Printed Wiring Board 2 Pad 6 Semiconductor Package 6b Lead 7 Lead Group 8 Pad Group 10 Groove
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成４年１１月６日[Submission date] November 6, 1992
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００５[Correction target item name] 0005
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００５】[0005]
【発明が解決しようとする課題】しかし、半導体パッケ
ージ１６のリードピッチが上述のように０．３mmまたは
それ以下となってくると、パッド面積が小さくなり、実
装時に、次のような問題が生じた。However, when the lead pitch of the semiconductor package 16 becomes 0.3 mm or less as described above, the pad area becomes small, and
The following problems arose during wearing .
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００６[Correction target item name] 0006
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００６】すなわち、半田付け時に加える熱で、同パ
ッケージ１６とプリント配線板１１が熱膨張し、そのと
きの線膨張率の差でリード１６ａがパッド１２から外れ
てしまう。つまり、半導体パッケージ１６に比べて線膨
張率の大きいプリント配線板１１に発生した応力で、半
導体パッケージ１６とプリント配線板１１が相対的に大
きくずれて、リード１６ａとパッド１２の半田による接
続部が離れてしまう。That is, the heat applied at the time of soldering causes the package 16 and the printed wiring board 11 to thermally expand, and the lead 16a comes off the pad 12 due to the difference in linear expansion coefficient at that time. That is, the stress generated in the printed wiring board 11 having a larger linear expansion coefficient than that of the semiconductor package 16 causes the semiconductor package 16 and the printed wiring board 11 to be relatively displaced from each other, so that the connection portion of the leads 16a and the pad 12 by soldering is formed. Get away.
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００９[Correction target item name] 0009
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００９】[0009]
【作用】この発明の実装構造においては、半田付け時に
加える熱によって線膨張率の大きいプリント配線板の方
が線膨張率の小さい半導体パッケージより大きく熱膨張
する。しかし、このときプリント配線板に発生する応力
は、上記溝によって緩和されるので、半導体パッケージ
とプリント配線板のずれが小さくなり、リードがパッド
から外れにくくなる。In the mounting structure of the present invention, when soldering
Due to the heat applied, a printed wiring board having a large linear expansion coefficient thermally expands more than a semiconductor package having a small linear expansion coefficient. However, since the stress generated in the printed wiring board at this time is relieved by the groove, the deviation between the semiconductor package and the printed wiring board becomes small, and the leads do not easily come off the pads.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１６[Correction target item name] 0016
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１６】半導体パッケージ１の半田付け時の加熱で
周囲の温度が上昇すると、線膨張率の大きいプリント配
線板１が、線膨張率の小さい半導体パッケージ６より大
きく熱膨張する。 When the ambient temperature rises due to heating during soldering of the semiconductor package 1, the printed wiring board 1 having a large linear expansion coefficient thermally expands more than the semiconductor package 6 having a small linear expansion coefficient.
Claims (1)
ージのプリント配線板への実装構造であって、前記半導
体パッケージのリードは、複数の、ピッチの小さいリー
ド群に分けられ、前記プリント配線板は、前記各リード
群に対応するリード接続用のパッド群とこれらパッド群
の間に設けた溝とを有していることを特徴とする半導体
パッケージのプリント配線板への実装構造。1. A mounting structure of a surface mounting type semiconductor package having leads on a printed wiring board, wherein the leads of the semiconductor package are divided into a plurality of lead groups having a small pitch, and the printed wiring board comprises: A mounting structure for mounting a semiconductor package on a printed wiring board, comprising: a pad group for lead connection corresponding to each of the lead groups and a groove provided between these pad groups.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4138189A JPH05335715A (en) | 1992-05-29 | 1992-05-29 | Installation structure of semiconductor package on printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4138189A JPH05335715A (en) | 1992-05-29 | 1992-05-29 | Installation structure of semiconductor package on printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05335715A true JPH05335715A (en) | 1993-12-17 |
Family
ID=15216159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4138189A Pending JPH05335715A (en) | 1992-05-29 | 1992-05-29 | Installation structure of semiconductor package on printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05335715A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8599571B2 (en) | 2006-04-21 | 2013-12-03 | Panasonic Corporation | Memory card |
-
1992
- 1992-05-29 JP JP4138189A patent/JPH05335715A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8599571B2 (en) | 2006-04-21 | 2013-12-03 | Panasonic Corporation | Memory card |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |