JPH05335366A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05335366A JPH05335366A JP4163656A JP16365692A JPH05335366A JP H05335366 A JPH05335366 A JP H05335366A JP 4163656 A JP4163656 A JP 4163656A JP 16365692 A JP16365692 A JP 16365692A JP H05335366 A JPH05335366 A JP H05335366A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- insulator
- chip
- semiconductor device
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に樹脂封止された半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.
【0002】[0002]
【従来の技術】多層リードフレームを用いた半導体装置
では、チップおよびリードフレームが銅板上に固着され
ることが多い。即ち、図3に示されるように、銅板1上
に絶縁体2を介してリードフレーム3が固着され、銅板
1の中央には導電性接着剤4を介してチップ5が搭載さ
れる。そして、チップ5−リードフレーム間をボンディ
ングワイヤ6により接続した後、全体をモールド樹脂7
により封止している。2. Description of the Related Art In a semiconductor device using a multilayer lead frame, a chip and a lead frame are often fixed on a copper plate. That is, as shown in FIG. 3, the lead frame 3 is fixed on the copper plate 1 via the insulator 2, and the chip 5 is mounted on the center of the copper plate 1 via the conductive adhesive 4. Then, after the chip 5 and the lead frame are connected by the bonding wire 6, the whole is molded resin 7.
It is sealed by.
【0003】[0003]
【発明が解決しようとする課題】上述した従来の半導体
装置では、チップとリードフレーム間が直接ボンディン
グワイヤにより接続されているため、ボンディングワイ
ヤが長い場合には、樹脂封止の際にボンディングワイヤ
が変形してしまい、隣り合うボンディングワイヤ同士が
接触してしまうという問題点があった。In the conventional semiconductor device described above, since the chip and the lead frame are directly connected to each other by the bonding wire, if the bonding wire is long, the bonding wire is not sealed at the time of resin sealing. There is a problem in that the bonding wires are deformed and adjacent bonding wires come into contact with each other.
【0004】[0004]
【課題を解決するための手段】本発明の半導体装置は、
金属板の中央にチップが搭載され、その周辺に絶縁体を
介してリードフレームが固着され、全体がモールド樹脂
により封止されたものであって、チップ−リードフレー
ム間を接続するボンディングワイヤは、チップ−リード
フレーム間の途中で絶縁体上にもボンディングされてい
る。The semiconductor device of the present invention comprises:
A chip is mounted in the center of a metal plate, a lead frame is fixed to the periphery through an insulator, and the whole is sealed with a mold resin. The bonding wire connecting the chip and the lead frame is Bonding is also performed on the insulator midway between the chip and the lead frame.
【0005】[0005]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図1は、本発明の第1の実施例を示す断面
図である。この半導体装置は、次のようにして組み立て
られる。銅板1に、予めリードフレーム3が固着されて
いる絶縁体2を接着剤を用いて接着する。この絶縁体2
の内側部分には突起が形成されており、この突起上には
メタライズ層が形成されている。Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention. This semiconductor device is assembled as follows. The insulator 2 to which the lead frame 3 is fixed in advance is adhered to the copper plate 1 using an adhesive. This insulator 2
A protrusion is formed on the inner side of the substrate, and a metallized layer is formed on the protrusion.
【0006】次に、銅板1上に導電性接着剤4を用いて
チップ5をマウントする。次いで、ボンディングワイヤ
6を用いてチップ上のパッド−絶縁体2上のメタライズ
層−リードフレーム3の順にボンディングを行い、最後
にモールド樹脂7にて封止を行う。Next, the chip 5 is mounted on the copper plate 1 by using the conductive adhesive 4. Next, the bonding wire 6 is used to perform bonding in the order of the pad on the chip-the metallized layer on the insulator 2-the lead frame 3, and finally sealing with the molding resin 7.
【0007】このように構成された半導体装置では、ボ
ンディングワイヤが中継点を経由しているためフライイ
ングワイヤ長が短くなり、変形されにくくなる。そのた
め、モールド工程でのワイヤ変形による短絡事故が激減
し歩留りが向上する。In the semiconductor device configured as described above, since the bonding wire passes through the relay point, the length of the flying wire is shortened and it is less likely to be deformed. Therefore, the short circuit accident due to the wire deformation in the molding process is drastically reduced, and the yield is improved.
【0008】本実施例では、絶縁体2に突起を設けて絶
縁体のボンディング面と、チップやリードフレームのボ
ンディング面との高低差を少なくしている。この構成に
よりフライイングワイヤ長をより短くすることができ、
また、ボンディング工程も容易化される。リードフレー
ムが多層リードフレームであるとき、リードフレームの
面に合わせて絶縁体の突起の表面にも凹凸を作ることが
できる。In this embodiment, the insulator 2 is provided with a protrusion to reduce the height difference between the insulator bonding surface and the chip or lead frame bonding surface. With this configuration, the flying wire length can be shortened,
Also, the bonding process is facilitated. When the lead frame is a multi-layer lead frame, it is possible to make unevenness on the surface of the protrusion of the insulator in accordance with the surface of the lead frame.
【0009】図2は、本発明の第2の実施例を示す断面
図である。本実施例は、絶縁体2上で2回ワイヤボンデ
ィングを行っている点が先の実施例と相違しているが、
その他の点では同様である。FIG. 2 is a sectional view showing a second embodiment of the present invention. This embodiment is different from the previous embodiment in that wire bonding is performed twice on the insulator 2.
The other points are the same.
【0010】[0010]
【発明の効果】以上説明したように、本発明の半導体装
置は、チップ−リードフレーム間のワイヤボンディング
を、リードフレームが固着された絶縁体を中継点として
行うものであるので、本発明によれば、ボンディングワ
イヤのフライイングワイヤ長を短くすることができる。
従って、本発明によれば、樹脂封止の際のボンディング
ワイヤの変形を抑制することができ、隣接するボンディ
ングワイヤ同士が接触するという事故を防止することが
できる。As described above, in the semiconductor device of the present invention, the wire bonding between the chip and the lead frame is performed by using the insulator to which the lead frame is fixed as a relay point. For example, the flying wire length of the bonding wire can be shortened.
Therefore, according to the present invention, the deformation of the bonding wire at the time of resin sealing can be suppressed, and the accident that adjacent bonding wires contact each other can be prevented.
【図1】 本発明の第1の実施例の断面図。FIG. 1 is a sectional view of a first embodiment of the present invention.
【図2】 本発明の第2の実施例の断面図。FIG. 2 is a sectional view of a second embodiment of the present invention.
【図3】 従来例の断面図。FIG. 3 is a sectional view of a conventional example.
1 銅板 2 絶縁体 3 リードフレーム 4 導電性接着剤 5 チップ 6 ボンディングワイヤ 7 モールド樹脂 1 Copper Plate 2 Insulator 3 Lead Frame 4 Conductive Adhesive 5 Chip 6 Bonding Wire 7 Mold Resin
Claims (1)
半導体素子上のパッドと前記リードフレーム間がボンデ
ィングワイヤにより接続され、全体がモールド樹脂によ
り封止されている半導体装置において、前記ボンディン
グワイヤが、前記リードフレーム−前記半導体素子間に
おいて、前記絶縁体上にもボンディングされていること
を特徴とする半導体装置。1. A lead frame is fixed on an insulator,
In a semiconductor device in which a pad on a semiconductor element and the lead frame are connected by a bonding wire and the whole is sealed with a molding resin, the bonding wire is on the insulator between the lead frame and the semiconductor element. A semiconductor device which is also bonded to.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4163656A JP2795069B2 (en) | 1992-05-29 | 1992-05-29 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4163656A JP2795069B2 (en) | 1992-05-29 | 1992-05-29 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05335366A true JPH05335366A (en) | 1993-12-17 |
JP2795069B2 JP2795069B2 (en) | 1998-09-10 |
Family
ID=15778088
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4163656A Expired - Fee Related JP2795069B2 (en) | 1992-05-29 | 1992-05-29 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2795069B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4839556A (en) * | 1983-02-25 | 1989-06-13 | Rca Licensing Corporation | Cathode-ray tube having an improved shadow mask contour |
US7199477B1 (en) * | 2000-09-29 | 2007-04-03 | Altera Corporation | Multi-tiered lead package for an integrated circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6113931U (en) * | 1984-06-29 | 1986-01-27 | 関西日本電気株式会社 | semiconductor equipment |
JPH0399455A (en) * | 1989-09-05 | 1991-04-24 | Advanced Micro Devices Inc | Package of integrated circuit capsuled by high performance plastics |
-
1992
- 1992-05-29 JP JP4163656A patent/JP2795069B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6113931U (en) * | 1984-06-29 | 1986-01-27 | 関西日本電気株式会社 | semiconductor equipment |
JPH0399455A (en) * | 1989-09-05 | 1991-04-24 | Advanced Micro Devices Inc | Package of integrated circuit capsuled by high performance plastics |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4839556A (en) * | 1983-02-25 | 1989-06-13 | Rca Licensing Corporation | Cathode-ray tube having an improved shadow mask contour |
US7199477B1 (en) * | 2000-09-29 | 2007-04-03 | Altera Corporation | Multi-tiered lead package for an integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2795069B2 (en) | 1998-09-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |