JPH01206660A - Lead frame and semiconductor device utilizing same - Google Patents

Lead frame and semiconductor device utilizing same

Info

Publication number
JPH01206660A
JPH01206660A JP63032372A JP3237288A JPH01206660A JP H01206660 A JPH01206660 A JP H01206660A JP 63032372 A JP63032372 A JP 63032372A JP 3237288 A JP3237288 A JP 3237288A JP H01206660 A JPH01206660 A JP H01206660A
Authority
JP
Japan
Prior art keywords
lead frame
chip
wire connection
semiconductor chip
connection lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63032372A
Other languages
Japanese (ja)
Inventor
Nobutaka Nagai
長井　信孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63032372A priority Critical patent/JPH01206660A/en
Publication of JPH01206660A publication Critical patent/JPH01206660A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enlarge the area for mounting a semiconductor chip by a method wherein a chip bond lead frame and a wire connection lead frame are formed on different metal plates and the chip bond lead frame is arranged under the wire connection lead frame with a specified distance between the two. CONSTITUTION:A chip bond lead frame 2a, which constitutes a chip-bonding lead frame section whereto a semiconductor chip 4 is to be bonded, and a wire connection lead frame 3a, which constitutes a wire-connected lead frame section whereto a terminal on the semiconductor chip 4 is to be connected by a bonding wire 1, are so arranged that the chip bond lead frame 2a will be positioned lower and the wire connection lead frame 3a higher, with a specified gap between the two. With the device being designed as such, the semiconductor chip 4 to be installed can be larger in size.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置分野に利用される。[Detailed description of the invention] [Industrial application field] The present invention is utilized in the field of semiconductor devices.

本発明は、半導体装置を構成するものの一つであるリー
ドフレームおよびこれを用いた半導体装置に関し、特に
ごく小さな半導体装置内に、大きな半導体チップを搭載
することが必要な半導体装置のリードフレームおよびこ
れを用いた半導体装置に関する。The present invention relates to a lead frame, which is one of the components of a semiconductor device, and a semiconductor device using the lead frame, and particularly to a lead frame for a semiconductor device that requires a large semiconductor chip to be mounted in a very small semiconductor device, and the lead frame. This invention relates to a semiconductor device using.

〔概要〕〔overview〕

本発明は、半導体チップを搭載するリードフレームおよ
びこれを用いた半導体装置において、前記半導体チップ
を接着するチップ接着リードフレームと前記半導体チッ
プ上の電極を金属細線で接続するワイヤ接続リードフレ
ームとを別個に設け、前記チップ接着リードフレームを
下側に前記ワイヤ接続リードフレームを上側に所定の空
間をおいて重ねて配置した構成とすることにより、搭載
可能な半導体チップの大きさを大きくしたものである。The present invention provides a lead frame on which a semiconductor chip is mounted and a semiconductor device using the same, in which a chip adhesion lead frame for adhering the semiconductor chip and a wire connection lead frame for connecting electrodes on the semiconductor chip with thin metal wires are provided separately. The size of the semiconductor chip that can be mounted is increased by arranging the chip adhesion lead frame on the lower side and the wire connection lead frame on the upper side with a predetermined space in between. .

〔従来の技術〕[Conventional technology]

従来、この種のリードフレーム６は第４図に示すように
、−枚の金属板から構成され、半導体チップ接着のため
のチップ接着リードフレーム部２とボンディングワイヤ
接続のためのワイヤ接続リードフレーム部３とが、同一
平面に打ち抜きまたはエツチングによって形成される。Conventionally, this type of lead frame 6 is composed of two metal plates, as shown in FIG. 4, including a chip adhesion lead frame part 2 for adhering semiconductor chips and a wire connection lead frame part for bonding wire connection. 3 are formed by punching or etching on the same plane.

このリードフレーム６のチップ接着リードフレーム部２
に半導体チップを銀ペーストおよび金等によって接着し
、この半導体チップと両わき等に配置されているワイヤ
接続リードフレーム部３に細い金線等のワイヤで接続し
た後、樹脂等で封止していた。なお、同図において、５
は樹脂封止領域、７は送り穴である。Chip bonding lead frame portion 2 of this lead frame 6
A semiconductor chip is bonded with silver paste and gold, etc., and the semiconductor chip is connected to wire connection lead frame parts 3 placed on both sides with wires such as thin gold wires, and then sealed with resin or the like. Ta. In addition, in the same figure, 5
is a resin-sealed area, and 7 is a feed hole.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前述した従来のリードフレーム６は、同一金属板に、ワ
イヤ接続リードフレーム部３とチップ接着リードフレー
ム部２とが形成さているので、搭載することのできる半
導体チップの大きさが、かなり制限される欠点があった
。In the conventional lead frame 6 described above, the wire connection lead frame part 3 and the chip adhesion lead frame part 2 are formed on the same metal plate, so the size of the semiconductor chip that can be mounted is considerably limited. There were drawbacks.

本発明の目的は、前記の欠点を除去することにより、搭
載できる半導体チップの大きさを大きくてきるようにし
たリードフレームおよびこれを用いた半導体装置を提供
することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a lead frame and a semiconductor device using the same, which can increase the size of a semiconductor chip that can be mounted by eliminating the above-mentioned drawbacks.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のリードフレームは、電子回路が形成された半導
体チップを接着するチップ接着リードフレーム部と、前
記半導体チップ上の端子を金属細線で接続するワイヤ接
続リードフレーム部とを含むリードフレームにおいて、
前記チップ接着リードフレーム部を構成するチップ接着
リードフレームと、前記ワイヤ接続リードフレーム部を
構成するワイヤ接続リードフレームとを別個に設け、前
記ワイヤ接続リードフレームは前記チップ接着リードフ
レームの上側に所定の空間を挟んで重ねて配置された構
造であることを特徴とする。The lead frame of the present invention includes a chip adhesion lead frame part for adhering a semiconductor chip on which an electronic circuit is formed, and a wire connection lead frame part for connecting terminals on the semiconductor chip with thin metal wires.
A chip adhesion lead frame constituting the chip adhesion lead frame portion and a wire connection lead frame constituting the wire connection lead frame portion are provided separately, and the wire connection lead frame is provided above the chip adhesion lead frame in a predetermined manner. They are characterized by a structure in which they are arranged one on top of the other with a space in between.

本発明の半導体装置は、　半導体チップがチップ接着リ
ードフレーム部上に接着され、前記半導体チップ上の端
子が金属細線でワイヤ接続リードフレーム部に接続され
、樹脂封じされた構造を有する半導体装置において、前
記チップ接着リードフレーム部が所定の間隔をおいて前
記ワイヤ接続リードフレーム部の下側に設けられたこと
を特徴とする。The semiconductor device of the present invention has a structure in which a semiconductor chip is bonded onto a chip adhesion lead frame portion, terminals on the semiconductor chip are connected to a wire connection lead frame portion using thin metal wires, and the semiconductor device is sealed with resin. The chip adhesion lead frame part is provided below the wire connection lead frame part at a predetermined interval.

〔作用〕[Effect]

チップ接着リードフレームが、所定の空間を挟んで、ワ
イヤ接続リードフレームの上側に配置される。A chip adhesive lead frame is placed above the wire connection lead frame with a predetermined space in between.

従って、半導体チップの寸法が大きくなっても、それに
よりワイヤ接続リードフレーム部が影響を受けることは
少なくなり、搭載可能な半導体チップの大きさを大きく
することができる。Therefore, even if the size of the semiconductor chip increases, the wire connection lead frame portion is less affected by the increase in size, and the size of the semiconductor chip that can be mounted can be increased.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.

第１図は本発明のリードフレームの第一実施例および本
発明の半導体装置の一実施例の要部を示す模式的縦断面
図で、半導体チップが搭載された状態を示す。第２図（
ａ）および（ｂ）はそれぞれそのワイヤ接続リードフレ
ームおよびチップ接着リードフレームを示す平面図であ
る。FIG. 1 is a schematic longitudinal cross-sectional view showing essential parts of a first embodiment of a lead frame of the present invention and an embodiment of a semiconductor device of the present invention, with a semiconductor chip mounted thereon. Figure 2 (
Figures a) and (b) are plan views showing the wire connection lead frame and the chip adhesion lead frame, respectively.

本実−実施例のリードフレーム６は、半導体チップ４を
接着するチップ接着リードフレーム部を構成するチップ
接着リードフレーム２ａと、前記半導体チップ上の端子
をボンディングワイヤ１で接続するワイヤ接続リードフ
レーム部を構成するワイヤ接続リードフレーム３ａとが
、所定の空間を挟んで、チップ接着リードフレーム２ａ
が下側、ワイヤ接続リードフレーム３ａが上側に所定位
置を保って重ねられ、例えばリードフレームの外周にお
いて圧着された構造となっている。ここで、所定の空間
は、チップ接着リードフレーム２ａに半導体チップ４を
接着後において、半導体チップ４とワイヤ接続リードフ
レーム３ａが触れない程度の空間とする。The lead frame 6 of this embodiment includes a chip adhesion lead frame 2a that constitutes a chip adhesion lead frame section to which a semiconductor chip 4 is bonded, and a wire connection lead frame section that connects terminals on the semiconductor chip with bonding wires 1. The wire connection lead frame 3a constituting the
is on the lower side, and the wire connection lead frame 3a is placed on the upper side while maintaining a predetermined position, and is crimped, for example, on the outer periphery of the lead frame. Here, the predetermined space is such that the semiconductor chip 4 and the wire connection lead frame 3a do not touch after the semiconductor chip 4 is bonded to the chip bonding lead frame 2a.

この構造により、半導体チップ４の面積を大きなものも
搭載できる。さらに半導体チップ４がボンディングワイ
ヤ１より低い位置にあるため半導体チップ４とボンディ
ングワイヤ１とが誤って接触し短絡することがなくなる
利点も得られる。With this structure, it is possible to mount a semiconductor chip 4 having a large area. Furthermore, since the semiconductor chip 4 is located at a lower position than the bonding wire 1, there is an advantage that the semiconductor chip 4 and the bonding wire 1 will not come into contact with each other accidentally and cause a short circuit.

また、本実施例の半導体装置は、前述のようにして半導
体チップ４がチップ接着リードフレーム部に接着され、
半導体チップ４上の電極がボンディングワイヤ１でワイ
ヤ接続リードフレーム部に接続されたものを、樹脂封止
領域５に示す部分を図外の樹脂で樹脂封じを行うことで
得られる。Further, in the semiconductor device of this embodiment, the semiconductor chip 4 is bonded to the chip bonding lead frame portion as described above,
The electrode on the semiconductor chip 4 is connected to the wire connection lead frame portion by the bonding wire 1, and the portion shown in the resin sealing region 5 is resin-sealed with a resin not shown.

第３図は本発明のリードフレームの第二実施例の要部を
示す平面図である。第３図において、上段のリードフレ
ームはワイヤ接続リードフレーム３ａであり、下段のリ
ードフレームはチップ接着リードフレーム２ａである。FIG. 3 is a plan view showing essential parts of a second embodiment of the lead frame of the present invention. In FIG. 3, the upper lead frame is a wire connection lead frame 3a, and the lower lead frame is a chip bonding lead frame 2a.

この第二実施例は、前述の第一実施例において、チップ
接着リードフレーム２ａは同一で、ワイヤ接続リードフ
レーム３ａとして多くの端子をもつものに変えたもので
ある。本第二実施例によれば、多くの端子をもつ半導体
チップを搭載することができる。さらに、引き出した電
極端子に種々の配線も可能である。またチップ接着リー
ドフレーム２ａとして、半導体チップを複数搭載できる
リードフレームを使用することにより、複雑な電子回路
も構成することができるという利点がある。In this second embodiment, the chip adhesion lead frame 2a is the same as that of the first embodiment described above, but a wire connection lead frame 3a having many terminals is used instead. According to the second embodiment, a semiconductor chip having many terminals can be mounted. Furthermore, various wirings can be made to the drawn-out electrode terminals. Further, by using a lead frame on which a plurality of semiconductor chips can be mounted as the chip adhesion lead frame 2a, there is an advantage that a complicated electronic circuit can be constructed.

本発明の特徴は、第１図、第２図（ａ）および（ｂ）、
第３図において、チップ接着リードフレーム２ａおよび
ワイヤ接続リードフレーム３ａを別個に設け、チップ接
着リードフレーム２ａを所定の間隔をおいてワイヤ接続
リードフレーム３ａの下側に配置したことにある。The features of the present invention are as shown in FIGS. 1, 2 (a) and (b),
In FIG. 3, a chip adhesion lead frame 2a and a wire connection lead frame 3a are provided separately, and the chip adhesion lead frame 2a is placed below the wire connection lead frame 3a at a predetermined interval.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、電子回路を構成してい
る半導体チップを搭載するリードフレームおよびそれを
用いた半導体装置において、チップ接着リードフレーム
とワイヤ接続リードフレームとを別個の金属板に形成し
、所定の間隔を挟んで前記チップ接着リードフレームを
前記ワイヤ接続リードフレームの下側に配置した構造と
することにより、半導体チップの搭載可能な面積が著し
く大きくなる効果がある。またリードをより多く引き出
せるようになり、ポンチ°イングワイヤとチップの接触
による短絡も少なくなる効果がある。As explained above, the present invention provides a lead frame on which a semiconductor chip constituting an electronic circuit is mounted, and a semiconductor device using the same, in which a chip adhesion lead frame and a wire connection lead frame are formed on separate metal plates. However, by arranging the chip adhesion lead frame below the wire connection lead frame with a predetermined spacing between them, the area on which the semiconductor chip can be mounted can be significantly increased. It also allows more leads to be pulled out, which has the effect of reducing short circuits caused by contact between the punching wire and the chip.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明のリードフレームの第一実施例および本
発明の半導体装置の一実施例の要部を示す模式的縦断面
図。 第２図（ａ）および（ｂ）はそれぞれそのワイヤ接続リ
ードフレームおよびチップ接着リードフレームを示す平
面図。 第３図は本発明のリードフレームの第二実施例の要部を
示す平面図。 第４図は従来のリードフレームを示す平面図。 １・・・ボンディングワイヤ、２・・・チップ接着り−
ドフレーム部、２ａ・・・チップ接着リードフレーム、
３・・・ワイヤ接続リードフレーム部、３ａ・・・ワイ
ヤ接続リードフレーム、４・・・半導体チップ、５・・
・樹脂封止領域、６・・・リードフレーム、７・・・送
り穴。FIG. 1 is a schematic longitudinal cross-sectional view showing essential parts of a first embodiment of a lead frame of the present invention and an embodiment of a semiconductor device of the present invention. FIGS. 2(a) and 2(b) are plan views showing the wire connection lead frame and the chip adhesion lead frame, respectively. FIG. 3 is a plan view showing the main parts of a second embodiment of the lead frame of the present invention. FIG. 4 is a plan view showing a conventional lead frame. 1...Bonding wire, 2...Chip adhesion-
frame part, 2a...chip adhesion lead frame,
3... Wire connection lead frame portion, 3a... Wire connection lead frame, 4... Semiconductor chip, 5...
- Resin sealing area, 6... Lead frame, 7... Sprocket hole.

Claims (1)

【特許請求の範囲】 １、電子回路が形成された半導体チップを接着するチッ
プ接着リードフレーム部と、前記半導体チップ上の端子
を金属細線で接続するワイヤ接続リードフレーム部とを
含むリードフレームにおいて、前記チップ接着リードフ
レーム部を構成するチップ接着リードフレーム（２ａ）
と、前記ワイヤ接続リードフレーム部を構成するワイヤ
接続リードフレーム（３ａ）とを別個に設け、 前記ワイヤ接続リードフレームは前記チップ接着リード
フレームの上側に所定の空間を挟んで重ねて配置された
構造である ことを特徴とするリードフレーム。 ２、半導体チップがチップ接着リードフレーム部上に接
着され、前記半導体チップ上の端子が金属細線でワイヤ
接続リードフレーム部に接続され、樹脂封じされた構造
を有する半導体装置において、前記チップ接着リードフ
レーム部が所定の間隔をおいて前記ワイヤ接続リードフ
レーム部の下側に設けられた ことを特徴とする半導体装置。[Scope of Claims] 1. A lead frame including a chip adhesion lead frame part for adhering a semiconductor chip on which an electronic circuit is formed, and a wire connection lead frame part for connecting terminals on the semiconductor chip with thin metal wires, Chip adhesion lead frame (2a) constituting the chip adhesion lead frame section
and a wire connection lead frame (3a) constituting the wire connection lead frame portion are separately provided, and the wire connection lead frame is arranged above the chip adhesion lead frame with a predetermined space in between. A lead frame characterized by: 2. In a semiconductor device having a structure in which a semiconductor chip is bonded onto a chip bonding lead frame portion, terminals on the semiconductor chip are connected to a wire connection lead frame portion with thin metal wires, and the semiconductor chip is sealed with resin, the chip bonding lead frame portion is bonded. A semiconductor device characterized in that a portion is provided below the wire connection lead frame portion at a predetermined interval.
JP63032372A 1988-02-15 1988-02-15 Lead frame and semiconductor device utilizing same Pending JPH01206660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63032372A JPH01206660A (en) 1988-02-15 1988-02-15 Lead frame and semiconductor device utilizing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63032372A JPH01206660A (en) 1988-02-15 1988-02-15 Lead frame and semiconductor device utilizing same

Publications (1)

Publication Number Publication Date
JPH01206660A true JPH01206660A (en) 1989-08-18

Family

ID=12357115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63032372A Pending JPH01206660A (en) 1988-02-15 1988-02-15 Lead frame and semiconductor device utilizing same

Country Status (1)

Country Link
JP (1) JPH01206660A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03147356A (en) * 1989-11-01 1991-06-24 Mitsubishi Electric Corp Lead frame for semiconductor device
US5592019A (en) * 1994-04-19 1997-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and module
EP0987758A3 (en) * 1991-12-27 2000-05-24 Fujitsu Limited Semiconducter device and method of producing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03147356A (en) * 1989-11-01 1991-06-24 Mitsubishi Electric Corp Lead frame for semiconductor device
EP0987758A3 (en) * 1991-12-27 2000-05-24 Fujitsu Limited Semiconducter device and method of producing the same
US5592019A (en) * 1994-04-19 1997-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and module

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