JPH05327293A - Mounting accuracy confirming land for chip - Google Patents
Mounting accuracy confirming land for chipInfo
- Publication number
- JPH05327293A JPH05327293A JP4133235A JP13323592A JPH05327293A JP H05327293 A JPH05327293 A JP H05327293A JP 4133235 A JP4133235 A JP 4133235A JP 13323592 A JP13323592 A JP 13323592A JP H05327293 A JPH05327293 A JP H05327293A
- Authority
- JP
- Japan
- Prior art keywords
- land
- chip
- mounting accuracy
- mount
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Supply And Installment Of Electrical Components (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子機器の回路にチッ
プを実装するチップマウンターのチップの実装精度確認
用ランドに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip mounting accuracy confirmation land of a chip mounter for mounting a chip on a circuit of an electronic device.
【０００２】[0002]
【従来の技術】従来、チップマウント実装精度の確認に
は、製品基板を用いて目視で確認していた。2. Description of the Related Art Conventionally, the accuracy of chip mount mounting has been checked visually by using a product substrate.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記従
来の製品基板での実装精度確認では、マウントズレ量の
目安となるものがないために、オペレーターの経験が必
要であり、誰もが容易に精度を確認することは難しいと
いう問題点があった。However, in the above-mentioned conventional mounting accuracy confirmation on the product board, there is no reference for the amount of mount deviation, so the experience of the operator is required, and everyone can easily obtain the accuracy. There was a problem that it was difficult to confirm.
【０００４】本発明は、このような従来の問題を解決す
るものであり、マウントズレ量の目安を設けて、これと
の比較によって、誰にでも容易にチップの実装精度を確
認できると共に、高い実装精度を確保することのできる
チップの実装精度確認用ランドを提供することを目的と
する。The present invention solves such a conventional problem. By providing a standard for the amount of mount deviation and comparing it with this, anyone can easily confirm the mounting accuracy of the chip and it is high. An object is to provide a land for confirming the mounting accuracy of a chip that can ensure the mounting accuracy.
【０００５】[0005]
【課題を解決するための手段】この目的を達成するため
に、本発明のチップの実装精度確認用ランドは、基板上
にチップと同サイズのメインランドを設け、このメイン
ランドの外周に、マウントズレ量目安枠を隔てて補助ラ
ンドを設け、この補助ランドにメインランドの中心線を
設けた構成を有している。To achieve this object, the chip mounting accuracy confirmation land of the present invention is provided with a main land of the same size as the chip on a substrate, and a mount is mounted on the outer periphery of the main land. Auxiliary lands are provided with a displacement amount reference frame, and the center line of the main land is provided on the auxiliary lands.
【０００６】[0006]
【作用】従って、本発明によれば、チップを実装精度確
認用ランドに重ねて、顕微鏡等を用いることによって、
実装精度が良ければ、チップがメインランドと重なって
いることを確認し、チップがズレているときは、マウン
トズレ量目安枠との比較によってチップのズレ量を判断
することができる。Therefore, according to the present invention, by stacking the chip on the mounting accuracy confirmation land and using a microscope or the like,
If the mounting accuracy is good, it is possible to confirm that the chip overlaps with the main land, and if the chip is misaligned, the amount of chip misalignment can be determined by comparison with the mount misalignment amount standard frame.
【０００７】[0007]
【実施例】以下に本発明の実施例について図１乃至図３
を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
Will be described with reference to.
【０００８】図において、１は１００５チップ５がマウ
ントされる１．０×０．５mmのメインランドで基板上に
設けられており、このメインランド１の外周に０．１５
mmのマウントズレ量目安枠２を隔てて補助ランド３が設
けられている。そして補助ランド３はメインランド１の
中心線４を備えている。In the figure, reference numeral 1 denotes a 1.0 × 0.5 mm main land on which a 1005 chip 5 is mounted, which is provided on a substrate.
Auxiliary lands 3 are provided separated by a frame 2 for indicating a mount misalignment amount of mm. The auxiliary land 3 has the center line 4 of the main land 1.
【０００９】以上のように構成されたチップの実装精度
確認用ランドを用いてチップマウント実装精度の確認を
するには、チップ５を実装精度確認用ランドに重ねて、
顕微鏡等を用いて比較することによって、図２に示すよ
うにチップ５がメインランド１と重なっていれば、実装
精度が良いと判定することができる。またチップ５が図
３に示す状態にズレているときは、チップ５はマウント
ズレ量目安枠２の寸法０．１５mmだけズレていると判断
することができる。In order to confirm the mounting accuracy of the chip mount using the mounting accuracy confirmation land of the chip constructed as described above, the chip 5 is placed on the mounting accuracy confirmation land.
By using a microscope or the like for comparison, if the chip 5 overlaps the main land 1 as shown in FIG. 2, it can be determined that the mounting accuracy is good. When the chip 5 is displaced to the state shown in FIG. 3, it can be judged that the chip 5 is displaced by the dimension of the mount displacement amount reference frame 2 by 0.15 mm.
【００１０】以上のように本実施例によれば、このチッ
プの実装精度確認用ランドは、チップ５がマウントズレ
量目安枠２のどの位置にあるかのズレ量を読み取ること
によって、チップ５の実装精度を確認するものであり、
これによってチップ５の実装精度を高めることが可能に
なる。As described above, according to this embodiment, the mounting accuracy confirmation land of this chip reads the displacement amount of the position of the mount displacement amount standard frame 2 of the chip 5 to detect the displacement of the chip 5. To check the mounting accuracy,
This makes it possible to improve the mounting accuracy of the chip 5.
【００１１】なお、本発明のランドを設けた基板には、
基準穴とランドとの寸法、ランド相互間の寸法などの基
準寸法の精度が必要である。The substrate provided with the land of the present invention,
The accuracy of reference dimensions such as the dimension between the reference hole and the land and the dimension between the lands is required.
【００１２】[0012]
【発明の効果】以上のように本発明は、上記実施例より
明らかなように、基板上にチップと同サイズのメインラ
ンドを設け、このメインランドの外周に、マウントズレ
量目安枠を隔てて補助ランドを設け、この補助ランドに
メインランドの中心線を設けることにより、チップを実
装精度確認用ランドに重ねて、顕微鏡等を用いてチップ
とメインランド及びマウントズレ量目安枠とを比較する
ことによって、チップのズレ量を読み取ることができ
て、チップの実装精度を確認することができると共に、
チップの実装精度を高めることができる優れたチップの
実装精度確認用ランドを実現できる。As described above, according to the present invention, as is clear from the above embodiment, the main land having the same size as the chip is provided on the substrate, and the mount deviation amount reference frame is provided on the outer periphery of the main land. By providing an auxiliary land and providing the center line of the main land on this auxiliary land, stack the chip on the land for confirmation of mounting accuracy, and compare the chip with the main land and the mount deviation amount standard frame using a microscope etc. With this, it is possible to read the amount of misalignment of the chip and confirm the mounting accuracy of the chip.
An excellent chip mounting accuracy confirmation land capable of improving chip mounting accuracy can be realized.
【図１】本発明の実施例におけるチップの実装精度確認
用ランドの平面図FIG. 1 is a plan view of a chip mounting accuracy confirmation land according to an embodiment of the present invention.
【図２】同作用説明図FIG. 2 is an explanatory view of the same action.
【図３】同作用説明図FIG. 3 is an explanatory view of the same operation
１ メインランド ２ マウントズレ量目安枠 ３ 補助ランド ４ メインランド中心線 ５ １００５チップ 1 Mainland 2 Mount misalignment standard frame 3 Auxiliary land 4 Mainland centerline 5 1005 chips
Claims (1)
ドを設け、このメインランドの外周に、マウントズレ量
目安枠を隔てて補助ランドを設け、この補助ランドにメ
インランドの中心線を設けたことを特徴とするチップの
実装精度確認用ランド。1. A main land of the same size as a chip is provided on a substrate, an auxiliary land is provided on the outer periphery of the main land with a mount deviation amount reference frame therebetween, and a center line of the main land is provided on the auxiliary land. A land for checking the mounting accuracy of a chip, which is characterized by
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4133235A JPH05327293A (en) | 1992-05-26 | 1992-05-26 | Mounting accuracy confirming land for chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4133235A JPH05327293A (en) | 1992-05-26 | 1992-05-26 | Mounting accuracy confirming land for chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05327293A true JPH05327293A (en) | 1993-12-10 |
Family
ID=15099873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4133235A Pending JPH05327293A (en) | 1992-05-26 | 1992-05-26 | Mounting accuracy confirming land for chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05327293A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005064423A (en) * | 2003-08-20 | 2005-03-10 | Nec Tokin Corp | Chip-type electronic component and its identifying method |
| US8525042B2 (en) | 2009-01-21 | 2013-09-03 | Fujitsu Limited | Printed circuit board and printed circuit board unit |
-
1992
- 1992-05-26 JP JP4133235A patent/JPH05327293A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005064423A (en) * | 2003-08-20 | 2005-03-10 | Nec Tokin Corp | Chip-type electronic component and its identifying method |
| US8525042B2 (en) | 2009-01-21 | 2013-09-03 | Fujitsu Limited | Printed circuit board and printed circuit board unit |
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