JPH05299011A - Field emission component and its manufacture - Google Patents
Field emission component and its manufactureInfo
- Publication number
- JPH05299011A JPH05299011A JP9942092A JP9942092A JPH05299011A JP H05299011 A JPH05299011 A JP H05299011A JP 9942092 A JP9942092 A JP 9942092A JP 9942092 A JP9942092 A JP 9942092A JP H05299011 A JPH05299011 A JP H05299011A
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- layer
- gate
- cathode conductor
- field emission
- emitter
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電界放出素子（Field
Emission Cathodes,以下ＦＥＣと呼ぶ。）と、その製造
方法に関するものである。本発明のＦＥＣは、蛍光表示
装置、ＣＲＴ、電子顕微鏡、電子ビーム露光装置等の各
種電子ビーム応用装置の電子源として有用である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission device (Field
Emission Cathodes, hereinafter referred to as FEC. ) And the manufacturing method thereof. The FEC of the present invention is useful as an electron source for various electron beam application devices such as fluorescent display devices, CRTs, electron microscopes, and electron beam exposure devices.
【０００２】[0002]
【従来の技術】図２は、特開平１−１５４４２６号で開
示されたＦＥＣである。基板１００の上にはカソード導
体１０１が形成され、その上には抵抗層１０２が形成さ
れている。抵抗層１０２の上には絶縁層１０３とゲート
１０４が順に積層されている。絶縁層１０３とゲート１
０４にはホールが形成され、ホール内の抵抗層１０２上
にはコーン形状のエミッタ１０５が形成されている。2. Description of the Related Art FIG. 2 shows an FEC disclosed in Japanese Patent Laid-Open No. 1-154426. A cathode conductor 101 is formed on the substrate 100, and a resistance layer 102 is formed thereon. An insulating layer 103 and a gate 104 are sequentially stacked on the resistance layer 102. Insulating layer 103 and gate 1
A hole is formed in 04, and a cone-shaped emitter 105 is formed on the resistance layer 102 in the hole.
【０００３】上記の構造において、前記抵抗層１０２は
多数形成されたエミッタ１０５について共通に設けられ
るものであり、カソード導体１０１上に連続して形成さ
れている。また該抵抗層１０２は、Ｉｎ2 Ｏ3 ，Ｆｅ2
Ｏ3 ，ＺｎＯ，Ｎｉ‐Ｃｒ合金、または不純物をドープ
したＳｉであり、抵抗率が１×１０2 Ω・ｃｍ〜１×１
０6 Ω・ｃｍとなっている。In the above structure, the resistance layer 102 is commonly provided for the many emitters 105 formed and is continuously formed on the cathode conductor 101. The resistance layer 102 is made of In 2 O 3 , Fe 2
O 3 , ZnO, Ni—Cr alloy, or Si doped with impurities and having a resistivity of 1 × 10 2 Ω · cm to 1 × 1
It is 0 6 Ω · cm.
【０００４】図３は、前記ＦＥＣの製造工程を示してい
る。まず、基板１００上に、カソード導体１０１と抵抗
層１０２と絶縁層１０３とゲート１０４を、順次積層さ
せる。次に、同図（ａ）に示すように、エッチングによ
ってゲート１０４と絶縁層１０３にホール１０６を形成
する。FIG. 3 shows the manufacturing process of the FEC. First, the cathode conductor 101, the resistance layer 102, the insulating layer 103, and the gate 104 are sequentially stacked on the substrate 100. Next, as shown in FIG. 4A, holes 106 are formed in the gate 104 and the insulating layer 103 by etching.
【０００５】図３（ｂ）に示すように、基板１００に対
して所定角度θをなす斜め上方の位置から、ゲート１０
４の表面にＮｉ又はＡｌを斜め蒸着させ、剥離層１０７
を形成する。Ｎｉ又はＡｌはゲート１０４の表面のみに
蒸着し、絶縁層１０３のホール１０６内には入らない。As shown in FIG. 3B, the gate 10 is moved from a position diagonally above the substrate 100 at a predetermined angle θ.
4. Ni or Al is obliquely vapor-deposited on the surface of No. 4, and the peeling layer 107
To form. Ni or Al is vapor-deposited only on the surface of the gate 104 and does not enter the hole 106 of the insulating layer 103.
【０００６】そして、図３（ｃ）に示すように、上方か
らエミッタ材料を蒸着してホール１０６内にコーン形状
のエミッタ１０５を形成し、その後、図３（ｄ）に示す
ように剥離層１０７とともに剥離層１０７上のエミッタ
材料を除去する。Then, as shown in FIG. 3C, an emitter material is vapor-deposited from above to form a cone-shaped emitter 105 in the hole 106, and thereafter, a peeling layer 107 is formed as shown in FIG. 3D. At the same time, the emitter material on the peeling layer 107 is removed.
【０００７】[0007]
【発明が解決しようとする課題】前述した従来のＦＥＣ
によれば、抵抗層１０２が共通であるために各エミッタ
１０５が電気的に独立しておらず、あるエミッタがゲー
トに接触して破壊すると損傷が抵抗層１０２にも及び、
すべてのエミッタが作用しなくなってしまうことがあっ
た。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
According to the above, since the resistance layer 102 is common, the respective emitters 105 are not electrically independent, and when a certain emitter comes into contact with the gate and breaks, damage is also applied to the resistance layer 102,
Sometimes all emitters would stop working.
【０００８】前述したＦＥＣの従来の製造方法によれ
ば、ゲート１０４上に剥離層１０７を形成するためにＮ
ｉ又はＡｌの斜め蒸着を行なっていた。この方法による
と、基板が大きい場合には、蒸着源と基板の各部との距
離が異なってくるため、基板上の位置によって形成され
る剥離層の厚さにばらつきが生じる。このような剥離層
の厚さのばらつきは開口径のばらつきにつながり、ホー
ル内に形成されるエミッタの高さにばらつきを生じさせ
るという問題があった。また、このような斜め蒸着法に
よる製造方法は非常に煩雑で量産性がないという問題も
あった。According to the conventional manufacturing method of the FEC described above, N is formed in order to form the release layer 107 on the gate 104.
Diagonal vapor deposition of i or Al was performed. According to this method, when the substrate is large, the distance between the vapor deposition source and each part of the substrate is different, so that the thickness of the peeling layer formed varies depending on the position on the substrate. Such a variation in the thickness of the peeling layer leads to a variation in the opening diameter, which causes a variation in the height of the emitter formed in the hole. Further, there is a problem that such a manufacturing method by the oblique vapor deposition method is very complicated and has no mass productivity.
【０００９】本発明は、エミッタごとに独立した抵抗層
を有するＦＥＣと、このようなＦＥＣを斜め蒸着法を用
いずに効率よく製造できる方法を提供することを目的と
している。It is an object of the present invention to provide an FEC having an independent resistance layer for each emitter, and a method capable of efficiently manufacturing such an FEC without using an oblique evaporation method.
【００１０】[0010]
【課題を解決するための手段】本発明の電界放出素子
は、絶縁基板上に形成されたカソード導体と、前記カソ
ード導体上に形成されて多数の空孔を有する絶縁層と、
前記各空孔内の前記カソード導体上に互いに独立して設
けられた抵抗層と、前記各抵抗層上に形成されたコーン
形状のエミッタと、前記絶縁層上に形成されたゲートを
有している。A field emission device according to the present invention comprises a cathode conductor formed on an insulating substrate, an insulating layer formed on the cathode conductor and having a large number of holes.
A resistance layer provided independently of each other on the cathode conductor in each hole, a cone-shaped emitter formed on each resistance layer, and a gate formed on the insulating layer. There is.
【００１１】また本発明によれば、前記電界放出素子に
おいて、Ｐ又はＢをドープして１×１０2 〜１×１０7
Ω・ｃｍの抵抗率を有するＳｉで前記抵抗層を形成して
もよい。Further, according to the present invention, in the above field emission device, P or B is doped to 1 × 10 2 to 1 × 10 7.
The resistance layer may be formed of Si having a resistivity of Ω · cm.
【００１２】本発明に係る電界放出素子の製造方法は、
絶縁基板上に所定パターンのカソード導体を形成する工
程と、前記カソード導体上に絶縁層と金属薄膜を順次積
層させる工程と、前記金属薄膜及び絶縁層をエッチング
してゲート及び多数の空孔を形成する工程と、前記ゲー
トと前記各空孔内の前記カソード導体に正蒸着によって
Ｓｉ層を形成する工程と、前記ゲートのＳｉ薄膜を陽極
酸化法で酸化してＳｉＯ2 剥離層を形成する工程と、前
記絶縁基板に真上からエミッタ材料を正蒸着させて前記
各空孔内の各Ｓｉ薄膜上にコーン形状のエミッタを形成
する工程と、前記ＳｉＯ2 剥離層上のエミッタ材料をＳ
ｉＯ2 剥離層とともに除去する工程を有している。The method of manufacturing a field emission device according to the present invention is
A step of forming a cathode conductor having a predetermined pattern on an insulating substrate, a step of sequentially laminating an insulating layer and a metal thin film on the cathode conductor, and a step of etching the metal thin film and the insulating layer to form a gate and a large number of holes. A step of forming a Si layer on the gate and the cathode conductor in each of the holes by positive vapor deposition, and a step of oxidizing the Si thin film of the gate by an anodic oxidation method to form a SiO 2 peeling layer. a step of forming an emitter cone shape on each Si thin film of the insulating substrate within the respective holes by a positive depositing an emitter material from above, the emitter material on the SiO 2 release layer S
It has a step of removing it together with the iO 2 peeling layer.
【００１３】[0013]
【実施例】本発明の一実施例を図１によって説明する。
図１（ａ）に示すように、ガラス等の絶縁基板１上にＮ
ｂ，Ｍｏ，Ａｌ等の金属薄膜をベタに形成し、フォトリ
ソグラフィーの手法で所望のパターンに加工し、カソー
ド導体２を得る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 1A, N is formed on the insulating substrate 1 such as glass.
A metal thin film of b, Mo, Al or the like is solidly formed and processed into a desired pattern by a photolithography method to obtain a cathode conductor 2.
【００１４】前記カソード導体２を覆って前記絶縁基板
１上にＳｉＯ2 からなる絶縁層３を形成する。該絶縁層
３の形成はスパッタ法やＣＶＤ法で行ない、膜厚は約
１．０μｍとする。An insulating layer 3 made of SiO 2 is formed on the insulating substrate 1 so as to cover the cathode conductor 2. The insulating layer 3 is formed by a sputtering method or a CVD method and has a film thickness of about 1.0 μm.
【００１５】前記絶縁層３の表面に、ゲートの材料であ
るＮｂ又はＭｏをスパッタ法によって約０．４μｍの厚
さに成膜し、ゲート層を形成する。On the surface of the insulating layer 3, a gate material, Nb or Mo, is deposited by sputtering to a thickness of about 0.4 μm to form a gate layer.
【００１６】リアクティブイオンエッチング（ＲＩＥ）
法で前記ゲート層に直径約１．０μｍの多数の孔４ａを
形成し、図１（ａ）に示すようなゲート４を形成する。Reactive ion etching (RIE)
By the method, a large number of holes 4a having a diameter of about 1.0 μm are formed in the gate layer to form the gate 4 as shown in FIG.
【００１７】前記カソード導体２があらわれるまで前記
絶縁層３を前記ゲート４の孔４ａからエッチングし、空
孔５を形成する。エッチングは、バッファード弗酸（Ｂ
ＨＦ）等を用いたウェットエッチングでもよいし、ＣＨ
Ｆ3 等のガスを用いてＲＩＥ法で行うドライエッチング
でもよい。この工程の後、レジストを剥離すれば、図１
（ａ）に示す構造が得られる。The insulating layer 3 is etched from the hole 4a of the gate 4 until the cathode conductor 2 is exposed, and a hole 5 is formed. For etching, use buffered hydrofluoric acid (B
Wet etching using HF) or CH
Dry etching performed by the RIE method using a gas such as F 3 may be used. After this step, if the resist is peeled off, as shown in FIG.
The structure shown in (a) is obtained.
【００１８】図１（ｂ）に示すように、Ｐ又はＢをドー
プしたＳｉを、エレクトロビーム蒸着（ＥＢ蒸着）法に
よって上方から絶縁基板１に正蒸着させる。ここで正蒸
着とは、絶縁基板１の真上に蒸着源を配置し、ゲート４
に対して垂直にＳｉを蒸着させることを指す。この正蒸
着法によれば、従来行われていた斜め蒸着と異なり、絶
縁基板１が比較的大きくても、蒸着源と絶縁基板１の各
部との距離には大きなばらつきは生じない。As shown in FIG. 1 (b), Si doped with P or B is positively vapor-deposited on the insulating substrate 1 from above by an electro-beam vapor deposition (EB vapor deposition) method. Here, the normal vapor deposition means that the vapor deposition source is arranged right above the insulating substrate 1 and the gate 4
It means that Si is vapor-deposited perpendicularly to. According to this normal vapor deposition method, unlike the conventional oblique vapor deposition, even if the insulating substrate 1 is relatively large, the distance between the vapor deposition source and each part of the insulating substrate 1 does not greatly vary.
【００１９】前記Ｓｉの正蒸着により、図１（ｂ）に示
すように、ゲート４の上面及び空孔５内のカソード電極
２上にはＳｉ層６及びＳｉからなる抵抗層７が形成され
る。その厚さは抵抗率が１×１０2 Ω・ｃｍ〜１×１０
7 Ω・ｃｍとなる寸法に設定する。As shown in FIG. 1B, a Si layer 6 and a resistance layer 7 made of Si are formed on the upper surface of the gate 4 and the cathode electrode 2 in the hole 5 by the normal vapor deposition of Si. .. The thickness has a resistivity of 1 × 10 2 Ω · cm to 1 × 10
Set the dimensions to be 7 Ω · cm.
【００２０】陽極酸化法を用い、ゲート４上のＳｉ層の
みを酸化してＳｉＯ2 とし、剥離層８を形成する。即
ち、０．０４ＮのＫＮＯ3 溶液中にエチレングリコール
を添加した溶液を用い、前記絶縁基板１のゲート４を陽
極とし、Ｐｔ又はＳＵＳの不動態電極を陰極として、１
〜２５ｍＡ／ｃｍ2 の電流密度で陽極酸化を行なう。Using the anodic oxidation method, only the Si layer on the gate 4 is oxidized to SiO 2 and the peeling layer 8 is formed. That is, a solution obtained by adding ethylene glycol to a 0.04N KNO 3 solution was used, and the gate 4 of the insulating substrate 1 was used as an anode, and a Pt or SUS passivation electrode was used as a cathode.
Anodization is performed at a current density of ˜25 mA / cm 2 .
【００２１】図１（ｃ）に示すように、ゲート４のＳｉ
層６はＳｉＯ2 に酸化し、剥離層８が形成される。この
場合、ゲート４上のＳｉ層６のみに通電し、カソード電
極２上の抵抗層７には通電しない。従って、Ｓｉ抵抗層
７は変化しない。As shown in FIG. 1C, the Si of the gate 4 is
Layer 6 is oxidized to SiO 2 to form release layer 8. In this case, only the Si layer 6 on the gate 4 is energized, and the resistance layer 7 on the cathode electrode 2 is not energized. Therefore, the Si resistance layer 7 does not change.
【００２２】次に、図１（ｃ）に示すように、空孔５の
真上から、エミッタ材料のＭｏを正蒸着させる。空孔５
内の抵抗層７上にはコーン形状のエミッタ９が形成さ
れ、剥離層８上にはＭｏの蒸着層１０が形成される。Next, as shown in FIG. 1 (c), Mo, which is an emitter material, is vapor-deposited directly above the holes 5. Hole 5
A cone-shaped emitter 9 is formed on the internal resistance layer 7, and a vapor deposition layer 10 of Mo is formed on the peeling layer 8.
【００２３】次に、バッファード弗酸（ＢＨＦ）を用い
て剥離層８を除去し、不要なＭｏの蒸着層１０を除去す
る。この時、ＢＨＦが空孔５内にも入り、絶縁層３を再
びエッチングするので、空孔５はさらに広げられて図１
（ｄ）に示すような断面形状のスピント形のＦＥＣが得
られる。Next, the peeling layer 8 is removed using buffered hydrofluoric acid (BHF), and the unnecessary Mo vapor deposition layer 10 is removed. At this time, BHF also enters the holes 5 and etches the insulating layer 3 again, so that the holes 5 are further widened and the structure shown in FIG.
A Spindt-type FEC having a cross-sectional shape as shown in (d) is obtained.
【００２４】[0024]
【発明の効果】本発明の電界放出素子によれば、エミッ
タの１個ごとにそれぞれ独立した抵抗層があるので、シ
ョートによって過電流が流れても、ショートした部分の
みが破壊するだけで、他のエミッタに損傷が波及するこ
とがない。従って寿命の長い電界放出素子が得られる。According to the field emission device of the present invention, since each emitter has an independent resistance layer, even if an overcurrent flows due to a short circuit, only the shorted part is destroyed, and The damage does not spread to the emitter of the. Therefore, a field emission device having a long life can be obtained.
【００２５】また、本発明に係る電界放出素子の製造方
法によれば、剥離層の成膜を正蒸着で行なうことができ
るので、膜厚を均一にすることができ、ゲート開口の孔
径も均一になる。従って、多数のエミッタを均一な高さ
に形成できるという効果がある。Further, according to the method for manufacturing a field emission device of the present invention, since the peeling layer can be formed by normal vapor deposition, the film thickness can be made uniform and the hole diameter of the gate opening can be made uniform. become. Therefore, there is an effect that many emitters can be formed at a uniform height.
【００２６】また、上述したように正蒸着法を応用して
いるので、基板面積が大きくても均一な電界放出素子を
形成できる。Since the normal vapor deposition method is applied as described above, a uniform field emission device can be formed even if the substrate area is large.
【００２７】また、抵抗層と剥離層を同時に形成できる
ので、製造工程が簡略化される。Further, since the resistance layer and the peeling layer can be formed at the same time, the manufacturing process is simplified.
【図１】一実施例の製造工程図である。FIG. 1 is a manufacturing process diagram of an example.
【図２】従来のＦＥＣの断面図である。FIG. 2 is a sectional view of a conventional FEC.
【図３】従来のＦＥＣの製造工程図である。FIG. 3 is a manufacturing process diagram of a conventional FEC.
１ 絶縁基板 ２ カソード導体 ３ 絶縁層 ４ ゲート ５ 空孔 ７ 抵抗層 ８ 剥離層 ９ エミッタ DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Cathode conductor 3 Insulating layer 4 Gate 5 Voids 7 Resistive layer 8 Release layer 9 Emitter
───────────────────────────────────────────────────── フロントページの続き (72)発明者 谷口 昌照 千葉県茂原市大芝629 双葉電子工業株式 会社 (72)発明者 西村 則雄 千葉県茂原市大芝629 双葉電子工業株式 会社 (72)発明者 落合 久隆 千葉県茂原市大芝629 双葉電子工業株式 会社 (72)発明者 山口 学 千葉県茂原市大芝629 双葉電子工業株式 会社 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masateru Taniguchi 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Co., Ltd. (72) Inventor Norio Nishimura 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Co., Ltd. (72) Inventor Hisataka Ochiai 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Co., Ltd. (72) Inventor Manabu Yamaguchi 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Co., Ltd.
Claims (3)
と、前記カソード導体上に形成されて多数の空孔を有す
る絶縁層と、前記各空孔内の前記カソード導体上に互い
に独立して設けられた抵抗層と、前記各抵抗層上に形成
されたコーン形状のエミッタと、前記絶縁層上に形成さ
れたゲートを有する電界放出素子。1. A cathode conductor formed on an insulating substrate, an insulating layer formed on the cathode conductor and having a large number of holes, and independently provided on the cathode conductor in each of the holes. A field emission device having a resistive layer formed thereon, a cone-shaped emitter formed on each resistive layer, and a gate formed on the insulating layer.
Ω・ｃｍの抵抗率を有するＰ又はＢをドープしたＳｉで
ある請求項１記載の電界放出素子。2. The resistance layer is 1 × 10 2 to 1 × 10 7.
The field emission device according to claim 1, which is P or B-doped Si having a resistivity of Ω · cm.
体を形成する工程と、前記カソード導体上に絶縁層と金
属薄膜を順次積層させる工程と、前記金属薄膜及び絶縁
層をエッチングしてゲート及び多数の空孔を形成する工
程と、前記ゲートと前記各空孔内の前記カソード導体に
正蒸着法によってＳｉ層を形成する工程と、前記ゲート
上のＳｉ薄膜を陽極酸化法で酸化してＳｉＯ2 剥離層を
形成する工程と、前記絶縁基板に真上からエミッタ材料
を正蒸着させて前記各空孔内の各Ｓｉ薄膜上にコーン形
状のエミッタを形成する工程と、前記ＳｉＯ2 剥離層上
のエミッタ材料をＳｉＯ2 剥離層とともに除去する工程
からなる電界放出素子の製造方法。3. A step of forming a cathode conductor having a predetermined pattern on an insulating substrate, a step of sequentially stacking an insulating layer and a metal thin film on the cathode conductor, and etching the metal thin film and the insulating layer to form gates and a large number of gates. forming a vacancy, a step of forming a Si layer by the positive deposition on the cathode conductor of said each of the holes and the gate, SiO 2 and the Si thin film on the gate oxidized by anodic oxidation Forming a peeling layer, forming a cone-shaped emitter on each Si thin film in each of the holes by directly vapor-depositing the emitter material on the insulating substrate, and forming a cone-shaped emitter on the SiO 2 peeling layer. A method for manufacturing a field emission device, comprising a step of removing an emitter material together with a SiO 2 peeling layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9942092A JP2636630B2 (en) | 1992-04-20 | 1992-04-20 | Field emission device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9942092A JP2636630B2 (en) | 1992-04-20 | 1992-04-20 | Field emission device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05299011A true JPH05299011A (en) | 1993-11-12 |
| JP2636630B2 JP2636630B2 (en) | 1997-07-30 |
Family
ID=14246984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9942092A Expired - Lifetime JP2636630B2 (en) | 1992-04-20 | 1992-04-20 | Field emission device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2636630B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07201272A (en) * | 1993-12-28 | 1995-08-04 | Nec Corp | Field emission cold cathode and its manufacture |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3745348B2 (en) | 2003-06-16 | 2006-02-15 | キヤノン株式会社 | Electron emitting device, electron source, and manufacturing method of image display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0536345A (en) * | 1991-07-25 | 1993-02-12 | Clarion Co Ltd | Manufacture of field emission type cold cathode |
| JPH0547296A (en) * | 1991-08-14 | 1993-02-26 | Sharp Corp | Electric field emission type electron source and manufacture thereof |
-
1992
- 1992-04-20 JP JP9942092A patent/JP2636630B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0536345A (en) * | 1991-07-25 | 1993-02-12 | Clarion Co Ltd | Manufacture of field emission type cold cathode |
| JPH0547296A (en) * | 1991-08-14 | 1993-02-26 | Sharp Corp | Electric field emission type electron source and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07201272A (en) * | 1993-12-28 | 1995-08-04 | Nec Corp | Field emission cold cathode and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2636630B2 (en) | 1997-07-30 |
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