JPH0594760A - Field emission component - Google Patents
Field emission componentInfo
- Publication number
- JPH0594760A JPH0594760A JP27623391A JP27623391A JPH0594760A JP H0594760 A JPH0594760 A JP H0594760A JP 27623391 A JP27623391 A JP 27623391A JP 27623391 A JP27623391 A JP 27623391A JP H0594760 A JPH0594760 A JP H0594760A
- Authority
- JP
- Japan
- Prior art keywords
- film
- emitter
- layer
- cathode electrode
- resistance layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2201/00—Electrodes common to discharge tubes
- H01J2201/30—Cold cathodes
- H01J2201/319—Circuit elements associated with the emitters by direct integration
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は電界放出素子（Field Em
issionCathodes,以下ＦＥＣとも呼ぶ。）に関するもの
である。本発明のＦＥＣは、蛍光表示装置をはじめとす
る各種表示装置、マイクロ波真空管、光源、増幅素子、
高速スイッチング素子、センサー等における電子源とし
て有用である。The present invention relates to a field emission device (Field Emitter).
ission Cathodes, hereinafter also referred to as FEC. ). The FEC of the present invention includes various display devices including a fluorescent display device, a microwave vacuum tube, a light source, an amplification element,
It is useful as an electron source in high-speed switching devices, sensors, etc.
【０００２】[0002]
【従来の技術】電子放出素子の一構造例であるいわゆる
縦型の構造を図４に示す。図中１００はガラス等から成
る絶縁性の基板である。基板１００の上面にはカソード
電極１０１が設けられている。カソード電極１０１の上
面にはシリコン薄膜等からなる抵抗層１０２が設けられ
ている。抵抗層１０２の上面にはＳｉＯ2 等の絶縁層１
０３が設けられている。該絶縁層１０３にはキャビティ
１０４が形成され、絶縁層１０３の上面にはゲート１０
５が設けられている。そして、前記キャビティ１０４内
の抵抗層１０２の上には円錐形のエミッタ１０６が設け
られている。即ちエミッタ１０６は、基板１００の上面
において抵抗層１０２を介してカソード電極１０１に接
続されている。2. Description of the Related Art A so-called vertical structure, which is an example of the structure of an electron-emitting device, is shown in FIG. In the figure, 100 is an insulating substrate made of glass or the like. A cathode electrode 101 is provided on the upper surface of the substrate 100. A resistance layer 102 made of a silicon thin film or the like is provided on the upper surface of the cathode electrode 101. An insulating layer 1 such as SiO 2 is formed on the upper surface of the resistance layer 102.
03 is provided. A cavity 104 is formed in the insulating layer 103, and the gate 10 is formed on the upper surface of the insulating layer 103.
5 are provided. A conical emitter 106 is provided on the resistance layer 102 in the cavity 104. That is, the emitter 106 is connected to the cathode electrode 101 via the resistance layer 102 on the upper surface of the substrate 100.
【０００３】前記電界放出素子において、作成後の電子
放出開始時に、各エミッタ構造等の不均一により特定の
エミッタに強電界がかかることにより、瞬間的に大量の
部分的なガス放出等による放電が生じ、エミッタが破壊
される事故が発生することがあった。しかしながら、前
記電界放出素子によれば、エミッタ１０６とカソード電
極１０１の間に電流制限用の抵抗層１０２が設けられて
いるため、エミッタ電流の増加に伴いエミッタ・ゲート
間にかかる電圧を低下させ、エミッタの暴走を抑える方
向で働く。また、短絡状態にはならないため、隣接する
他のエミッタ１０６からの電子放出を損ねるほどの電圧
降下が起こることはない。In the field emission device, when an electron emission is started after the production, a strong electric field is applied to a specific emitter due to non-uniformity of each emitter structure and the like, so that a large amount of partial discharge of gas is instantaneously discharged. Occasionally, an accident occurred in which the emitter was destroyed. However, according to the field emission device, since the resistance layer 102 for current limitation is provided between the emitter 106 and the cathode electrode 101, the voltage applied between the emitter and the gate is reduced as the emitter current increases. It works in the direction of suppressing runaway of the emitter. Further, since the short-circuited state does not occur, a voltage drop that would impair the emission of electrons from another adjacent emitter 106 does not occur.
【０００４】さて、前記抵抗層１０２を構成する材料と
しては、特開平１−１５４４２６号に記載されているよ
うに、Ｉｎ2 Ｏ3 ，ＳｎＯ2 ，Ｆｅ2 Ｏ3 ，ＺｎＯ又は
ドープ型Ｓｉが提案されているが、実用化されているの
はドープ型Ｓｉだけである。As a material for forming the resistance layer 102, In 2 O 3 , SnO 2 , Fe 2 O 3 , ZnO or doped Si is proposed as described in JP-A-1-154426. However, only doped Si is practically used.
【０００５】[0005]
（１）ドープ型ＳｉはＣＶＤ法によって形成されるた
め、成膜速度が非常に遅く、例えば５〜１０×１０-9ｍ
／ｍｉｎ程度である。このため１０6 Ωｃｍ±２０％程
度の抵抗を有する膜厚（０．１〜１μｍ）を得るのに非
常に長い時間がかかり効率的ではなかった。(1) Since doped Si is formed by the CVD method, the film formation rate is very slow, for example, 5 to 10 × 10 −9 m
/ Min. Therefore, it takes a very long time to obtain a film thickness (0.1 to 1 μm) having a resistance of about 10 6 Ωcm ± 20%, which is not efficient.
【０００６】（２）ドープ型Ｓｉ以外の前記酸化物は、
一般にスパッタ法で成膜できるが、この方法もＣＶＤ法
同様に成膜速度が遅いという問題点があった。(2) The oxide other than doped Si is
Generally, a film can be formed by a sputtering method, but this method also has a problem that the film forming rate is slow like the CVD method.
【０００７】（３）ＣＶＤ法等でドープ型Ｓｉや酸化物
の膜を形成する場合には、ドープガスとして有毒なホス
フィン（ＰＨ3 ）を使用しなければならなかった。ま
た、ホスフィンを使用する場合、抵抗を下げるために高
温アニール（７００〜９００℃）が必要になる。ところ
が、このような高温ではガラス基板が溶融してしまい、
結局目的の抵抗値１０5 〜１０7 Ωｃｍが得られないと
いう問題点があった。(3) When forming a doped Si or oxide film by the CVD method or the like, toxic phosphine (PH 3 ) had to be used as a doping gas. Further, when phosphine is used, high temperature annealing (700 to 900 ° C.) is required to reduce the resistance. However, at such a high temperature, the glass substrate melts,
After all, there was a problem that the target resistance value of 10 5 to 10 7 Ωcm could not be obtained.
【０００８】（４）ＣＶＤ法・蒸着法・スパッタ法等の
方法では、形成する酸化物の膜厚を基板の全面で均一に
することが困難であった。従って、ＦＥＣを表示装置の
電子源とした場合には、表示部に対応するＦＥＣの全面
において抵抗層の抵抗値を均一にすることが困難であっ
た。(4) It has been difficult to make the film thickness of the oxide to be formed uniform on the entire surface of the substrate by the methods such as the CVD method, the vapor deposition method and the sputtering method. Therefore, when the FEC is used as the electron source of the display device, it is difficult to make the resistance value of the resistance layer uniform over the entire surface of the FEC corresponding to the display unit.
【０００９】本発明は、抵抗層として均一な厚さの酸化
膜を有する電界放出素子を提供することを目的としてい
る。An object of the present invention is to provide a field emission device having an oxide film having a uniform thickness as a resistance layer.
【００１０】[0010]
【課題を解決するための手段】本発明の電界放出素子
は、絶縁性の基板と、前記基板上に設けられたカソード
電極と、前記カソード電極上に設けられた抵抗層と、前
記抵抗層を介して前記カソード電極に接続されたエミッ
タとを具備する電界放出素子において、前記抵抗層が酸
化タンタルの薄膜を有することを特徴としている。A field emission device according to the present invention comprises an insulating substrate, a cathode electrode provided on the substrate, a resistance layer provided on the cathode electrode, and the resistance layer. In the field emission device having an emitter connected to the cathode electrode through the resistance layer, the resistance layer has a thin film of tantalum oxide.
【００１１】[0011]
【作用】基板のカソード電極上にタンタル膜を形成し、
このタンタル膜を酸化させれば酸化タンタルの薄膜を得
られるが、酸化の一手法として用いうる陽極酸化では電
圧や電流、処理時間等によって酸化膜の膜厚を精密に制
御することができる。[Function] A tantalum film is formed on the cathode electrode of the substrate,
Although a thin film of tantalum oxide can be obtained by oxidizing this tantalum film, the thickness of the oxide film can be precisely controlled by voltage, current, processing time or the like in anodic oxidation which can be used as a method of oxidation.
【００１２】[0012]
【実施例】図１〜図３により一実施例の電界放出素子１
を説明する。図１に示すように、ガラス基板２上にはア
ルミニウムからなるカソード電極３が形成されている。
その上にはタンタル膜４が被着されており、その上層は
抵抗層としての酸化タンタル層５になっている。図中６
は絶縁層であり、その上にはゲート電極７が設けられて
いる。ゲート電極７及び絶縁層５にはホール８が形成さ
れ、ホール８内の酸化タンタル層５上にはコーン形状の
エミッタ９が形成されている。Embodiment A field emission device 1 according to one embodiment will be described with reference to FIGS.
Will be explained. As shown in FIG. 1, a cathode electrode 3 made of aluminum is formed on a glass substrate 2.
A tantalum film 4 is deposited thereon, and an upper layer thereof is a tantalum oxide layer 5 as a resistance layer. 6 in the figure
Is an insulating layer, and the gate electrode 7 is provided thereon. A hole 8 is formed in the gate electrode 7 and the insulating layer 5, and a cone-shaped emitter 9 is formed on the tantalum oxide layer 5 in the hole 8.
【００１３】次に、前記電界放出素子１の製造工程を説
明する。 （１）ガラス基板２上に、ストライプ状のパターンとな
るように２００ｎｍの厚さでアルミニウムを被着し、カ
ソード電極３とする。 （２）前記カソード電極３上に、スパッタ法によって５
００ｎｍの厚さでＴａ膜４をベタに被着する。このＴａ
膜４をフォトエッチングによって所定のパターンにエッ
チングする。この場合、ＣＦ4 とＯ2 の分圧を適当に調
整してドライエッチングで形成してもよい。Next, the manufacturing process of the field emission device 1 will be described. (1) Aluminum is deposited on the glass substrate 2 in a thickness of 200 nm so as to form a striped pattern to form the cathode electrode 3. (2) 5 is formed on the cathode electrode 3 by a sputtering method.
A Ta film 4 having a thickness of 00 nm is solidly deposited. This Ta
The film 4 is etched into a predetermined pattern by photoetching. In this case, it may be formed by dry etching with the partial pressure of CF 4 and O 2 adjusted appropriately.
【００１４】（３）次に、前記Ｔａ膜４の表面に陽極酸
化によりピンホールの少い安定で緻密な酸化タンタル層
５を形成する。まず図２に示すように、ガラス基板２を
リン酸水溶液等の化成液１０中に浸漬する。そしてガラ
ス基板２のカソード電極３を陽極に接続するとともに対
向電極としての白金電極１１を陰極に接続する。(3) Next, a stable and dense tantalum oxide layer 5 with few pinholes is formed on the surface of the Ta film 4 by anodic oxidation. First, as shown in FIG. 2, the glass substrate 2 is immersed in a chemical conversion solution 10 such as a phosphoric acid aqueous solution. Then, the cathode electrode 3 of the glass substrate 2 is connected to the anode, and the platinum electrode 11 as the counter electrode is connected to the cathode.
【００１５】（４）図３に示すように白金電極１１に電
圧を印加して陽極酸化を行う。ここで、陽極付近におい
ては次に示すような反応が生じ、Ｔａ膜４の表面には酸
化タンタル層５が形成されていく。(4) As shown in FIG. 3, a voltage is applied to the platinum electrode 11 to perform anodic oxidation. Here, the following reaction occurs near the anode, and the tantalum oxide layer 5 is formed on the surface of the Ta film 4.
【００１６】[0016]
【化１】 [Chemical 1]
【００１７】酸化膜形成上重要な点は、膜厚及び膜質そ
してこれらの均一性である。膜厚は印加電圧で決まり、
図３中に示す初期電流値により成膜速度を制御して膜質
を制御する。初期電流値が小さい程緻密な膜を形成する
ことができるが、成膜速度は遅くなる。The important points in forming the oxide film are the film thickness, the film quality and their uniformity. The film thickness is determined by the applied voltage,
The film quality is controlled by controlling the film formation rate according to the initial current value shown in FIG. The smaller the initial current value is, the finer the film can be formed, but the film formation rate becomes slower.
【００１８】均一性については、反応過程で酸化膜の薄
い部分に電界が集中する自己整合作用が働くので、他の
ＣＶＤ法やスパッタ法に比較してピンホールの少い良質
な成膜が、電圧・電流・時間をパラメータとして再現性
良く行なえる。また、陽極酸化された部分とされていな
い部分の色差により、容易に断線チェックを行なうこと
ができる。Regarding the uniformity, since a self-aligning action in which an electric field is concentrated on a thin portion of an oxide film in the reaction process works, a good quality film with few pinholes can be formed as compared with other CVD methods and sputtering methods. It can be performed with good reproducibility using voltage, current and time as parameters. Further, disconnection can be easily checked by the color difference between the anodized portion and the non-anodized portion.
【００１９】（５）次に、ＳｉＯ2 やＡｌ2 Ｏ3 等から
なる絶縁層６を前記酸化タンタル層５上に１．０μｍの
厚さで形成する。 （６）前記絶縁層６の表面に、Ｔｉ，Ｃｒ，Ｎｂ，Ｍｏ
等の金属により０．４μｍの厚さでゲート電極７を形成
する。このゲート電極７は、ストライプ状の前記カソー
ド電極３と直交する方向に沿ってストライプ状に形成す
る。(5) Next, an insulating layer 6 made of SiO 2 , Al 2 O 3 or the like is formed on the tantalum oxide layer 5 to a thickness of 1.0 μm. (6) On the surface of the insulating layer 6, Ti, Cr, Nb, Mo
The gate electrode 7 is formed with a thickness of 0.4 μm using a metal such as. This gate electrode 7 is formed in a stripe shape along a direction orthogonal to the stripe-shaped cathode electrode 3.
【００２０】（７）フォトリソグラフィ法及びエッチン
グにより、ゲート電極７及び絶縁層６にホール８を多数
形成する。ホール８の径は１．４μｍ位であり、本工程
でホールの底に前記酸化タンタル（Ｔａ2 Ｏ5 ）層５が
あらわれる。斜め蒸着法等により、ホール８内の酸化タ
ンタル層５上にＭｏ，Ｎｂ等の金属で円錐状のエミッタ
９を形成する。エミッタ９の先端は、ほぼゲート電極７
と同じ高さにくるようにする。(7) A large number of holes 8 are formed in the gate electrode 7 and the insulating layer 6 by photolithography and etching. The diameter of the hole 8 is about 1.4 μm, and the tantalum oxide (Ta 2 O 5 ) layer 5 appears at the bottom of the hole in this step. A conical emitter 9 made of a metal such as Mo or Nb is formed on the tantalum oxide layer 5 in the hole 8 by an oblique deposition method or the like. The tip of the emitter 9 is almost the gate electrode 7.
So that it is at the same height as.
【００２１】[0021]
【発明の効果】本発明によれば、ＦＥＣのエミッタとカ
ソード電極間に設ける抵抗層を酸化タンタルで構成した
ので、次のような効果が得られる。 （１）酸化タンタル層は陽極酸化法により厚さを精密に
制御して製造できるので、大面積のＦＥＣにおいても前
記抵抗層の厚さを一定にでき、均一な性能のＦＥＣを形
成できる。 （２）陽極酸化法で抵抗層を形成するので、工程が簡単
であり、量産性良くＦＥＣを製造できる。According to the present invention, since the resistance layer provided between the emitter and cathode electrodes of the FEC is made of tantalum oxide, the following effects can be obtained. (1) Since the tantalum oxide layer can be manufactured by precisely controlling the thickness by the anodic oxidation method, the thickness of the resistance layer can be made constant even in a large area FEC, and an FEC with uniform performance can be formed. (2) Since the resistance layer is formed by the anodic oxidation method, the process is simple and the FEC can be manufactured with good mass productivity.
【図１】本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
【図２】一実施例で用いる陽極酸化法の装置を示す図で
ある。FIG. 2 is a diagram showing an apparatus for an anodizing method used in one example.
【図３】陽極酸化法における印加電圧・電流を示すグラ
フである。FIG. 3 is a graph showing applied voltage / current in the anodizing method.
【図４】抵抗層を有する従来のスピント形のＦＥＣを示
す斜視図である。FIG. 4 is a perspective view showing a conventional Spindt-type FEC having a resistance layer.
１ 電界放出素子（ＦＥＣ） ２ ガラス基板 ３ カソード電極 ５ 抵抗層である酸化タンタル層 ９ エミッタ DESCRIPTION OF SYMBOLS 1 Field emission device (FEC) 2 Glass substrate 3 Cathode electrode 5 Tantalum oxide layer which is a resistance layer 9 Emitter
Claims (1)
たカソード電極と、前記カソード電極上に設けられた抵
抗層と、前記抵抗層を介して前記カソード電極に接続さ
れたエミッタとを具備する電界放出素子において、前記
抵抗層が酸化タンタルの薄膜を有することを特徴とする
電界放出素子。1. An insulating substrate, a cathode electrode provided on the substrate, a resistance layer provided on the cathode electrode, and an emitter connected to the cathode electrode via the resistance layer. A field emission device comprising: the resistance layer having a thin film of tantalum oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27623391A JP2720662B2 (en) | 1991-09-30 | 1991-09-30 | Field emission device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27623391A JP2720662B2 (en) | 1991-09-30 | 1991-09-30 | Field emission device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0594760A true JPH0594760A (en) | 1993-04-16 |
| JP2720662B2 JP2720662B2 (en) | 1998-03-04 |
Family
ID=17566554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27623391A Expired - Fee Related JP2720662B2 (en) | 1991-09-30 | 1991-09-30 | Field emission device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2720662B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5557160A (en) * | 1993-12-28 | 1996-09-17 | Nec Corporation | Field emission cathode including cylindrically shaped resistive connector and method of manufacturing |
| EP0818799A2 (en) * | 1996-07-12 | 1998-01-14 | Tektronix, Inc. | Cathode structure for a plasma addressed liquid crystal display panel |
| US6060823A (en) * | 1997-03-27 | 2000-05-09 | Nec Corporation | Field emission cold cathode element |
| EP1019935A1 (en) * | 1997-09-30 | 2000-07-19 | Candescent Technologies Corporation | Row electrode anodization |
| WO2002015214A3 (en) * | 2000-08-11 | 2002-08-08 | Isis Innovation | Field emitter devices incorporating an improved ballast resistor |
| JP2007066892A (en) * | 2005-08-26 | 2007-03-15 | Samsung Sdi Co Ltd | Electron emission device, electron emission display device and method for manufacturing same electron emission display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5114281A (en) * | 1974-07-26 | 1976-02-04 | Hitachi Ltd | Taiyodenchino seizohoho |
| JPH01154426A (en) * | 1987-11-06 | 1989-06-16 | Commiss Energ Atom | Electron source |
| JPH0371529A (en) * | 1989-08-09 | 1991-03-27 | Seiko Epson Corp | Manufacture of field generating electrode |
-
1991
- 1991-09-30 JP JP27623391A patent/JP2720662B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5114281A (en) * | 1974-07-26 | 1976-02-04 | Hitachi Ltd | Taiyodenchino seizohoho |
| JPH01154426A (en) * | 1987-11-06 | 1989-06-16 | Commiss Energ Atom | Electron source |
| JPH0371529A (en) * | 1989-08-09 | 1991-03-27 | Seiko Epson Corp | Manufacture of field generating electrode |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5557160A (en) * | 1993-12-28 | 1996-09-17 | Nec Corporation | Field emission cathode including cylindrically shaped resistive connector and method of manufacturing |
| EP0818799A2 (en) * | 1996-07-12 | 1998-01-14 | Tektronix, Inc. | Cathode structure for a plasma addressed liquid crystal display panel |
| EP0818799A3 (en) * | 1996-07-12 | 1998-09-23 | Tektronix, Inc. | Cathode structure for a plasma addressed liquid crystal display panel |
| US5897415A (en) * | 1996-07-12 | 1999-04-27 | Tektronix, Inc. | Cathode structure for a plasma addressed liquid crystal display panel |
| US6060823A (en) * | 1997-03-27 | 2000-05-09 | Nec Corporation | Field emission cold cathode element |
| EP1019935A1 (en) * | 1997-09-30 | 2000-07-19 | Candescent Technologies Corporation | Row electrode anodization |
| EP1019935A4 (en) * | 1997-09-30 | 2004-04-07 | Candescent Tech Corp | Row electrode anodization |
| WO2002015214A3 (en) * | 2000-08-11 | 2002-08-08 | Isis Innovation | Field emitter devices incorporating an improved ballast resistor |
| JP2007066892A (en) * | 2005-08-26 | 2007-03-15 | Samsung Sdi Co Ltd | Electron emission device, electron emission display device and method for manufacturing same electron emission display device |
| US7626323B2 (en) | 2005-08-26 | 2009-12-01 | Samsung Sdi Co., Ltd. | Electron emission element, electron emission display, and method of manufacturing electron emission unit for the electron emission display |
| JP4602295B2 (en) * | 2005-08-26 | 2010-12-22 | 三星エスディアイ株式会社 | Electron emission display device and method of manufacturing electron emission display device |
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|---|---|
| JP2720662B2 (en) | 1998-03-04 |
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