JPH0529768A - Multilayer wiring structural member - Google Patents
Multilayer wiring structural memberInfo
- Publication number
- JPH0529768A JPH0529768A JP17927191A JP17927191A JPH0529768A JP H0529768 A JPH0529768 A JP H0529768A JP 17927191 A JP17927191 A JP 17927191A JP 17927191 A JP17927191 A JP 17927191A JP H0529768 A JPH0529768 A JP H0529768A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- multilayer wiring
- viahole
- solder paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は多層配線ＦＰＣ、多層配
線基板などに形成されたバイアホールの連結構造体に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection structure for via holes formed in a multi-layer wiring FPC, a multi-layer wiring board, or the like.
【０００２】[0002]
【従来の技術】最近ＩＣの高速化に対応して、伝送スピ
ードの向上、ノイズの低減などの観点からＴＡＢテープ
やＦＰＣなどの配線基板において多層配線構造体が用い
られるようになった。このような多層配線構造体におい
ては、例えばポリイミドフィルムなどの絶縁層の上面に
信号層、下面に電源層を有しているが、下面の電源層か
ら配線をとるためなどの目的でバイアホールが設けられ
る。2. Description of the Related Art Recently, in response to the speeding up of ICs, multilayer wiring structures have come to be used in wiring boards such as TAB tapes and FPCs from the viewpoint of improving transmission speed and reducing noise. In such a multilayer wiring structure, a signal layer is provided on the upper surface of an insulating layer such as a polyimide film, and a power supply layer is provided on the lower surface, but via holes are formed for the purpose of taking wiring from the power supply layer on the lower surface. It is provided.
【０００３】バイアホールを介してこのような層間を電
気的に連結する手段として、従来めっき法や蒸着法が知
られている。As a means for electrically connecting such layers electrically via a via hole, a plating method and a vapor deposition method have been conventionally known.
【０００４】めっき法は電気めっき法や無電解めっき法
により、図２に示すようにバイアホール１内壁の垂直方
向に厚さ約５〜１０μｍのめっき２を施して層間を連結
するもので、バイアホール部以外にめっきレジストを印
刷してバイアホール部のみにめっきを施す方法、あるい
は全面めっき後にホトエッチング法により余分な部分の
めっき膜を除去する方法がある。この場合銅の電気めっ
きでは５〜１０分、無電解めっきでは１〜２時間とめっ
きに時間がかかること、湿式で行なわれるためイオン性
物質がバイアホールや層間に残留して、マイグレーショ
ンや配線腐食原因となること、めっき層が薄いため熱ス
トレスに弱いこと、更には連結部の電気抵抗が高く、伝
送特性が低下するなどの問題点がある。The plating method uses electroplating or electroless plating to form a plating 2 having a thickness of about 5 to 10 μm in the direction perpendicular to the inner wall of the via hole 1 as shown in FIG. There is a method of printing a plating resist on a portion other than the hole portion to plate only the via hole portion, or a method of removing an excessive portion of the plating film by photoetching after the entire surface is plated. In this case, electroplating of copper takes 5 to 10 minutes, electroless plating takes 1 to 2 hours, and since it is carried out by a wet method, ionic substances remain in via holes and layers, causing migration and wiring corrosion. There are problems that it is a cause, that the plating layer is thin, and that it is vulnerable to heat stress, and that the electrical resistance of the connecting portion is high and the transmission characteristics deteriorate.
【０００５】また蒸着法はイオンプレーティング法、ス
パッタリング法などがあり、図３に示すように蒸着マス
ク１１を用いてバイアホール部への蒸着３を行なうか、
またはめっき法と同様に全面蒸着後に余分な部分をホト
エッチング法により除去する方法である。この方法では
５〜１０μｍの厚さに蒸着させるのに４〜５時間と時間
がかかること、蒸着マスクが高価である上に高価な蒸着
設備が必要であること、さらにめっき法による連結と同
様に連結部が熱ストレスに弱く、また電気抵抗が高いと
いう問題点がある。Further, the vapor deposition method includes an ion plating method, a sputtering method and the like. As shown in FIG. 3, the vapor deposition mask 11 is used to perform vapor deposition 3 on the via hole portion, or
Alternatively, as in the plating method, after the entire surface is vapor-deposited, the excess portion is removed by the photoetching method. In this method, it takes 4 to 5 hours to deposit a film having a thickness of 5 to 10 μm, an evaporation mask is expensive, and expensive evaporation equipment is required. There are problems that the connecting part is weak against heat stress and has high electric resistance.
【０００６】[0006]
【発明が解決しようとする課題】バイアホールの連結に
関する上記従来技術の課題に鑑み、信頼性が高く、容易
に連結できる方法が求められていた。本発明は、このよ
うな要望に応えるものである。In view of the above-mentioned problems of the prior art relating to the connection of via holes, there has been a demand for a method which is highly reliable and can be easily connected. The present invention meets these needs.
【０００７】本発明の目的はバイアホールの連結を半田
ペーストを印刷することにより実現するものであり、加
工作業が極めて簡単で、バイアホールの連結信頼性の高
い多層配線構造体を提供するものである。An object of the present invention is to realize connection of via holes by printing a solder paste, and to provide a multilayer wiring structure which is extremely easy to process and has high reliability of via hole connection. is there.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に本発明によれば、絶縁層の両面に配線層を有する多層
配線構造体に形成されたバイアホールに、半田ペースト
を印刷することにより、両配線層を連結して成る多層配
線構造体が提供される。以下、本発明をさらに詳細に説
明する。To achieve the above object, according to the present invention, a solder paste is printed on a via hole formed in a multilayer wiring structure having wiring layers on both sides of an insulating layer. Provided is a multilayer wiring structure formed by connecting both wiring layers. Hereinafter, the present invention will be described in more detail.
【０００９】図１は、本発明の多層配線構造体の連結構
造の一例を示す断面図である。以下多層配線構造体とし
てＦＰＣを代表例として説明するがこれに限るものでは
ない。FIG. 1 is a sectional view showing an example of a connection structure of a multilayer wiring structure of the present invention. An FPC will be described below as a typical example of the multilayer wiring structure, but the present invention is not limited to this.
【００１０】本発明において絶縁層５は、ポリイミドフ
ィルムを挙げることができるがこれに限るものではな
い。この絶縁層の厚さは限定しないが、例えば２５μm
程度である。In the present invention, the insulating layer 5 may be a polyimide film, but is not limited thereto. The thickness of this insulating layer is not limited, but is 25 μm, for example.
It is a degree.
【００１１】前記絶縁層５の両面に第１配線層４および
第２（裏面）配線層７を有する。第１配線層４として
は、例えば厚さ２０μm 程度の銅などを挙げることがで
きる。A first wiring layer 4 and a second (back surface) wiring layer 7 are provided on both surfaces of the insulating layer 5. As the first wiring layer 4, for example, copper having a thickness of about 20 μm can be used.
【００１２】通常、前記絶縁層５に第１配線層４を設け
た状態で、例えば金型プレス開口法によりバイアホール
１を開口する。その後、下面に例えば４２アロイ（４２
％Ｎｉ−Ｆｅ合金）の第２配線層７を貼りつけて構造体
としている。前記第２配線層７は、例えばエポキシ系接
着剤層６を介して貼りつけられる。前記バイアホール１
の大きさは、配線作業などを考慮して適宜の大きさとす
ればよく、通常０．５ｍｍФ程度である。Normally, with the first wiring layer 4 provided on the insulating layer 5, the via hole 1 is opened by, for example, a die press opening method. Then, for example, 42 alloy (42
% Ni—Fe alloy) is attached to form a structure. The second wiring layer 7 is attached, for example, via the epoxy adhesive layer 6. The via hole 1
The size may be set to an appropriate size in consideration of wiring work and the like, and is usually about 0.5 mmΦ.
【００１３】本発明では、前記バイアホール１に、半田
ペースト印刷層８を形成することにより、前記両配線層
４，７が連結されている。半田ペーストの印刷方法とし
ては、例えばメタルマスクを用い、バイアホールに合せ
てスクリーン印刷する方法を挙げることができる。この
印刷層８の厚さは限定しないが、硬化後で２０μm 前後
であれば電気抵抗値および機械的強度上問題ない。前記
半田ペーストは、通常エポキシレジンと硬化剤の混合レ
ジンに配合して用い、印刷後加熱硬化処理を施す。半田
粉末は、例えば、６０％Ｓｎ−Ｐｂで２〜３μm Ф程度
のものでよい。In the present invention, the wiring layers 4 and 7 are connected to each other by forming the solder paste printed layer 8 in the via hole 1. As a printing method of the solder paste, for example, a method of using a metal mask and screen printing in accordance with the via hole can be mentioned. The thickness of the printed layer 8 is not limited, but if it is about 20 μm after curing, there is no problem in terms of electric resistance and mechanical strength. The solder paste is usually used by mixing it with a mixed resin of an epoxy resin and a curing agent, and is subjected to heat curing treatment after printing. The solder powder may be, for example, 60% Sn-Pb and about 2-3 μm Φ.
【００１４】[0014]
【実施例】以下に本発明を実施例に基づき具体的に説明
する。EXAMPLES The present invention will be specifically described below based on examples.
【００１５】（実施例１）図１に示す構造の多層配線Ｆ
ＰＣを作成した。用いた多層配線ＦＰＣは厚さ２５μｍ
のポリイミドフィルム絶縁層５の上面に、厚さ２０μｍ
の銅の第１配線層４を設け、金型プレス開口法により
０．５ｍｍΦのバイアホール開口後、下面に厚さ２０μ
ｍのエポキシ系接着剤層６を介して厚さ２５μｍの４２
アロイ７（第２配線層）を貼りつけた。次いで半田ペー
ストをメタルマスクを用い、バイアホールに合わせて、
２５μｍの厚さに印刷した。半田ペーストはエポキシレ
ジンと硬化剤の混合レジンに対して、２〜３μｍΦの６
０％Ｓｎ−Ｐｂ半田粉末を配合したもので、印刷後２５
０℃、５時間加熱硬化処理を施した。硬化後の印刷層８
の厚さは２０μｍであった。バイアホール連結部の特性
試験結果を表１に示す。(Embodiment 1) Multilayer wiring F having the structure shown in FIG.
Created a PC. The multilayer wiring FPC used has a thickness of 25 μm.
20 μm thick on the upper surface of the polyimide film insulating layer 5 of
Copper first wiring layer 4 is provided, a via hole of 0.5 mmΦ is opened by a die press opening method, and then a thickness of 20 μm is formed on the lower surface.
m having a thickness of 25 μm through the epoxy adhesive layer 6
Alloy 7 (second wiring layer) was attached. Next, use a metal mask to match the solder paste to the via holes,
Printed to a thickness of 25 μm. Solder paste is 6 μm of 2-3 μmΦ for mixed resin of epoxy resin and curing agent.
25% after printing with a mixture of 0% Sn-Pb solder powder
It was heat-cured at 0 ° C. for 5 hours. Printed layer 8 after curing
Had a thickness of 20 μm. Table 1 shows the results of the characteristic test of the via hole connecting portion.
【００１６】（実施例２）実施例１において、バイアホ
ールの開口径を０．２ｍｍΦとした他は実施例１と同様
に行なった。バイアホール連結部の特性試験結果を表１
に示す。(Embodiment 2) The same operation as in Embodiment 1 is carried out except that the opening diameter of the via hole is changed to 0.2 mmΦ. Table 1 shows the characteristics test results of the via hole connection part.
Shown in.
【００１７】（比較例１）実施例１と同じバイアホール
を有する多層配線構造体を、無電解法銅めっきにより連
結した（図２参照）。(Comparative Example 1) Multilayer wiring structures having the same via holes as in Example 1 were connected by electroless copper plating (see FIG. 2).
【００１８】（試験法）温度サイクル（熱ストレス）
試験 バイアホールを連結した多層配線ＦＰＣをＥＩＡＪ規格
に準拠し、温度サイクル試験機を用い、−５０℃に５時
間保った後、昇温速度１０分間で１５０℃に昇温し、５
時間保つ。次いで降温速度１０分間で−５０℃とする。
これを５００サイクル行い、試験数２０に対し連結が破
断したサンプル個数を調べる。(Test method) Temperature cycle (heat stress)
According to the EIAJ standard, a multi-layer wiring FPC having test via holes connected was kept at -50 ° C for 5 hours using a temperature cycle tester, and then heated to 150 ° C at a heating rate of 10 minutes.
Keep time Then, the temperature is lowered to −50 ° C. for 10 minutes.
This is performed for 500 cycles, and the number of samples in which the connection is broken is examined for 20 tests.
【００１９】バイアホール連結部の直流抵抗値の変化 連結後の抵抗値と、６５℃、９５％相対湿度の雰囲気に
１００時間保持後の抵抗値（Ω）を示したもので、試験
数２０の平均値である。Change in DC resistance value of via-hole connection part The resistance value after connection and the resistance value (Ω) after 100 hours of holding in an atmosphere of 65 ° C. and 95% relative humidity are shown. It is an average value.
【００２０】 [0020]
【００２１】[0021]
【発明の効果】本発明は以上説明したように構成されて
いるので、本発明によって提供される多層配線構造体
は、バイアホールの連結に作業容易な半田ペーストによ
る印刷法をとり入れたため、きわめて能率良く製造する
ことができる。まためっき法のようにイオン性不純物の
侵入の恐れが全くなく、バイアホールの連結部の熱スト
レスによる信頼性も良好で、連結部の電気抵抗も小さ
い。Since the present invention is constructed as described above, the multilayer wiring structure provided by the present invention employs a solder paste printing method for connecting via holes, which is very efficient. It can be manufactured well. Further, unlike the plating method, there is no possibility of invasion of ionic impurities, the reliability due to the thermal stress at the connecting portion of the via hole is good, and the electrical resistance of the connecting portion is small.
【図１】本発明の多層配線構造体の連結構造の一例を示
す断面図である。FIG. 1 is a cross-sectional view showing an example of a connection structure of a multilayer wiring structure of the present invention.
【図２】従来法（めっき法）による連結構造を示す断面
図である。FIG. 2 is a cross-sectional view showing a connection structure by a conventional method (plating method).
【図３】従来法（蒸着法）による連結構造を示す断面図
である。FIG. 3 is a cross-sectional view showing a connection structure by a conventional method (vapor deposition method).
１ バイアホール ２ バイアホールの連結層（めっき） ３ バイアホールの連結層（蒸着） ４ 第１配線層 ５ 絶縁層 ６ 接着剤層 ７ 第２（裏面）配線層 ８ 半田ペースト印刷層 1 Via Hole 2 Via Hole Connection Layer (Plating) 3 Via Hole Connection Layer (Evaporation) 4 First Wiring Layer 5 Insulating Layer 6 Adhesive Layer 7 Second (Backside) Wiring Layer 8 Solder Paste Printed Layer
Claims (1)
構造体に形成されたバイアホールに、半田ペーストを印
刷することにより、両配線層を連結して成る多層配線構
造体。Claim: What is claimed is: 1. A multilayer wiring comprising a wiring layer having wiring layers on both sides of an insulating layer, the wiring layer being connected to each other by printing solder paste in via holes formed in the multilayer wiring structure. Structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17927191A JPH0529768A (en) | 1991-07-19 | 1991-07-19 | Multilayer wiring structural member |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17927191A JPH0529768A (en) | 1991-07-19 | 1991-07-19 | Multilayer wiring structural member |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0529768A true JPH0529768A (en) | 1993-02-05 |
Family
ID=16062925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17927191A Withdrawn JPH0529768A (en) | 1991-07-19 | 1991-07-19 | Multilayer wiring structural member |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0529768A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5248238A (en) * | 1991-04-15 | 1993-09-28 | Nippondenso Co., Ltd. | Vortex pump |
| FR2834180A1 (en) * | 2001-12-20 | 2003-06-27 | Org Europeene De Rech | Production of a multi layer module for high-density printed circuits comprises anisotropically etching micro holes through a metal-coated polyimide film |
-
1991
- 1991-07-19 JP JP17927191A patent/JPH0529768A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5248238A (en) * | 1991-04-15 | 1993-09-28 | Nippondenso Co., Ltd. | Vortex pump |
| FR2834180A1 (en) * | 2001-12-20 | 2003-06-27 | Org Europeene De Rech | Production of a multi layer module for high-density printed circuits comprises anisotropically etching micro holes through a metal-coated polyimide film |
| WO2003055288A1 (en) * | 2001-12-20 | 2003-07-03 | Organisation Europeenne Pour La Recherche Nucleaire | Method for making a multilayer module with high-density printed circuits |
| US7135119B2 (en) | 2001-12-20 | 2006-11-14 | Organisation Europeenne Pour La Recherche Nucleaire | Method for making a multilayer module with high-density printed circuits |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981008 |