JPH05252000A - Signal processing unit - Google Patents
Signal processing unitInfo
- Publication number
- JPH05252000A JPH05252000A JP4823892A JP4823892A JPH05252000A JP H05252000 A JPH05252000 A JP H05252000A JP 4823892 A JP4823892 A JP 4823892A JP 4823892 A JP4823892 A JP 4823892A JP H05252000 A JPH05252000 A JP H05252000A
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- Japan
- Prior art keywords
- adder
- output
- filter
- coefficient
- circuit
- Prior art date
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- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、制御のための信号処理
装置に係り、特に、適応等化器に適する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for control, and particularly to an adaptive equalizer.
【０００２】[0002]
【従来の技術】従来、適応等化器は、特開昭59−134927
号公報に示された回路で実現されていた。これは、山登
り法のなかの、特に、ＡＤＡ（Amplitude Dependent Al
gorithms）法と呼ばれる適応アルゴリズムを、応用した
ものである。このアルゴリズムは、制御変数Ｃ１，Ｃ
２，…Ｃｎによって挙動を決定される系を仮定したと
き、その系の評価関数を極に導くように制御変数を、逐
次、更新するもので、評価関数として誤差の２乗平均を
用いている。2. Description of the Related Art A conventional adaptive equalizer is disclosed in Japanese Patent Laid-Open No. 59-134927.
It was realized by the circuit shown in the publication. This is the ADA (Amplitude Dependent Al
gorithms) method is an application of an adaptive algorithm. This algorithm uses control variables C1 and C
2, ... Assuming a system whose behavior is determined by Cn, the control variables are sequentially updated so that the evaluation function of the system is led to a pole, and the mean square of the error is used as the evaluation function. ..
【０００３】この従来例は、平均化回路によって誤差の
２乗平均を求めている。この平均化回路を実現しようと
すれば、図２に示す移動平均回路１になる。図２の回路
は、基本的な適応フィルタの構成を示したものである。
有限インパルス応答フィルタ（Finite Impulse Respons
e Filter；以後これをＦＩＲフィルタと呼ぶ）で構成さ
れた適応フィルタの係数を制御変数Ｃ−２，Ｃ−１，…
Ｃ２としたものである。等化出力２と出力期待値３との
差から得られた誤差信号４と入力データの積は、誤差の
自乗をフィルタの係数で偏微分したものに相当し、フィ
ルタ係数をベクトルとして扱う場合の最大傾斜方向を表
わすベクトルとなる。これにフィードバック・ゲインα
を掛けたものの平均値をフィルタ係数の更新に用いるこ
とにより、２乗平均誤差を最小とする適応等化器とな
る。In this conventional example, the mean square of the error is calculated by an averaging circuit. In order to realize this averaging circuit, the moving average circuit 1 shown in FIG. 2 is obtained. The circuit of FIG. 2 shows the configuration of a basic adaptive filter.
Finite Impulse Respons
e Filter; hereinafter referred to as FIR filter), the coefficients of the adaptive filter configured by the control variables C-2, C-1, ...
It is C2. The product of the error signal 4 obtained from the difference between the equalized output 2 and the expected output value 3 and the input data corresponds to the square of the error partially differentiated by the coefficient of the filter, and when the filter coefficient is treated as a vector, It is a vector representing the maximum tilt direction. Feedback gain α
By using the average value of those multiplied by for updating the filter coefficient, an adaptive equalizer that minimizes the root mean square error is obtained.
【０００４】[0004]
【発明が解決しようとする課題】上記従来回路は、移動
平均回路１が、多数の遅延素子５と多入力加算器６１に
よって構成され、回路規模の増大を招くという問題が生
じることがわかった。図２では、簡略化のため、各係数
ごとに備えた係数更新回路を１係数についてのみ示して
ある。１係数のための移動平均回路１は、４個の遅延素
子５と、５入力加算器６１よりなる。５入力加算器６１
は、通常の２入力加算器４個で構成することができ、回
路規模もそれと同等になる。In the above-mentioned conventional circuit, it has been found that the moving average circuit 1 is composed of a large number of delay elements 5 and a multi-input adder 61, which causes a problem that the circuit scale is increased. In FIG. 2, for simplification, the coefficient updating circuit provided for each coefficient is shown only for one coefficient. The moving average circuit 1 for 1 coefficient includes four delay elements 5 and a 5-input adder 61. 5-input adder 61
Can be composed of four ordinary 2-input adders, and the circuit scale becomes equivalent to that.
【０００５】[0005]
【課題を解決するための手段】図１に示すように、移動
平均回路１を、それと同程度の低域濾波特性（遮断周波
数）を持つ無限インパルス応答フィルタ(Infinite Impu
lse Response Filter；以後これをＩＩＲフィルタと呼
ぶ）で置換することによって解決される。As shown in FIG. 1, a moving average circuit 1 is provided with an infinite impulse response filter (Infinite Impu Response Filter) having a low-pass filtering characteristic (cutoff frequency) equivalent to that of the moving average circuit 1.
lse Response Filter; hereinafter referred to as IIR filter).
【０００６】[0006]
【作用】従来の移動平均回路は、外乱等によって想定し
ない入力が系に加えられた場合に、係数の差分が急激に
変化し等化器の動作が安定点からずれることを防止する
ための、低域濾波特性を示すＦＩＲフィルタとみなすこ
とが可能である。通常、遮断周波数は、顕著な外来要因
を除去するように決められる。従って、遮断周波数は厳
密な精度を要求されないため、同程度の遮断周波数を有
するＩＩＲフィルタで代用することが可能であることが
わかった。In the conventional moving average circuit, when an unexpected input is applied to the system due to a disturbance or the like, the difference between the coefficients is suddenly changed to prevent the operation of the equalizer from deviating from the stable point. It can be regarded as an FIR filter showing a low-pass filtering characteristic. The cutoff frequency is usually determined to eliminate significant extraneous factors. Therefore, it has been found that the cutoff frequency does not require strict accuracy, and thus an IIR filter having the same cutoff frequency can be used as a substitute.
【０００７】[0007]
【実施例】本発明の第１の実施例を図１に示す。本実施
例はＦＩＲフィルタ８の出力Ｙと出力期待値ａの誤差ｅ
＝Ｙ−ａの自乗平均値を評価量Ｊとし、この評価量Ｊを
最小にする適応フィルタである。ここでＪ＝Ｅ(ｅ2）。
ただし、Ｅは平均値を求める演算。山登り法では、Ｊを
係数Ｃで偏微分し、その量より係数の更新量を求める。FIG. 1 shows a first embodiment of the present invention. In this embodiment, the error e between the output Y of the FIR filter 8 and the expected output value a
= Y-a is the mean square value of the evaluation amount J, and the evaluation amount J is an adaptive filter that is minimized. Where J = E (e 2 ).
However, E is a calculation for obtaining an average value. In the hill climbing method, J is partially differentiated by the coefficient C, and the updated amount of the coefficient is obtained from the amount.
【０００８】本実施例の特徴は、係数更新量を算出する
際、等価的に平均値を求めるためにＩＩＲフィルタを用
いる点にある。このＩＩＲフィルタは伝達関数で表現す
ると、少なくとも一つの極を有するものである。The feature of this embodiment is that an IIR filter is used to equivalently obtain an average value when calculating the coefficient update amount. This IIR filter has at least one pole when expressed by a transfer function.
【０００９】本発明の第１の実施例のより具体的な実施
例を図３に示す。等化を行なうＦＩＲフィルタ８と、等
化出力２から出力期待値３を引いて等化誤差４を求め、
係数の更新を行なう回路よりなる適応等化器である。こ
こでＩＩＲフィルタ７１は、図２の移動平均回路と同程
度の遮断特性を有するものである。ここでａ，ｂは、フ
ィルタの遮断周波数を決める係数である。係数値を２の
冪乗分の１若しくはせいぜいその中の二つの和若しくは
差に選べば、回路規模は極めて小さくなる。A more specific embodiment of the first embodiment of the present invention is shown in FIG. An equalization error 4 is obtained by subtracting the expected output value 3 from the equalization output 2 and the FIR filter 8 for equalization.
The adaptive equalizer is composed of a circuit for updating coefficients. Here, the IIR filter 71 has a cutoff characteristic similar to that of the moving average circuit of FIG. Here, a and b are coefficients that determine the cutoff frequency of the filter. If the coefficient value is selected to be a power of 2 or at most two sums or differences thereof, the circuit scale becomes extremely small.
【００１０】図４に、図２に示した５入力の移動平均回
路１と係数ａ＝０．２５，ｂ＝０.５とした図３のＩＩ
Ｒフィルタ７１の周波数特性を示す。横軸は標本化周波
数で規格化した周波数、縦軸は直流利得を１に規格化し
た振幅利得である。両者はほぼ同等の遮断周波数を有す
ることがわかる。In FIG. 4, the moving average circuit 1 of 5 inputs shown in FIG. 2 and the coefficient a = 0.25, b = 0.5 are used, and II of FIG.
The frequency characteristic of the R filter 71 is shown. The horizontal axis represents the frequency normalized by the sampling frequency, and the vertical axis represents the amplitude gain in which the DC gain is normalized to 1. It can be seen that both have almost the same cutoff frequency.
【００１１】遮断周波数を上記の実施例よりも低く設定
したい場合には、移動平均回路１をＩＩＲフィルタ７１
に置き換えたことによる回路規模の削減効果は、更に大
きくなる。移動平均回路１を用いて遮断周波数を下げる
ためには、多数の遅延素子と多入力加算器を備えて、平
均するデータの数を増やす必要がある。一方、ＩＩＲフ
ィルタ７１を用いれば、係数ｂの値を１に近づけること
によって回路規模のわずかな増加で遮断周波数を下げる
ことができる。When it is desired to set the cutoff frequency lower than that of the above embodiment, the moving average circuit 1 is connected to the IIR filter 71.
The effect of reducing the circuit scale due to the replacement by In order to reduce the cutoff frequency using the moving average circuit 1, it is necessary to increase the number of data to be averaged by providing a large number of delay elements and a multi-input adder. On the other hand, if the IIR filter 71 is used, the cutoff frequency can be lowered by slightly increasing the circuit scale by bringing the value of the coefficient b closer to 1.
【００１２】図５に示した周波数特性は、係数を調節し
て遮断周波数の低いＩＩＲフィルタを実現した例であ
る。ｂ＝３／４，７／８，１５／１６とするには、ｂ＝
１／２の場合に比べて、減算器を１個だけ増やせば良
い。それぞれ、ｂ＝１−１／４，１−１／８，１−１／
１６のように、２の冪乗数の差で表現されるためであ
る。The frequency characteristic shown in FIG. 5 is an example of realizing an IIR filter having a low cutoff frequency by adjusting the coefficient. To set b = 3/4, 7/8, 15/16, b =
Only one subtractor needs to be added as compared with the case of 1/2. B = 1-1 / 4, 1-1 / 8, 1-1 /
This is because it is represented by the difference of powers of 2 as in 16.
【００１３】本発明の第２の実施例を図６に示す。図６
は、ＦＩＲフィルタで構成した等化フィルタのタップ数
と同じ回数だけ演算器を多重使用して実現したＩＩＲフ
ィルタ回路である。係数ａ，ｂは、それぞれ２の冪乗、
１−２の冪乗で与えており、３個の加算器６と５個の遅
延素子５と６個のラッチ回路９で構成できる。２の冪乗
の演算１０は単に配線のシフトで良く、回路素子を必要
としない。遅延素子５は、ＦＩＲフィルタで構成した等
化フィルタのタップ数と同じ数だけの記憶素子を備え、
前段の加算器の出力を順次格納し、二つの出力ポートに
別のタイミングで順次出力する。遅延素子５の出力は、
フィードフォワード側とフィードバック側に別のタイミ
ングで信号を供給する必要があるため、２個の出力ポー
トを持つ。A second embodiment of the present invention is shown in FIG. Figure 6
Is an IIR filter circuit that is realized by multiple use of arithmetic units as many times as the number of taps of the equalization filter configured by the FIR filter. Coefficients a and b are powers of 2 respectively,
It is given by a power of 1-2, and can be composed of three adders 6, five delay elements 5 and six latch circuits 9. The power of 2 operation 10 is simply a wiring shift and does not require a circuit element. The delay element 5 includes as many storage elements as the number of taps of the equalization filter configured by the FIR filter,
The outputs of the adders in the preceding stages are sequentially stored and are sequentially output to the two output ports at different timings. The output of the delay element 5 is
Since it is necessary to supply signals to the feedforward side and the feedback side at different timings, it has two output ports.
【００１４】このフィルタの回路規模は、１２９０ゲー
トになる。一方、図２に示した５入力の移動平均回路
は、４個の加算器と２５個の遅延素子と１０個のラッチ
回路で構成される。回路規模は３３８０ゲートになる。
以上のように、移動平均回路の代わりにＩＩＲフィルタ
を用いることにより、この部分の回路規模を約１／３に
することができる。遮断周波数をより低く設定したい場
合には、回路の削減効果はさらに大きくなる。ＩＩＲフ
ィルタでは、係数値を調整するだけで特に回路の追加は
必要ない。移動平均回路では、入力数を増やすことで遮
断周波数の低減に対応しているため、この入力数に比例
して回路規模を増やす必要が生じる。移動平均回路も演
算器の多重使用により構成することが可能であるが、演
算速度が高く、高い多重度で動作させても、遅延素子は
削減できない。そのため、元来多数の遅延を必要とする
移動平均回路では、演算器多重使用の効果が、あまり期
待できない。The circuit scale of this filter is 1290 gates. On the other hand, the 5-input moving average circuit shown in FIG. 2 is composed of 4 adders, 25 delay elements, and 10 latch circuits. The circuit scale is 3380 gates.
As described above, by using the IIR filter instead of the moving average circuit, the circuit scale of this portion can be reduced to about 1/3. When it is desired to set the cutoff frequency lower, the reduction effect of the circuit is further increased. The IIR filter only adjusts the coefficient value and does not require any additional circuit. In the moving average circuit, since the cutoff frequency is reduced by increasing the number of inputs, it is necessary to increase the circuit scale in proportion to the number of inputs. The moving average circuit can also be configured by using multiple arithmetic units, but the calculation speed is high, and the delay elements cannot be reduced even when operated with high multiplicity. Therefore, in a moving average circuit which originally requires a large number of delays, the effect of using multiple arithmetic units cannot be expected so much.
【００１５】以上は、遮断周波数を厳密に規定する必要
のない場合について記載した。遮断周数を厳密に規定し
たりノッチ特性を持たせたい場合には、高次のＩＩＲフ
ィルタを採用すると有効である。The case where it is not necessary to strictly specify the cutoff frequency has been described above. It is effective to employ a high-order IIR filter in order to strictly define the cutoff frequency and to have a notch characteristic.
【００１６】[0016]
【発明の効果】本発明によれば、係数差分の平滑回路の
規模を１／２以下にすることができる。削減効果は、演
算器の多重化を行うとさらに大きい。また、遮断周波数
の変動に対して回路規模の増加なく対応できる。According to the present invention, the scale of the coefficient difference smoothing circuit can be reduced to 1/2 or less. The reduction effect is even greater when the arithmetic units are multiplexed. Further, it is possible to deal with the fluctuation of the cutoff frequency without increasing the circuit scale.
【図１】本発明の第１の実施例の回路図。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
【図２】従来例の回路図。FIG. 2 is a circuit diagram of a conventional example.
【図３】本発明の第１の実施例のより具体的な実施例の
回路図。FIG. 3 is a circuit diagram of a more specific embodiment of the first embodiment of the present invention.
【図４】本発明の回路特性を従来例と比較した説明図。FIG. 4 is an explanatory diagram comparing the circuit characteristics of the present invention with a conventional example.
【図５】本発明の回路特性の説明図。FIG. 5 is an explanatory diagram of circuit characteristics of the present invention.
【図６】本発明の第２の実施例の回路図。FIG. 6 is a circuit diagram of a second embodiment of the present invention.
１…移動平均回路、２…等化出力、３…出力期待値、４
…等化誤差、５…遅延回路、６…加算器、７…ＩＩＲフ
ィルタ、８…ＦＩＲフィルタ。1 ... Moving average circuit, 2 ... Equalized output, 3 ... Output expected value, 4
... Equalization error, 5 ... Delay circuit, 6 ... Adder, 7 ... IIR filter, 8 ... FIR filter.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 岡田 豊 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 田中 聡 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 花村 昭次 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体設計開発センタ内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yutaka Okada 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Satoshi Tanaka 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Shoji Hanamura 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Design Development Center
Claims (4)
える系と、前記系の挙動を評価関数で評価し、その結果
によって前記制御変数を変更する系よりなる信号処理装
置において、前記評価関数を前記制御変数で偏微分もし
くは差分して得られた関数を伝達関数として表現したと
きに、少なくとも一つの極を有するように、前記評価関
数を選んだことを特徴とする信号処理装置。1. A signal processing device comprising a system that changes behavior with at least one or more control variables, and a system that evaluates the behavior of the system with an evaluation function and changes the control variable according to the result. The signal processing device is characterized in that the evaluation function is selected so as to have at least one pole when a function obtained by performing partial differentiation or difference with the control variable is expressed as a transfer function.
力し係数値を増減できる有限インパルス応答フィルタ
と、前記有限インパルス応答フィルタの出力値から前記
出力に期待される値を減じて得られた誤差信号をもとに
して前記係数値を増減するための差分信号を求める信号
処理装置において、前記差分信号の急激な変動を抑制す
る無限インパルス応答フィルタを備えた信号処理装置。2. A finite impulse response filter capable of increasing or decreasing a coefficient value by inputting a sampled signal, and a value obtained by subtracting an expected value of the output from an output value of the finite impulse response filter. A signal processing device for obtaining a differential signal for increasing or decreasing the coefficient value based on the error signal, the signal processing device comprising an infinite impulse response filter for suppressing abrupt fluctuation of the differential signal.
答フィルタを、前記差分信号を第１の入力端子に入力す
る第１の加算器と、前記第１の加算器の出力に１タイム
・スロットの遅延を与える遅延回路と、前記遅延回路の
出力に第１の定数を乗じて第１の加算器の第２の入力端
子に与える回路と、前記第１の加算器の出力に前記遅延
回路の出力を加える第２の加算器と、前記第２の加算器
の出力に第２の定数を乗じる回路によって構成した信号
処理装置。3. The infinite impulse response filter according to claim 2, wherein a first adder for inputting the differential signal to a first input terminal and an output of the first adder for one time slot are provided. A delay circuit for giving a delay, a circuit for multiplying the output of the delay circuit by a first constant and applying it to the second input terminal of the first adder, and an output of the first adder for the output of the delay circuit And a circuit for multiplying the output of the second adder by a second constant.
入力端子に与えた第１の加算器と、前記第１の加算器の
出力を第１の入力端子に与えられた第２の加算器と、前
記第１の加算器の出力を格納できる遅延回路群と、前記
遅延回路群の第１の出力信号を第１の定数倍して前記第
１の加算器の第２の入力端子に与える回路手段と、前記
遅延回路群の第２の出力信号を前記第１の加算器の第２
の入力端子に与える回路手段と、前記第２の加算器の出
力を第２の定数倍して出力する回路手段とにより構成し
た信号処理装置。4. The first adder according to claim 2, wherein the input signal is applied to the first input terminal, and the second adder according to which the output of the first adder is applied to the first input terminal. An adder, a delay circuit group capable of storing the output of the first adder, and a second input terminal of the first adder by multiplying a first output signal of the delay circuit group by a first constant. And a second output signal of the delay circuit group to the second adder of the first adder.
And a circuit means for outputting the output of the second adder by multiplying it by a second constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4823892A JPH05252000A (en) | 1992-03-05 | 1992-03-05 | Signal processing unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4823892A JPH05252000A (en) | 1992-03-05 | 1992-03-05 | Signal processing unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05252000A true JPH05252000A (en) | 1993-09-28 |
Family
ID=12797869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4823892A Pending JPH05252000A (en) | 1992-03-05 | 1992-03-05 | Signal processing unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05252000A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010070755A1 (en) * | 2008-12-18 | 2010-06-24 | 株式会社島津製作所 | Tft array inspecting method, and tft array inspecting device |
| WO2013128783A1 (en) * | 2012-03-01 | 2013-09-06 | 日本電気株式会社 | Digital-signal processing device, reception device, and signal transmission/reception system |
| JP6388754B1 (en) * | 2017-09-15 | 2018-09-12 | 三菱電機株式会社 | Signal processing device, sensor device, and signal processing method |
-
1992
- 1992-03-05 JP JP4823892A patent/JPH05252000A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010070755A1 (en) * | 2008-12-18 | 2010-06-24 | 株式会社島津製作所 | Tft array inspecting method, and tft array inspecting device |
| JP5182595B2 (en) * | 2008-12-18 | 2013-04-17 | 株式会社島津製作所 | TFT array inspection method and TFT array inspection apparatus |
| WO2013128783A1 (en) * | 2012-03-01 | 2013-09-06 | 日本電気株式会社 | Digital-signal processing device, reception device, and signal transmission/reception system |
| JPWO2013128783A1 (en) * | 2012-03-01 | 2015-07-30 | 日本電気株式会社 | Digital signal processing device, receiving device, and signal transmission / reception system |
| US9385766B2 (en) | 2012-03-01 | 2016-07-05 | Nec Corporation | Digital signal processing device, receiving device, and signal transmitting and receiving system |
| JP6388754B1 (en) * | 2017-09-15 | 2018-09-12 | 三菱電機株式会社 | Signal processing device, sensor device, and signal processing method |
| WO2019053896A1 (en) * | 2017-09-15 | 2019-03-21 | 三菱電機株式会社 | Signal processing device, sensor device, and signal processing method |
| US10458789B2 (en) | 2017-09-15 | 2019-10-29 | Mitsubishi Electric Corporation | Signal processing device, sensor device, and signal processing method |
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