JPH05243720A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH05243720A JPH05243720A JP4041192A JP4119292A JPH05243720A JP H05243720 A JPH05243720 A JP H05243720A JP 4041192 A JP4041192 A JP 4041192A JP 4119292 A JP4119292 A JP 4119292A JP H05243720 A JPH05243720 A JP H05243720A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- solder
- photoresist layer
- circuit pattern
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はクォード・フラット・パ
ッケージタイプのＬＳＩを搭載する混成集積回路装置に
関し、詳細には、そのＬＳＩの外部リードの固着構造に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device mounting a quad flat package type LSI, and more particularly to a structure for fixing external leads of the LSI.
【０００２】[0002]
【従来の技術】図４および図５を参照して従来の混成集
積回路装置を説明する。なお、図４はクォード・フラッ
ト・パッケージタイプのＬＳＩ固着部の平面図であり、
図５はクォード・フラット・パッケージタイプのＬＳＩ
固着部の側面図である。小型化のため、混成集積回路装
置の搭載素子にはベアチップ若しくはクォード・フラッ
ト・パッケージ（以下、ＱＦＰと称する）が使用され
る。典型的なＱＦＰ(40)は、図４に示すように、一辺が
１０ｍｍのチップ(42)を一辺１５ｍｍ程度のサイズに樹
脂モールドしたものである。数１０におよぶ外部リード
(46)はリード幅が０．３５ｍｍ、リードピッチが０．６
５ｍｍであって、その一端がチップ(42)の電極(44)にワ
イアボンディングされる。2. Description of the Related Art A conventional hybrid integrated circuit device will be described with reference to FIGS. 4 is a plan view of the quad flat package type LSI fixing part,
Figure 5 is a quad flat package type LSI
It is a side view of a fixed part. For miniaturization, a bare chip or a quad flat package (hereinafter referred to as QFP) is used as a mounting element of the hybrid integrated circuit device. As shown in FIG. 4, a typical QFP (40) is a chip (42) having a side of 10 mm and resin-molded to a size of a side of about 15 mm. Tens of external leads
(46) has a lead width of 0.35 mm and a lead pitch of 0.6
5 mm, one end of which is wire bonded to the electrode (44) of the chip (42).
【０００３】図５を参照すると、集積回路基板(50)には
放熱特性および加工性を考慮して略２ｍｍ厚のアルミニ
ウムが使用され、絶縁性の向上のためにその表面が陽極
酸化処理される。パッド(54)等の回路パターンは、ポリ
イミド樹脂等の接着性を有する熱硬化性絶縁樹脂と略３
５μｍ厚の銅箔とのクラッド材を温度１５０℃〜１７０
℃、１平方センチメートル当り５０〜１００Ｋｇの圧力
で集積回路基板(50)にホットプレスした後、その銅箔を
ホトエッチングする等して所定パターンに形成される。
なお、現実の混成集積回路装置ではベアチップを固着す
るダイボンドパッド、ベアチップの電極と回路パターン
を接続するワイアボンディングパッド、混成集積回路装
置の外部リードを固着する外部リード用パッド、図４に
その一部を示す導電路(56)が同時形成される。また、前
記熱硬化性絶縁樹脂はこのホットプレス工程で完全硬化
して略３５μｍ厚の絶縁樹脂層(52)となる。Referring to FIG. 5, aluminum having a thickness of about 2 mm is used for the integrated circuit board (50) in consideration of heat dissipation characteristics and workability, and the surface thereof is anodized to improve insulation. .. The circuit pattern of the pad (54) and the like is made of a thermosetting insulating resin having adhesiveness such as polyimide resin, and is approximately 3
Clad material with a copper foil of 5 μm in temperature 150 ° C. to 170 ° C.
After hot pressing the integrated circuit board (50) at a pressure of 50 to 100 kg per square centimeter at a temperature of 50 ° C., the copper foil is photo-etched to form a predetermined pattern.
In an actual hybrid integrated circuit device, a die bond pad for fixing a bare chip, a wire bonding pad for connecting an electrode of the bare chip and a circuit pattern, an external lead pad for fixing an external lead of the hybrid integrated circuit device, a part of which is shown in FIG. Is formed at the same time. Further, the thermosetting insulating resin is completely cured in this hot pressing step to form an insulating resin layer (52) having a thickness of about 35 μm.
【０００４】ＱＦＰ(40)の固着は以下のように行われ
る。先ず、ＱＦＰ(40)の外部リード(46)が固着されるパ
ッド(54)および同時に半田固着される他の半導体素子、
部品のためのパッドに、重量混合比が６３／３７の錫
（Ｓｎ）、鉛（Ｐｂ）そして少量のフラックスを混合し
たクリーム状の半田をスクリーン印刷し、この半田クリ
ームの粘性を利用してＱＦＰ(40)が仮固着される。そし
て、１８３℃、数分の条件でリフローしてＱＦＰ(40)、
その他の半田固着素子、部品が完全固着される。The fixing of the QFP (40) is performed as follows. First, the pad (54) to which the external lead (46) of the QFP (40) is fixed, and another semiconductor element to be soldered at the same time,
Screen-printed creamy solder mixed with tin (Sn), lead (Pb) and a small amount of flux in a weight mixing ratio of 63/37 on the pad for parts, and using the viscosity of this solder cream, QFP (40) is temporarily fixed. Then, reflowing under the condition of 183 ° C. for several minutes, QFP (40),
Other solder fixing elements and parts are completely fixed.
【０００５】混成集積回路装置は、この後、ワイアボン
ディング、オーバコート等の処理工程を経て、樹脂製の
ケースで封止される。The hybrid integrated circuit device is then sealed with a resin case after undergoing processing steps such as wire bonding and overcoating.
【０００６】[0006]
【発明が解決しようとする課題】ＱＦＰは技術開発に伴
い高集積小型化傾向になってきている。それによってＱ
ＦＰのリード間ピッチも微細となり、リードを固着する
固着パッド(54)のピッチ間隔も微細となってきている。
固着パッドの微細間隔はフォトエッチング技術によって
リード間ピッチに対応して容易に形成することができ
る。The QFP tends to be highly integrated and miniaturized with technological development. Thereby Q
The pitch between the leads of the FP has become fine, and the pitch interval of the fixing pads (54) for fixing the leads has also become fine.
The fine gaps between the fixed pads can be easily formed in accordance with the pitch between the leads by a photo etching technique.
【０００７】しかしながら、パッド(54)のピッチ間隔が
微細である場合には、半田クリーム量の制御が困難であ
るとともに、パッド(54)間隙にフラックスが浸透してパ
ッド(54)の間隙に溶融半田が流出し、ブリッジが発生す
ることがあった。この問題は上述したようにＱＦＰ(40)
の小型化、多ピン化に伴ってますます顕著となる。この
発明は上述した課題に鑑みてなされたもので、この発明
の目的は、極めて微細なリードピッチのＱＦＰを高品質
に半田固着できる構造の混成集積回路装置を提供するこ
とにある。However, when the pitch interval of the pads (54) is fine, it is difficult to control the amount of solder cream, and flux penetrates into the gaps of the pads (54) and melts into the gaps of the pads (54). Sometimes solder leaked out and a bridge was generated. This problem is caused by QFP (40) as described above.
It becomes more and more prominent with the miniaturization and the increase in the number of pins. The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a hybrid integrated circuit device having a structure capable of soldering a QFP having an extremely fine lead pitch with high quality.
【０００８】[0008]
【課題を解決するための手段】上述した課題を解決し、
目的を達成するため、この発明に係わる混成集積回路
は、絶縁性基板と、この絶縁性基板上に所定の形状に形
成した回路パターンと、この回路パターン厚より厚肉で
あって、半導体素子が半田固着される固着パッドの上部
を開口したホトレジスト層とを具備し、前記ホトレジス
ト層の開口領域の固着パッド上に半田を塗布し、前記半
導体素子が前記開口領域で固着されたことを特徴として
いる。[Means for Solving the Problems]
To achieve the object, a hybrid integrated circuit according to the present invention has an insulating substrate, a circuit pattern formed on the insulating substrate in a predetermined shape, and a semiconductor element having a thickness larger than the circuit pattern thickness. And a photoresist layer having an opening at the top of a fixing pad to be soldered, wherein solder is applied to the fixing pad in the opening region of the photoresist layer, and the semiconductor element is fixed in the opening region. ..
【０００９】また、この発明に係わる混成集積回路は、
絶縁性基板と、この絶縁性基板上に所定の形状に形成し
た回路パターンと、この回路パターン厚より厚肉であっ
て、クォード・フラット・パッケージタイプの半導体素
子が半田固着される固着パッドの上部を開口したホトレ
ジスト層とを具備し、前記ホトレジスト層の開口領域の
固着パッド上に半田を塗布し、前記半導体素子が前記開
口領域で固着されたことを特徴としている。The hybrid integrated circuit according to the present invention is
An insulating substrate, a circuit pattern formed in a predetermined shape on the insulating substrate, and an upper portion of a fixing pad that is thicker than the circuit pattern thickness and to which a quad flat package type semiconductor element is soldered and fixed. A photoresist layer having openings formed therein, and solder is applied onto the fixing pad in the opening region of the photoresist layer, and the semiconductor element is fixed in the opening region.
【００１０】[0010]
【作用】以上のように構成される混成集積回路装置にお
いては、回路パターン上に厚肉のホトレジスト層を形成
し、半田固着が行われるパッドの上部を開口することに
より、過剰な半田クリームの充填を防止し、ホトレジス
ト層表面を平坦にして半田流れを防止する。In the hybrid integrated circuit device configured as described above, a thick photoresist layer is formed on the circuit pattern and the upper portion of the pad to which the solder is fixed is opened to fill the excessive solder cream. And prevent the solder flow by flattening the surface of the photoresist layer.
【００１１】また、この混成集積回路装置では、基板の
全面にホトレジスト層を形成し、半田固着が行われるパ
ッドの上部を開口することにより、過剰な半田クリーム
の充填を防止し、ホトレジスト層表面を平坦にして半田
流れを防止すると共にオーバコート層を不要にする。Further, in this hybrid integrated circuit device, a photoresist layer is formed on the entire surface of the substrate, and the upper portion of the pad to which the solder is fixed is opened to prevent excessive solder cream from being filled and the surface of the photoresist layer to be covered. Flattening prevents solder flow and eliminates the need for an overcoat layer.
【００１２】[0012]
【実施例】図１乃至図３を参照して本発明の一実施例を
説明する。なお、図は所定の製造段階の混成集積回路基
板の断面図であり、クォード・フラット・パッケージ
（以下、再びＱＦＰと称する）タイプのＬＳＩの固着部
周辺を示す。図１を参照すると、本発明の混成集積回路
装置は絶縁金属基板(10)、この絶縁金属基板(10)上に絶
縁樹脂層(12)を介して所定形状に形成したパッド(14)等
の回路パターン、所定のパッド(14)の一部が開口するよ
う選択形成したホトレジスト層(16)、前記パッド(14)に
外部リード(32)を半田固着したＱＦＰ(30)等からなる構
造を備える。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS. The figure is a cross-sectional view of the hybrid integrated circuit substrate at a predetermined manufacturing stage, and shows the periphery of a fixed portion of a quad flat package (hereinafter, referred to as QFP) type LSI. Referring to FIG. 1, the hybrid integrated circuit device of the present invention comprises an insulating metal substrate (10), a pad (14) formed in a predetermined shape on the insulating metal substrate (10) via an insulating resin layer (12), and the like. The structure includes a circuit pattern, a photoresist layer (16) selectively formed so that a part of a predetermined pad (14) is opened, and a QFP (30) in which an external lead (32) is soldered and fixed to the pad (14). ..
【００１３】絶縁金属基板(10)には放熱特性および加工
性を考慮して略２ｍｍ厚のアルミニウムが使用され、絶
縁性の向上のためにその表面が陽極酸化処理される。パ
ッド(14)等の回路パターンは、ポリイミド樹脂等の接着
性を有する熱硬化性絶縁樹脂と略３５μｍ厚の銅箔との
クラッド材を温度１５０℃〜１７０℃、１平方センチメ
ートル当り５０〜１００Ｋｇの圧力で絶縁金属基板(10)
にホットプレスした後、その銅箔をホトエッチングする
等して所定パターンに形成される。なお、現実の混成集
積回路装置ではバス等の導電路、ベアチップを固着する
ダイボンドパッド、ベアチップの電極と回路パターンを
接続するワイアボンディングパッド、混成集積回路装置
の外部リードを固着する外部リード用パッドが同時形成
される。また、前記熱硬化性絶縁樹脂はこのホットプレ
ス工程で完全硬化して略３５μｍ厚の絶縁樹脂層(12)と
なる。Aluminum having a thickness of about 2 mm is used for the insulating metal substrate (10) in consideration of heat dissipation characteristics and workability, and the surface thereof is anodized to improve the insulating property. The circuit pattern such as the pad (14) is formed by using a clad material made of a thermosetting insulating resin having adhesiveness such as polyimide resin and a copper foil having a thickness of about 35 μm at a temperature of 150 ° C. to 170 ° C. With Insulation Metal Substrate (10)
After hot pressing, the copper foil is photo-etched to form a predetermined pattern. In an actual hybrid integrated circuit device, a conductive path such as a bus, a die bond pad for fixing a bare chip, a wire bonding pad for connecting an electrode of the bare chip and a circuit pattern, and an external lead pad for fixing an external lead of the hybrid integrated circuit device are provided. Simultaneously formed. Further, the thermosetting insulating resin is completely cured in this hot pressing process to form an insulating resin layer (12) having a thickness of about 35 μm.
【００１４】ホトレジスト層(16)は半導体素子の製造に
利用されるホトレジストをスピナ等により絶縁金属基板
(10)の所定の領域あるいは全面に塗布し、これを選択露
光してパッド(14)の一部を開口したものである。このホ
トレジスト層(16)はパッド(14)等の銅箔回路パターンの
３倍の略０．１ｍｍ厚であるため、ホトレジスト層(16)
の平面は開口部を除き実質的に平坦となる。なお、ホト
レジスト層(16)を絶縁金属基板(10)の全面に形成する場
合にはこのホトレジスト層(16)をオーバコート層として
利用することができる。The photoresist layer (16) is an insulating metal substrate formed by spinner or the like for photoresist used in the manufacture of semiconductor devices.
It is applied on a predetermined area or the entire surface of (10) and selectively exposed to light to open a part of the pad (14). Since this photoresist layer (16) is about 0.1 mm thick, which is three times as thick as the copper foil circuit pattern such as the pad (14), the photoresist layer (16)
Is substantially flat except for the opening. When the photoresist layer (16) is formed on the entire surface of the insulating metal substrate (10), this photoresist layer (16) can be used as an overcoat layer.
【００１５】次に、図２および図３を参照してＱＦＰ(3
0)の固着方法を説明する。図２は半田クリーム(20)のス
クリーン印刷の様子を示す。図示するように、ホトレジ
スト層(16)形成が終了した絶縁金属基板(10)の当該面
に、ホトレジスト層(16)の開口部に対応する開口部を形
成したメタルマスク(18)を位置合わせし、重量混合比が
６３／３７の錫（Ｓｎ）、鉛（Ｐｂ）そして少量のフラ
ックスを混合した半田クリーム(20)が前記メタルマスク
(18)の開口部に充填される。この際、メタルマスク(18)
上の半田クリーム量およびスキージの押圧力を制御すれ
ば、メタルマスク(18)の開口部に充填される半田クリー
ム(20)量をメタルマスク(18)厚に近い値に制御すること
ができ、過剰半田によるブリッジの問題が解決できる。Next, referring to FIGS. 2 and 3, QFP (3
The fixing method of 0) will be described. FIG. 2 shows the screen printing of the solder cream (20). As shown in the figure, a metal mask (18) having openings corresponding to the openings of the photoresist layer (16) is aligned with the relevant surface of the insulating metal substrate (10) on which the photoresist layer (16) has been formed. The solder mask (20), which is a mixture of tin (Sn), lead (Pb) and a small amount of flux with a weight mixing ratio of 63/37, is the metal mask.
It is filled in the opening of (18). At this time, metal mask (18)
By controlling the amount of solder cream above and the pressing force of the squeegee, it is possible to control the amount of solder cream (20) filled in the opening of the metal mask (18) to a value close to the thickness of the metal mask (18), The problem of bridging due to excessive solder can be solved.
【００１６】図３はメタルマスク(18)除去後の絶縁金属
基板(10)を示す。この絶縁金属基板(10)の所定位置にＱ
ＦＰ(30)、その他の半導体素子、部品が自動機を使用し
て配置され、半田クリーム(20)の粘性により仮固着され
る。この後、１８３℃、数分の条件でリフローしてＱＦ
Ｐ(30)、その他の半田固着素子、部品が同時固着され、
先に説明した図１の構造が得られる。FIG. 3 shows the insulating metal substrate 10 after the metal mask 18 has been removed. Q at the specified position of this insulating metal substrate (10).
The FP (30), other semiconductor elements, and parts are arranged by using an automatic machine and temporarily fixed due to the viscosity of the solder cream (20). After this, reflow under the condition of 183 ° C for a few minutes to perform QF
P (30), other solder fixing elements, parts are fixed simultaneously,
The structure of FIG. 1 described above is obtained.
【００１７】以上説明したように、従来の混成集積回路
装置ではパッド間がパッド厚だけ低くなるため、リフロ
ー時の溶融半田がパッド間隙に流出しがちであるに対し
て、本発明の混成集積回路装置はパッド(14)等の回路パ
ターン上に厚肉のホトレジスト層(16)を形成したため、
パッド(14)周辺の構造が単純となり、半田流出が妨げら
れる。その結果、パッド(14)間のブリッジが防止され
る。なお、ＱＦＰ(30)の半田固着を例として本発明を説
明したが、本発明はＱＦＰ(30)以外の、微細リードの素
子、部品の半田固着に利用可能である。As described above, in the conventional hybrid integrated circuit device, the distance between the pads is reduced by the pad thickness, so that the molten solder during reflow tends to flow out into the pad gap, whereas the hybrid integrated circuit of the present invention. Since the device formed a thick photoresist layer (16) on the circuit pattern such as the pad (14),
The structure around the pad (14) is simplified, and solder outflow is prevented. As a result, bridges between pads 14 are prevented. Although the present invention has been described by taking the solder fixing of the QFP (30) as an example, the present invention can be used for solder fixing of fine lead elements and parts other than the QFP (30).
【００１８】また、この実施例では基板に金属基板を用
いて説明したが、この発明は金属基板に限定されるもの
ではなく、例えば、セラミックス基板、ガラスエポキシ
基板等の絶縁基板を用いても同様である。In this embodiment, a metal substrate is used as the substrate, but the present invention is not limited to the metal substrate. For example, an insulating substrate such as a ceramic substrate or a glass epoxy substrate may be used. Is.
【００１９】[0019]
【発明の効果】以上述べたように本発明の混成集積回路
装置は、回路パターン上に厚肉のホトレジスト層を形成
して、半田固着が行われるパッド周辺の構造を単純にし
たため、半田流出によるブリッジが防止される。また、
ホトレジスト層を絶縁性基板の全面に形成する場合には
オーバコートが不要となる利点を有する。As described above, in the hybrid integrated circuit device of the present invention, since the thick photoresist layer is formed on the circuit pattern to simplify the structure around the pad where the solder is fixed, the solder outflow occurs. Bridges are prevented. Also,
When the photoresist layer is formed on the entire surface of the insulating substrate, there is an advantage that the overcoat is unnecessary.
【図１】本発明の一実施例の要部断面図。FIG. 1 is a sectional view of an essential part of an embodiment of the present invention.
【図２】本発明の一実施例の所定の製造段階の要部断面
図。FIG. 2 is a sectional view of an essential part in a predetermined manufacturing stage according to an embodiment of the present invention.
【図３】本発明の一実施例の所定の製造段階の要部断面
図。FIG. 3 is a cross-sectional view of an essential part in a predetermined manufacturing stage according to an embodiment of the present invention.
【図４】従来例の平面図FIG. 4 is a plan view of a conventional example.
【図５】従来例の要部断面図。FIG. 5 is a sectional view of a main part of a conventional example.
１０ 絶縁金属基板 １２ 絶縁樹脂層 １４ パッド １６ ホトレジスト層 ２０ ロウ材 ３０ クォード・フラット・パッケージ ３２ 外部リード 10 Insulating Metal Substrate 12 Insulating Resin Layer 14 Pad 16 Photoresist Layer 20 Brazing Material 30 Quad Flat Package 32 External Lead
Claims (2)
の形状に形成した回路パターンと、この回路パターン厚
より厚肉であって、半導体素子が半田固着される固着パ
ッドの上部を開口したホトレジスト層とを具備し、前記
ホトレジスト層の開口領域の固着パッド上に半田を塗布
し、前記半導体素子が前記開口領域で固着されたことを
特徴とする混成集積回路装置。1. An insulating substrate, a circuit pattern formed in a predetermined shape on the insulating substrate, and an opening at an upper portion of a fixing pad thicker than the circuit pattern thickness and to which a semiconductor element is soldered and fixed. And a photoresist layer, wherein solder is applied on the fixing pad in the opening region of the photoresist layer, and the semiconductor element is fixed in the opening region.
の形状に形成した回路パターンと、この回路パターン厚
より厚肉であって、クォード・フラット・パッケージタ
イプの半導体素子が半田固着される固着パッドの上部を
開口したホトレジスト層とを具備し、前記ホトレジスト
層の開口領域の固着パッド上に半田を塗布し、前記半導
体素子が前記開口領域で固着されたことを特徴とする混
成集積回路装置。2. An insulative substrate, a circuit pattern formed in a predetermined shape on the insulative substrate, and a quad flat package type semiconductor element thicker than the thickness of the circuit pattern and fixed by soldering. And a photoresist layer having an opening above the fixing pad, wherein solder is applied to the fixing pad in the opening region of the photoresist layer, and the semiconductor element is fixed in the opening region. apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4041192A JPH05243720A (en) | 1992-02-27 | 1992-02-27 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4041192A JPH05243720A (en) | 1992-02-27 | 1992-02-27 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05243720A true JPH05243720A (en) | 1993-09-21 |
Family
ID=12601564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4041192A Pending JPH05243720A (en) | 1992-02-27 | 1992-02-27 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05243720A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0723387A1 (en) * | 1995-01-19 | 1996-07-24 | Digital Equipment Corporation | Soldermask gasketing of printed wiring board surface mount pads |
| US8168376B2 (en) * | 2008-01-22 | 2012-05-01 | Nitto Denko Corporation | Manufacturing method of optical waveguide device |
-
1992
- 1992-02-27 JP JP4041192A patent/JPH05243720A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0723387A1 (en) * | 1995-01-19 | 1996-07-24 | Digital Equipment Corporation | Soldermask gasketing of printed wiring board surface mount pads |
| JPH08236914A (en) * | 1995-01-19 | 1996-09-13 | Digital Equip Corp <Dec> | Solder mask for bonding pad on surface of printed wiring board |
| US8168376B2 (en) * | 2008-01-22 | 2012-05-01 | Nitto Denko Corporation | Manufacturing method of optical waveguide device |
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