JPH10233463A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH10233463A JPH10233463A JP1266597A JP1266597A JPH10233463A JP H10233463 A JPH10233463 A JP H10233463A JP 1266597 A JP1266597 A JP 1266597A JP 1266597 A JP1266597 A JP 1266597A JP H10233463 A JPH10233463 A JP H10233463A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- resin
- wiring
- wiring board
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その製造方法に係り、特にボールグリッドアレイ（ＢＧ
Ａ）パッケージ構造を有する半導体装置の配線基板およ
び半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a ball grid array (BG).
A) The present invention relates to a wiring board of a semiconductor device having a package structure and a method of manufacturing the semiconductor device.
【０００２】[0002]
【従来の技術】例えば集積回路カード、ゲーム用マスク
ＲＯＭカード、小型携帯電話器などに使用される半導体
装置は、パッケージの小型化・薄型化に対する要求が特
に強い。このような要求に応じるべく、ベア状態の半導
体チップ（ベア・チップ）の実装技術が発展しており、
チップ・オン・ボード（ＣＯＢ）実装、フリップチップ
実装などが知られている。2. Description of the Related Art A semiconductor device used for an integrated circuit card, a mask ROM card for a game, a small portable telephone, or the like has a particularly strong demand for a smaller and thinner package. In order to respond to such demands, mounting technology of bare semiconductor chips (bare chips) has been developed,
Chip-on-board (COB) mounting, flip-chip mounting, and the like are known.
【０００３】上記フリップチップ実装は、ベア・チップ
の素子形成面の金属バンプ電極を配線基板上のチップ搭
載面に形成されている電極パッドに押し付けて接続（フ
リップチップボンディング）するものである。これは、
ワイヤーボンディングを必要とするＣＯＢ実装よりも実
装密度が優れているが、基板の熱膨脹などに起因する応
力が基板・チップの接続部に加わって接続の信頼性を損
なうという問題がある。[0003] In the flip chip mounting, a metal bump electrode on an element forming surface of a bare chip is pressed against an electrode pad formed on a chip mounting surface on a wiring board to make connection (flip chip bonding). this is,
Although the mounting density is higher than that of the COB mounting that requires wire bonding, there is a problem that the stress due to thermal expansion of the substrate is applied to the connection portion between the substrate and the chip, and the reliability of the connection is impaired.
【０００４】上記フリップチップ実装の改良例として、
ベア・チップと基板との間に樹脂を介在させて基板・チ
ップ相互を機械的に固定した片面樹脂封止型パッケージ
構造が知られており、その一例としてボールグリッドア
レイ（ＢＧＡ）パッケージ構造が知られている。As an improved example of the flip chip mounting,
A single-sided resin-sealed package structure in which a substrate and a chip are mechanically fixed to each other by interposing a resin between a bare chip and a substrate is known, and a ball grid array (BGA) package structure is known as an example. Have been.
【０００５】図７は、従来のＢＧＡパッケージ構造を有
する半導体装置の断面構造の一例を概略的に示してい
る。図７のパッケージ構造は、主面に被接続部を含む配
線パターン１３を有する例えば二層の配線基板１１と、
上記配線基板１１のチップ搭載面に金属バンプ電極（例
えば半田バンプ）１２を介してフェースダウン型に実装
された半導体チップ１０と、上記半導体チップ１０と配
線基板１１との間に充填された封止樹脂１６と、前記配
線基板１１のチップ非搭載面に形成され、前記配線パタ
ーン１３に電気的に接続された外部接続用端子２２とを
具備する。FIG. 7 schematically shows an example of a sectional structure of a semiconductor device having a conventional BGA package structure. The package structure of FIG. 7 includes, for example, a two-layer wiring board 11 having a wiring pattern 13 including a portion to be connected on a main surface;
A semiconductor chip 10 mounted face down on a chip mounting surface of the wiring board 11 via metal bump electrodes (for example, solder bumps) 12; and a sealing filled between the semiconductor chip 10 and the wiring board 11. The semiconductor device includes a resin 16 and an external connection terminal 22 formed on a surface of the wiring board 11 where a chip is not mounted and electrically connected to the wiring pattern 13.
【０００６】この場合、前記外部接続用端子２２とし
て、配線基板１１の下面で垂直方向にバンプ状に形成さ
れ、スルーホール配線１３ｂ、あるいは層間配線パター
ン１３ａとブラインドビアホール配線を介して配線パタ
ーン１３に接続されている。In this case, the external connection terminals 22 are formed in the form of bumps in the vertical direction on the lower surface of the wiring board 11 and are connected to the wiring pattern 13 through the through-hole wiring 13b or the interlayer wiring pattern 13a and the blind via-hole wiring. It is connected.
【０００７】前記封止樹脂１６の形成に際しては、例え
ば樹脂供給装置（図示せず）のノズルから液状の樹脂を
基板１１上に供給し、樹脂の表面張力と毛細管現象を利
用してチップ・基板間に樹脂を流し込んで充填した後に
硬化させている。In forming the sealing resin 16, for example, a liquid resin is supplied onto the substrate 11 from a nozzle of a resin supply device (not shown), and the chip / substrate is made utilizing the surface tension of the resin and the capillary phenomenon. After the resin is poured and filled in between, it is cured.
【０００８】前記したようなパッケージ構造を有する半
導体装置の使用に際して、図７中に点線で示すように応
用製品のマザーボード５０上の配線に配線基板１１の下
面の外部接続用バンプ２２が例えば半田付けにより実装
される。When a semiconductor device having the above-described package structure is used, the external connection bumps 22 on the lower surface of the wiring board 11 are soldered to the wiring on the motherboard 50 of the application product as shown by a dotted line in FIG. Implemented by
【０００９】この場合、前記配線基板１１は、チップ１
０とマザーボード５０とのピッチ変換の役割を持つイン
ターポーザとして機能するが、その材質として、コスト
低減や生産性向上の要求により、セラミック系の材料か
ら樹脂系の材料に転換されつつあり、これに伴い、以下
に述べるような問題（１）、（２）が生じる。In this case, the wiring board 11 is provided with the chip 1
Although it functions as an interposer having a role of converting the pitch between the substrate and the motherboard 50, the material is being switched from a ceramic material to a resin material due to demands for cost reduction and productivity improvement. The following problems (1) and (2) occur.
【００１０】（１）チップ１０と配線基板１１の熱膨脹
係数が異なるので、例えば図８に示すように、熱応力に
より配線基板１１が反り、コプラナリティが低下し、マ
ザーボード５０への半導体装置の実装が困難になる。仮
に実装がされても、基板１１・マザーボード５０間の半
田接合部、チップ１０・基板１１間の半田接合部に歪み
が生じ、疲労寿命が低下する。(1) Since the thermal expansion coefficients of the chip 10 and the wiring board 11 are different, the wiring board 11 is warped due to thermal stress as shown in FIG. 8, for example, and the coplanarity is reduced. It becomes difficult. Even if mounted, the solder joint between the substrate 11 and the motherboard 50 and the solder joint between the chip 10 and the substrate 11 are distorted, and the fatigue life is shortened.
【００１１】（２）樹脂系の配線基板１１は保管中に吸
湿し、チップ１０・基板１１間の充填樹脂１６まで水分
が達するので、マザーボード５０への半導体装置の実装
時の熱により気化し、例えば図８に示すように樹脂１６
が散発的に弾けてひび割れ（いわゆる、ポプコーンクラ
ック）１７が生じる。(2) Since the resin-based wiring board 11 absorbs moisture during storage and reaches the filling resin 16 between the chip 10 and the board 11, the wiring board 11 is vaporized by heat when the semiconductor device is mounted on the motherboard 50, For example, as shown in FIG.
Sporadically pops and cracks (so-called popcorn cracks) 17 occur.
【００１２】なお、特開平８−９７３１３号公報の「マ
ルチチップモジュール」には、フリップチップ搭載用の
ガラスエポキシ回路基板上の素子搭載部に形成した絶縁
性保護膜を選択的にエッチングして接続端子間を通る溝
を形成しておき、チップ搭載後に流し込む封止樹脂の流
れを均一化し、ボイドの発生を防止する技術が開示され
ているが、この技術は前記したような問題（１）、
（２）を解決するものではない。The "multi-chip module" disclosed in Japanese Patent Application Laid-Open No. 8-97313 is connected by selectively etching an insulating protective film formed on an element mounting portion on a glass epoxy circuit board for flip chip mounting. A technology has been disclosed in which a groove is formed between terminals to make the flow of the sealing resin poured after mounting the chip uniform and to prevent the occurrence of voids. However, this technology has the above-mentioned problems (1),
It does not solve (2).
【００１３】[0013]
【発明が解決しようとする課題】上記したように従来の
片面樹脂封止型パッケージ構造を有する半導体装置は、
チップと樹脂系配線基板の熱膨脹係数が異なると、熱応
力によりパッケージが反り、マザーボードへの半導体装
置の実装が困難になり、チップ・基板間の半田接合部、
基板・マザーボード間の半田接合部に歪みが生じ、疲労
寿命が低下するという問題、基板の吸湿性に起因してチ
ップ・基板間の充填樹脂まで達した水分がマザーボード
への実装時の熱により気化した時に樹脂のひび割れが生
じるという問題があった。As described above, the conventional semiconductor device having a single-sided resin-sealed package structure is:
If the chip and the resin-based wiring board have different coefficients of thermal expansion, the package will warp due to thermal stress, making it difficult to mount the semiconductor device on the motherboard.
Distortion occurs at the solder joint between the board and motherboard, shortening the fatigue life.Moisture that reaches the filling resin between the chip and board due to the moisture absorption of the board is vaporized by heat when mounted on the motherboard. There is a problem that cracking of the resin occurs when this occurs.
【００１４】本発明は上記の問題点を解決すべくなされ
たもので、チップと樹脂系配線基板の熱膨脹係数が異な
っても熱応力によるパッケージの反りを低減でき、マザ
ーボードへの半導体装置の実装が容易になり、チップ・
基板間の半田接合部、基板・マザーボード間の半田接合
部の歪みが発生せず、基板の吸湿性に起因してチップ・
基板間の充填樹脂まで達した水分がマザーボードへの実
装時の熱により気化した時でも樹脂のひび割れが生じな
くなり、パッケージの信頼性の向上を図り得る片面樹脂
封止型パッケージ構造を有する半導体装置およびその製
造方法を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can reduce the warpage of a package due to thermal stress even when the thermal expansion coefficients of a chip and a resin-based wiring board are different, so that a semiconductor device can be mounted on a motherboard. Easier, tip
Distortion does not occur in the solder joint between the boards and the solder joint between the board and the motherboard.
A semiconductor device having a single-sided resin-encapsulated package structure capable of preventing cracking of the resin even when moisture reaching the filling resin between the substrates is vaporized by heat during mounting on the motherboard and improving package reliability; and It is an object of the present invention to provide a manufacturing method thereof.
【００１５】[0015]
【課題を解決するための手段】本発明の半導体装置は、
チップ搭載面に被接続部を含む配線パターンおよび前記
配線パターンを避けた位置でチップ外側端に連なる溝を
有する配線基板と、素子形成面に外部接続端子群を有
し、前記素子形成面が前記配線基板のチップ搭載面にフ
ェースダウン型に実装され、前記外部接続端子群が前記
被接続部と電気的に接続された半導体チップと、前記半
導体チップと配線基板との間を充填すると共に前記半導
体チップの各外周側面を覆うように封止する樹脂と、前
記配線基板のチップ非搭載面に形成され、前記配線パタ
ーンに電気的に接続された外部接続用端子とを具備し、
前記溝は、その内面が前記樹脂に対する剥離性を有する
ことを特徴とする。According to the present invention, there is provided a semiconductor device comprising:
A wiring board having a wiring pattern including a portion to be connected on a chip mounting surface and a groove connected to an outer end of the chip at a position avoiding the wiring pattern, and an external connection terminal group on an element formation surface, wherein the element formation surface is A semiconductor chip mounted face-down on a chip mounting surface of a wiring board, wherein the external connection terminal group is electrically connected to the portion to be connected; and the semiconductor chip is filled between the semiconductor chip and the wiring board. A resin for sealing to cover each outer peripheral side surface of the chip, and an external connection terminal formed on the chip non-mounting surface of the wiring board and electrically connected to the wiring pattern,
The inner surface of the groove has a releasability from the resin.
【００１６】また、本発明の半導体装置の製造方法は、
チップ搭載面に被接続部を含む配線パターンが形成さ
れ、チップ搭載面の前記配線パターンを避ける位置でチ
ップ外側端に連なるとともに内面が樹脂に対する剥離性
を持つ溝が形成され、前記チップ搭載面の配線パターン
とチップの他主面との間に配線経路が形成された配線基
板を製造する工程と、前記配線基板の被接続部に対応す
る位置で素子形成面に外部接続用電極端子部を有する半
導体チップを製造する工程と、前記半導体チップをその
電極端子部の位置が前記被接続部に対向するように前記
配線基板上に配置し、前記半導体チップの電極端子部と
配線基板の被接続部とを固定接続する工程と、この後、
前記半導体チップと配線基板との間を充填すると共に前
記半導体チップの各外周側面を覆うように封止用の樹脂
を形成する工程と、前記配線基板の他主面側に前記配線
経路に連なる外部接続用端子を形成する工程とを具備す
ることを特徴とする。Further, a method of manufacturing a semiconductor device according to the present invention
A wiring pattern including a portion to be connected is formed on the chip mounting surface, a groove continuous with the chip outer end is formed at a position avoiding the wiring pattern on the chip mounting surface, and a groove having a releasable property with respect to resin is formed on the chip mounting surface. A step of manufacturing a wiring board in which a wiring path is formed between the wiring pattern and the other main surface of the chip; and having an external connection electrode terminal portion on the element forming surface at a position corresponding to a connected portion of the wiring substrate. Manufacturing a semiconductor chip, arranging the semiconductor chip on the wiring substrate such that the position of the electrode terminal portion faces the connected portion, and connecting the electrode terminal portion of the semiconductor chip to the connected portion of the wiring substrate. And the step of fixedly connecting
Forming a sealing resin so as to fill the space between the semiconductor chip and the wiring board and to cover each outer peripheral side surface of the semiconductor chip; Forming a connection terminal.
【００１７】[0017]
【発明の実施の形態】以下、図面を参照して本発明の実
施の形態を詳細に説明する。図１は、ＢＧＡパッケージ
構造を有する半導体装置の一例を概略的に示す斜視図で
ある。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a perspective view schematically showing an example of a semiconductor device having a BGA package structure.
【００１８】図２は、図１の半導体装置に本発明の第１
の実施の形態を適用した場合に図１中のＢ−Ｂ線に沿っ
て概略的に示す断面図である。図３は、図２中の配線基
板を取り出して一例を示す斜視図である。FIG. 2 shows the semiconductor device of FIG.
FIG. 2 is a cross-sectional view schematically showing the embodiment of FIG. 1 along line BB in FIG. 1. FIG. 3 is a perspective view showing an example of the wiring board in FIG. 2 taken out.
【００１９】図１乃至図３に示す半導体装置は、チップ
搭載面に被接続部を含む配線パターン１３および前記配
線パターン１３を避けた位置でチップ外側端に連なる溝
２０を有する配線基板２１と、素子形成面に外部接続端
子群（例えば金属バンプ電極群）を有し、前記素子形成
面が前記配線基板２１のチップ搭載面にフェースダウン
型に実装され、前記外部接続端子群が前記被接続部と電
気的に接続された方形の半導体チップ１０と、前記半導
体チップ１０と配線基板２１との間を充填すると共に前
記半導体チップ１０の各外周側面を覆うように封止した
樹脂１６と、前記配線基板２１のチップ非搭載面（本例
では、チップ下面）に形成され、前記配線パターン１３
に電気的に接続された外部接続用端子２２とを具備す
る。The semiconductor device shown in FIGS. 1 to 3 has a wiring board 21 having a wiring pattern 13 including a portion to be connected on a chip mounting surface and a groove 20 continuous with the outer end of the chip at a position avoiding the wiring pattern 13. An external connection terminal group (for example, a group of metal bump electrodes) is provided on the element formation surface, the element formation surface is mounted face-down on the chip mounting surface of the wiring board 21, and the external connection terminal group is connected to the connected portion. A semiconductor chip 10 electrically connected to the semiconductor chip 10, a resin 16 filled between the semiconductor chip 10 and the wiring board 21 and sealed so as to cover each outer peripheral side surface of the semiconductor chip 10, The wiring pattern 13 is formed on the chip non-mounting surface of the substrate 21 (in this example, the chip lower surface).
And an external connection terminal 22 electrically connected to the terminal.
【００２０】なお、前記配線基板２１のサイズは、縦・
横がチップ１０のサイズより１〜２ｍｍ程度大きく、厚
さが５００μｍ〜１ｍｍである。本例では、前記溝２０
は、配線基板２１のチップ搭載面の対角線上に２本形成
され、前記２本の溝２０はチップ搭載面の中央部で交差
しており、溝２０のサイズは、幅が１〜２ｍｍ、深さが
５０〜１００μｍである。The size of the wiring board 21 is
The width is about 1 to 2 mm larger than the size of the chip 10 and the thickness is 500 μm to 1 mm. In this example, the groove 20
Are formed on the diagonal line of the chip mounting surface of the wiring board 21, and the two grooves 20 intersect at the center of the chip mounting surface. The size of the groove 20 is 1 to 2 mm wide and deep. Is 50 to 100 μm.
【００２１】そして、溝２０の内面は、前記樹脂１６に
対する剥離性を有するように処理されている。この処理
としては、溝２０の内面にワックスなどの剥離剤２０ａ
を塗布しておくことにより樹脂１６に対する剥離性を持
たせることが可能であり、あるいは、溝２０の内面にＣ
ｕ膜をコーティングしておけば、その表面に存在する酸
化膜により樹脂１６の層に対する剥離性を持たせること
が可能である。The inner surface of the groove 20 is treated so as to have releasability from the resin 16. As this treatment, a release agent 20a such as wax is applied to the inner surface of the groove 20.
Can be imparted to the resin 16 by applying a coating on the inner surface of the groove 20.
If the u film is coated, it is possible to give the resin 16 a releasability from the layer of the resin 16 by the oxide film present on the surface thereof.
【００２２】なお、本例では、配線基板２１として、外
部接続用端子２２がスルーホール配線１３ｂ、あるいは
層間配線パターン１３ａとブラインドビアホール配線
（図示せず）を介して配線パターン１３に接続されてい
る多層構造のものが用いられており、前記端子２２は配
線基板２１に垂直方向なバンプ状に形成されている。In this embodiment, as the wiring board 21, the external connection terminal 22 is connected to the wiring pattern 13 through the through-hole wiring 13b or the interlayer wiring pattern 13a and the blind via-hole wiring (not shown). A terminal having a multilayer structure is used, and the terminal 22 is formed in a bump shape perpendicular to the wiring board 21.
【００２３】また、配線基板２１は、配線パターン１３
が配線基板面から突出する状態で形成されているものも
のに限らず、配線パターン１３が配線基板面とほぼ同一
平面を成すように埋め込まれているものを用いてもよ
い。The wiring board 21 is provided with a wiring pattern 13.
Is not limited to those formed so as to protrude from the wiring board surface, but may be used in which the wiring pattern 13 is embedded so as to be substantially flush with the wiring board surface.
【００２４】また、半導体チップ１０の素子形成面の金
属バンプ電極１２群（例えば半田バンプ群）を配線基板
２１のチップ搭載面にフェースダウン型に実装する際に
は、予め配線基板２１のチップ搭載面上で配線パターン
１３の被接続部以外の領域にソルダーレジストなどの絶
縁性保護膜を塗布しておくことが望ましい。When the metal bump electrodes 12 (for example, solder bumps) on the element forming surface of the semiconductor chip 10 are mounted face-down on the chip mounting surface of the wiring board 21, the chip mounting of the wiring board 21 is performed in advance. It is desirable that an insulating protective film such as a solder resist be applied to a region other than the connected portion of the wiring pattern 13 on the surface.
【００２５】また、前記封止樹脂１６の形成に際して
は、例えば樹脂供給装置（図示せず）のノズルから液状
の樹脂を基板２１上に供給し、樹脂の表面張力と毛細管
現象を利用してチップ・基板間に樹脂を流し込んで充填
した後に硬化させている。When the sealing resin 16 is formed, a liquid resin is supplied onto the substrate 21 from, for example, a nozzle of a resin supply device (not shown), and a chip is formed by utilizing the surface tension of the resin and the capillary phenomenon. -It is cured after pouring and filling the resin between the substrates.
【００２６】なお、前記チップ１０の露出上面は、緻
密、堅牢な素材（例えばシリコン）からなり、樹脂封止
を行わなくても信頼性上の問題は少ない。次に、図４
（ａ）乃至（ｃ）を参照しながら、図１乃至図３に示し
た半導体装置の製造工程の一例を簡単に説明する。The exposed upper surface of the chip 10 is made of a dense and robust material (for example, silicon), so that there is little reliability problem without resin sealing. Next, FIG.
An example of a manufacturing process of the semiconductor device shown in FIGS. 1 to 3 will be briefly described with reference to FIGS.
【００２７】まず、図４（ａ）に示すように、配線基板
２１として、チップ搭載面に被接続部を含む配線パター
ン１３が絶縁基材面から少し突出するように形成され、
この配線パターン１３を避ける位置でチップ外側端に連
なる溝２０が形成され、溝２０の内面に剥離剤２０ａが
塗布され、前記被接続部とチップ非搭載面（本例では下
面）との間に配線経路（例えば前記したようなスルーホ
ール配線１３ｂ、あるいは層間配線パターン１３ａとブ
ラインドビアホール配線）が形成されたものを用意す
る。First, as shown in FIG. 4A, a wiring pattern 13 including a portion to be connected is formed on the chip mounting surface as a wiring substrate 21 so as to slightly protrude from the insulating base material surface.
A groove 20 is formed at a position avoiding the wiring pattern 13 so as to be continuous with the outer end of the chip, a release agent 20a is applied to the inner surface of the groove 20, and a gap is formed between the connected portion and the chip non-mounting surface (the lower surface in this example). A wiring path (for example, the through-hole wiring 13b or the interlayer wiring pattern 13a and the blind via-hole wiring as described above) is prepared.
【００２８】一方、半導体チップ１０として、素子形成
面上における前記配線基板２１の被接続部に対応する位
置に外部接続用端子部としてパッドに導電性物質（例え
ば半田からなるバンプ電極１２（インナーリード）が形
成されているものを用意する。On the other hand, as a semiconductor chip 10, a conductive material (for example, a bump electrode 12 (inner lead made of solder) is applied to a pad as a terminal for external connection at a position corresponding to a connected portion of the wiring board 21 on the element forming surface. ) Is prepared.
【００２９】なお、前記基板２１のチップ搭載面に被接
続部を形成する際には、チップ搭載面に配線パターン１
３を有する基板２１を例えば真空吸着機構付きのスクリ
ーン印刷機のステージ上に固定し、基板２１上でチップ
１０のバンプ電極１２に対応する部分に例えば平面型の
接続パッドを形成する。When forming a connected portion on the chip mounting surface of the substrate 21, the wiring pattern 1 is formed on the chip mounting surface.
For example, the substrate 21 having the substrate 3 is fixed on a stage of a screen printing machine having a vacuum suction mechanism, and, for example, a planar connection pad is formed on a portion of the substrate 10 corresponding to the bump electrode 12.
【００３０】この際、チップ１０のバンプ電極１２に対
応する開口を有するメタルマスクを用いて基板２１の配
線形成面上に導電性ペースト、例えば銀ペーストをスク
リーン印刷して前記接続パッドを形成する。At this time, using a metal mask having openings corresponding to the bump electrodes 12 of the chip 10, a conductive paste, for example, silver paste is screen-printed on the wiring forming surface of the substrate 21 to form the connection pads.
【００３１】次に、チップ１０を真空吸着し得る機構を
有するボンディング装置を用いて基板２１上にチップ１
０をフェースダウン型に実装するためにフリップチップ
ボンディング（インナーリードボンディング）を行う。
即ち、図４（ｂ）に示すように、チップ１０の外部接続
用の電極端子部１２の位置が基板２１の被接続部に対向
するように、チップ１０を基板上に配置し、チップ１０
の電極端子部１２と基板２１の被接続部とを固定接続す
る。次に、チップ・基板間に樹脂１６を充填させるとと
もにチップの各外周側面部を樹脂で覆うように樹脂１６
で封止する。Next, the chip 1 is placed on the substrate 21 by using a bonding apparatus having a mechanism capable of vacuum-sucking the chip 10.
Flip chip bonding (inner lead bonding) is performed in order to mount 0 in a face-down type.
That is, as shown in FIG. 4B, the chip 10 is arranged on the substrate 10 such that the position of the electrode terminal portion 12 for external connection of the chip 10 faces the connected portion of the substrate 21.
Is fixedly connected to the electrode terminal portion 12 of the substrate 21 and the connected portion of the substrate 21. Next, the resin 16 is filled between the chip and the substrate, and the resin 16 is coated so as to cover each outer peripheral side surface of the chip with the resin.
Seal with.
【００３２】次に、図４（ｃ）に示すように、基板２１
のチップ非搭載面（本例では下面）に前記配線経路に連
なるように外部接続用端子２２（アウターリード）とし
て例えば半田バンプを形成する。Next, as shown in FIG.
For example, solder bumps are formed as external connection terminals 22 (outer leads) on the chip non-mounting surface (the lower surface in this example) so as to be continuous with the wiring path.
【００３３】図１乃至図３に示したようなパッケージ構
造を有する半導体装置の使用に際して、図５に示すよう
に応用製品のマザーボード５０上の配線に基板２１を例
えば半田付けにより実装（アウターリードボンディン
グ）する。この場合、基板２１は、チップ１０とマザー
ボード５０とのピッチ変換の役割を持つインターポーザ
として機能する。When using the semiconductor device having the package structure as shown in FIGS. 1 to 3, the substrate 21 is mounted on the wiring on the motherboard 50 of the application product by, for example, soldering (outer lead bonding) as shown in FIG. ). In this case, the substrate 21 functions as an interposer having a role of converting the pitch between the chip 10 and the motherboard 50.
【００３４】即ち、図１乃至図３に示した半導体装置に
よれば、配線基板２１のチップ搭載面に形成された溝２
０の内面が樹脂１６に対する剥離性を有するように処理
されており、チップ１０と基板１１の熱膨脹係数が異な
ることに起因して熱などにより生じた応力による配線基
板２１の反りが生じても溝２０の部分で樹脂１６が剥離
するので、パッケージの反りが低減し、マザーボード５
０への半導体装置の実装が容易になり、実装状態におけ
るチップ１０・基板１１間の半田接合部、基板２１・マ
ザーボード５０間の半田接合部での破断不良が防止さ
れ、半導体装置の信頼性が向上する。That is, according to the semiconductor device shown in FIGS. 1 to 3, the groove 2 formed on the chip mounting surface of the wiring board 21 is formed.
0 is treated so as to have releasability from the resin 16, and the groove is formed even if the wiring board 21 warps due to stress caused by heat or the like due to the difference in the thermal expansion coefficient between the chip 10 and the substrate 11. Since the resin 16 is peeled off at the portion 20, the warpage of the package is reduced, and the motherboard 5 is removed.
0 is easy to mount the semiconductor device on the chip 10, the solder joint between the chip 10 and the board 11 and the solder joint between the board 21 and the motherboard 50 in the mounted state are prevented from breaking failure, and the reliability of the semiconductor device is improved. improves.
【００３５】また、樹脂系の配線基板２１の保管中にお
ける吸湿によりチップ・基板間の充填樹脂１６まで達し
た水分がマザーボード５０への半導体装置の実装時の熱
により気化したとしても、それは基板２１のチップ搭載
面の溝２０（樹脂剥離部分）に沿って配線基板２１のチ
ップ外側端から放出されるので、パッケージにひび割れ
（クラック）が生じるおそれがなくなり、半導体装置の
信頼性が向上する。Further, even if the moisture that has reached the filling resin 16 between the chip and the substrate due to moisture absorption during storage of the resin-based wiring board 21 is vaporized by the heat at the time of mounting the semiconductor device on the motherboard 50, it is not changed. Is released from the chip outer end of the wiring board 21 along the groove 20 (resin peeling portion) of the chip mounting surface, so that there is no possibility that a crack is generated in the package, and the reliability of the semiconductor device is improved.
【００３６】なお、上記実施例では、配線基板２１のチ
ップ搭載面の溝２０は、方形のチップ搭載面の中央部で
交差するようにチップ搭載面の対角線上に２本形成され
ているが、図６に示すように、さらに２本の溝２０の交
差部に例えば円形の皿状の溝２０ｂを形成しても、本発
明の効果が得られる。In the above embodiment, two grooves 20 on the chip mounting surface of the wiring board 21 are formed on the diagonal line of the chip mounting surface so as to intersect at the center of the rectangular chip mounting surface. As shown in FIG. 6, the effect of the present invention can be obtained even if a circular dish-shaped groove 20b is formed at the intersection of two grooves 20.
【００３７】また、前記中央部の溝２０ｂに代えてチッ
プ貫通孔を形成すれば、樹脂封止に際してチップの裏面
から上記チップ貫通孔を通して素子形成面（基板対向
面）側に樹脂を注入することが可能になる。If a chip through hole is formed instead of the central groove 20b, resin is injected from the back surface of the chip to the element forming surface (substrate facing surface) through the chip through hole during resin sealing. Becomes possible.
【００３８】[0038]
【発明の効果】上述したように本発明によれば、チップ
と樹脂系配線基板の熱膨脹係数が異なっても熱応力によ
るパッケージの反りを低減でき、マザーボードへの半導
体装置の実装が容易になり、チップ・基板間の半田接合
部、基板・マザーボード間の半田接合部の歪みが発生せ
ず、基板の吸湿性に起因してチップ・基板間の充填樹脂
まで達した水分がマザーボードへの実装時の熱により気
化した時でも樹脂のひび割れが生じなくなり、パッケー
ジの信頼性の向上を図り得る片面樹脂封止型パッケージ
構造を有する半導体装置およびその製造方法を提供する
ことができる。As described above, according to the present invention, even if the chip and the resin-based wiring board have different coefficients of thermal expansion, the warpage of the package due to thermal stress can be reduced, and the semiconductor device can be easily mounted on the motherboard. Distortion of the solder joint between the chip and the board and the solder joint between the board and the motherboard do not occur, and the moisture that has reached the filling resin between the chip and the board due to the moisture absorption of the board causes It is possible to provide a semiconductor device having a single-sided resin-encapsulated package structure capable of preventing the resin from cracking even when vaporized by heat and improving the reliability of the package, and a method for manufacturing the same.
【図１】 ＢＧＡパッケージ構造を有する半導体装置の
一例を概略的に示す斜視図。FIG. 1 is a perspective view schematically showing an example of a semiconductor device having a BGA package structure.
【図２】 図１の半導体装置に本発明の第１の実施の形
態を適用した場合に図１中のＢ−Ｂ線に沿って概略的に
示す断面図。FIG. 2 is a sectional view schematically showing the semiconductor device of FIG. 1 according to the first embodiment of the present invention, taken along line BB in FIG. 1;
【図３】 図２中の配線基板を取り出して一例を示す斜
視図。FIG. 3 is an exemplary perspective view illustrating an example of a circuit board taken out of FIG. 2;
【図４】 図１乃至図３に示した半導体装置の製造工程
の一例を説明するために示す図。FIG. 4 is a diagram illustrating an example of a manufacturing process of the semiconductor device illustrated in FIGS. 1 to 3;
【図５】 図１乃至図３に示した半導体装置を応用製品
のマザーボード上に半田付けにより実装した状態を示す
図。FIG. 5 is a diagram showing a state where the semiconductor device shown in FIGS. 1 to 3 is mounted on a motherboard of an application product by soldering.
【図６】 図３の配線基板の変形例を示す斜視図。FIG. 6 is an exemplary perspective view showing a modification of the wiring board of FIG. 3;
【図７】 従来のＢＧＡパッケージ構造を有する半導体
装置の構造の一例を概略的に示す断面図。FIG. 7 is a sectional view schematically showing an example of the structure of a semiconductor device having a conventional BGA package structure.
【図８】 図７中の半導体装置において配線基板として
ミック系の材料を用いた場合にパッケージが反る様子お
よびマザーボードへの半導体装置の実装時の熱により樹
脂にひび割れが生じる様子を示す図。FIG. 8 is a diagram showing a state in which a package warps when a wiring substrate is made of a material of the Mic type in the semiconductor device in FIG. 7 and a state in which a resin cracks due to heat when the semiconductor device is mounted on a motherboard;
１０…半導体チップ、 １２…チップの外部接続端子（バンプ電極）、 １３…配線パターン、 １３ａ…層間配線パターン、 １３ｂ…スルーホール配線、 １６…封止樹脂、 ２０…溝、 ２０ａ…剥離剤、 ２１…配線基板、 ２２…基板の外部接続端子（バンプ電極）。 Reference Signs List 10: semiconductor chip, 12: external connection terminal (bump electrode) of chip, 13: wiring pattern, 13a: interlayer wiring pattern, 13b: through-hole wiring, 16: sealing resin, 20: groove, 20a: release agent, 21 ... wiring board, 22 ... external connection terminal (bump electrode) of the board.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 23/12 Ｌ ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 23/12 L
Claims (5)
ーンおよび前記配線パターンを避けた位置でチップ外側
端に連なる溝を有する配線基板と、 素子形成面に外部接続端子群を有し、前記素子形成面が
前記配線基板のチップ搭載面にフェースダウン型に実装
され、前記外部接続端子群が前記被接続部と電気的に接
続された半導体チップと、 前記半導体チップと配線基板との間を充填すると共に前
記半導体チップの少なくとも各外周側面を覆うように封
止する樹脂と、 前記配線基板のチップ非搭載面に形成され、前記配線パ
ターンに電気的に接続された外部接続用端子とを具備
し、 前記溝の内面は、前記樹脂に対する剥離性を有すること
を特徴とする半導体装置。1. A wiring board having a wiring pattern including a portion to be connected on a chip mounting surface and a groove connected to an outer end of the chip at a position avoiding the wiring pattern, and an external connection terminal group on an element forming surface, A semiconductor chip in which an element forming surface is mounted face-down on a chip mounting surface of the wiring substrate, and the external connection terminal group is electrically connected to the connected portion; A resin that is filled and sealed so as to cover at least each outer peripheral surface of the semiconductor chip; and an external connection terminal formed on the chip non-mounting surface of the wiring board and electrically connected to the wiring pattern. A semiconductor device, wherein an inner surface of the groove has releasability from the resin.
れ、前記２本の溝はチップ搭載面の中央部で交差してい
ることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein two of said grooves are formed on a diagonal line of a rectangular chip mounting surface, and said two grooves intersect at a central portion of said chip mounting surface. A semiconductor device characterized by the above-mentioned.
いて、 前記溝は、内面にＣｕ膜がコーティングされていること
を特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the groove has an inner surface coated with a Cu film.
いて、 前記溝は、内面に剥離剤が塗布されていることを特徴と
する半導体装置。4. The semiconductor device according to claim 1, wherein the groove has an inner surface coated with a release agent.
ーンが形成され、チップ搭載面の前記配線パターンを避
ける位置でチップ外側端に連なるとともに内面が樹脂に
対する剥離性を持つ溝が形成され、前記チップ搭載面の
配線パターンとチップの他主面との間に配線経路が形成
された配線基板を製造する工程と、 前記配線基板の被接続部に対応する位置で素子形成面に
外部接続用電極端子部を有する半導体チップを製造する
工程と、 前記半導体チップをその電極端子部の位置が前記被接続
部に対向するように前記配線基板上に配置し、前記半導
体チップの電極端子部と配線基板の被接続部とを固定接
続する工程と、 この後、前記半導体チップと配線基板との間を充填する
と共に前記半導体チップの各外周側面を覆うように封止
用の樹脂を形成する工程と、 前記配線基板の他主面側に前記配線経路に連なる外部接
続用端子を形成する工程とを具備することを特徴とする
半導体装置の製造方法。5. A wiring pattern including a portion to be connected is formed on the chip mounting surface, and a groove is formed at the position avoiding the wiring pattern on the chip mounting surface, the groove being connected to an outer end of the chip and having an inner surface peelable from resin. A step of manufacturing a wiring board in which a wiring path is formed between a wiring pattern on the chip mounting surface and the other main surface of the chip; and an external connection to an element formation surface at a position corresponding to a connected portion of the wiring board. A step of manufacturing a semiconductor chip having an electrode terminal portion, arranging the semiconductor chip on the wiring board such that the position of the electrode terminal portion faces the connected portion, and wiring the semiconductor chip with the electrode terminal portion of the semiconductor chip. A step of fixedly connecting the connected portion of the substrate to a connecting portion; and thereafter, a resin for sealing is formed so as to fill the space between the semiconductor chip and the wiring board and cover each outer peripheral side surface of the semiconductor chip. And a step of forming an external connection terminal connected to the wiring path on the other main surface side of the wiring substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1266597A JPH10233463A (en) | 1997-01-27 | 1997-01-27 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1266597A JPH10233463A (en) | 1997-01-27 | 1997-01-27 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10233463A true JPH10233463A (en) | 1998-09-02 |
Family
ID=11811673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1266597A Pending JPH10233463A (en) | 1997-01-27 | 1997-01-27 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10233463A (en) |
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| US6469373B2 (en) | 2000-05-15 | 2002-10-22 | Kabushiki Kaisha Toshiba | Semiconductor apparatus with improved thermal and mechanical characteristic under-fill layer and manufacturing method therefor |
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- 1997-01-27 JP JP1266597A patent/JPH10233463A/en active Pending
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