JPH02309643A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02309643A JPH02309643A JP1130841A JP13084189A JPH02309643A JP H02309643 A JPH02309643 A JP H02309643A JP 1130841 A JP1130841 A JP 1130841A JP 13084189 A JP13084189 A JP 13084189A JP H02309643 A JPH02309643 A JP H02309643A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- electrode
- bump
- packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004020 conductor Substances 0.000 claims description 8
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 abstract description 5
- 238000004806 packaging method and process Methods 0.000 abstract 4
- 239000010408 film Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor device.
従来の技術
従来の半導体装置は、第２図ａ、ｂに示す様に、回路導
体層１５および電極１ｅを形成した基板１４に、電極１
２の上に直方体のバンプ１３を有する半導体チップ１１
を、接着剤１７を介して、バンプ１３と電極１６が当接
する様に加圧し、接着剤１７を硬化させ固定していた。2. Description of the Related Art As shown in FIGS. 2a and 2b, a conventional semiconductor device has an electrode 1 on a substrate 14 on which a circuit conductor layer 15 and an electrode 1e are formed.
Semiconductor chip 11 having a rectangular parallelepiped bump 13 on 2
The bumps 13 and the electrodes 16 were pressed through the adhesive 17 so that they came into contact with each other, and the adhesive 17 was cured and fixed.
発明が解決しようとする課題
しかしながら、この様な半導体装置では、基板１４上の
電極１６と半導体テラ、プ１１上のバンプ１３を当接す
る時に、扁い圧力値で加圧する必要がある。このため、
基板１４および半導体チップ１１がそりや歪み等の変形
を生じたまま接着剤１７で固定されることとなシ、半導
体チップ１１自体や、半導体チップ１１と基板１４間の
接続の信頼性が低く、歩留等が悪かった。Problems to be Solved by the Invention However, in such a semiconductor device, when the electrode 16 on the substrate 14 and the bump 13 on the semiconductor plate 11 are brought into contact with each other, it is necessary to apply pressure with a flat pressure value. For this reason,
If the substrate 14 and the semiconductor chip 11 are fixed with the adhesive 17 while being deformed such as warpage or distortion, the reliability of the semiconductor chip 11 itself and the connection between the semiconductor chip 11 and the substrate 14 will be low. Yield etc. were poor.
課題を解決するための手段
上記課題を解決するために、本発明の半導体装置は、半
導体チップ上のバンプの基板側の面を、環状または断続
的な環状の突部を設けたものである。Means for Solving the Problems In order to solve the above-mentioned problems, a semiconductor device of the present invention is provided with an annular or intermittent annular protrusion on the substrate side surface of a bump on a semiconductor chip.
作用
上記本発明によれば、半導体チップのバンプの基板の電
極への当接部の面積が減少するので、実装置の加圧値が
低くて実装が可能となり、したがって半導体チップ及び
基板等に無理な力が加わることがなく、実装の信頼性が
向上し、歩留も上がる。Effects According to the present invention, since the area of the contact portion of the bump of the semiconductor chip to the electrode of the substrate is reduced, it is possible to mount the actual device with a low pressure value, and therefore there is no stress on the semiconductor chip and the substrate. No force is applied, improving mounting reliability and increasing yield.
実施例
以下、本発明の一実施例を図面を用いて説明する。第１
図ａＮＣは、本発明の一実施例における半導体装置を示
すものである。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
Figure aNC shows a semiconductor device in one embodiment of the present invention.
１は半導体チップ、２は半導体チップ１０表面に形成さ
れたアルミニウムよりなる第２の電極、３は第２の電極
２の上に形成された金製バンプである。４は半導体チッ
プ１を実装する基板、６は基板４上に形成した回路導体
層、６は基板４上に形成され、しかも回路導体層５と接
続された第１の電極、７は半導体チップ１と基板４との
間に塗布され、これらを圧着固定するだめの接着剤、８
は半導体チップ１の表面に形成された保護膜である。1 is a semiconductor chip, 2 is a second electrode made of aluminum formed on the surface of the semiconductor chip 10, and 3 is a gold bump formed on the second electrode 2. 4 is a substrate on which the semiconductor chip 1 is mounted; 6 is a circuit conductor layer formed on the substrate 4; 6 is a first electrode formed on the substrate 4 and connected to the circuit conductor layer 5; 7 is the semiconductor chip 1; and the substrate 4, and an adhesive 8 for crimping and fixing them;
is a protective film formed on the surface of the semiconductor chip 1.
以上のように構造される半導体装置の製造方法について
説明する。A method of manufacturing a semiconductor device structured as described above will be described.
先ず半導体プロセスを用いて単結晶シリコン基板（ウェ
ハ）上に、各種素子を形成しく図示せず）、次に百数十
μｍ角の第２の電極２を形成する。次に単結晶シリコン
基板上を、第２の電極２の周囲を数〜十数μｍかぶさる
ように第２の電極２以外の全面を保護膜８である厚さ約
１μｍの窒化膜でおおい、半導体素子を保護する。次に
電気メツキ法等により、第２の電極２上に金を数μｍの
厚さで形成し、バンプ３を作る。この時、第２の電極２
上で、保護膜８がおおわれている部分の上にも金が形成
されるため、バンプ３の周囲幅数〜十数μｍの部分が約
１μｍ程度環状に突出する形状となる。その後この単結
晶シリコン基板を高精度ダイシング技術により切断し、
半導体チップ１を作る。また、ガラスまたはアルミナ等
の基板４上に、ムＵやムｇ−Ｐｔ等の貴金属をスクリー
ン印刷法または薄膜形成法とフォ） ＩＪソ法を用いて
回路導体層６及び第１の電極６を形成する。この基板４
の所定の位置にアクＩＪ ）し系の光硬化型絶縁樹脂で
ある接着剤７をスクリーン印刷やディスペンサ等で所定
量を塗布し、その上に先の半導体チップ１をバンプ３側
を下方にして配置する。その後この半導体チップ１に上
方から所定の圧力を加え、半導体チップ１上のすべての
バンプ３が、基板４上の対応する第１の電極６に当接す
るようにさせる。First, various elements are formed on a single crystal silicon substrate (wafer) using a semiconductor process (not shown), and then a second electrode 2 of more than 100 μm square is formed. Next, the entire surface of the single crystal silicon substrate other than the second electrode 2 is covered with a nitride film having a thickness of approximately 1 μm as a protective film 8 so as to cover the circumference of the second electrode 2 by several to tens of μm. Protect the element. Next, by electroplating or the like, gold is formed on the second electrode 2 to a thickness of several micrometers to form the bumps 3. At this time, the second electrode 2
Since gold is also formed on the portion covered by the protective film 8, the portion of the bump 3 having a peripheral width of several to several tens of μm protrudes in an annular shape by about 1 μm. This single-crystal silicon substrate is then cut using high-precision dicing technology.
Make semiconductor chip 1. In addition, a circuit conductor layer 6 and the first electrode 6 are formed on a substrate 4 made of glass or alumina using a screen printing method or a thin film forming method or an IJ method using a noble metal such as MuU or Mug-Pt. Form. This board 4
Apply a predetermined amount of adhesive 7, which is a photocurable insulating resin based on Acrylic IJ, to a predetermined position using screen printing or a dispenser, and then place the previous semiconductor chip 1 on top of it with the bump 3 side facing downward. Deploy. Thereafter, a predetermined pressure is applied to this semiconductor chip 1 from above so that all the bumps 3 on the semiconductor chip 1 come into contact with the corresponding first electrodes 6 on the substrate 4.
この時、バンプ３や第１の電極６の高さのばらつき、及
び半導体チップ１や基板４のそりなどを吸収するため、
バンプ３の先端の環状の突出部がつぶされる状態となる
。次に外部より、回路導体層６を介して電圧を加え、半
導体チップ１が正常に動作するのを確認したのち、基板
４がガラスであればそのガラスを透して、又アルミナで
あればすき間より紫外線照射をし、光硬化型絶縁樹脂７
を硬化し、実装を完了する。この様に、バンプ３を、そ
の先端の周囲が特に環状に突出している形状にすること
により、バンプ３の表面積を大きくして、半導体チップ
１と基板４の位置合せを容易にし、しかも、実装時にバ
ンプ３のつぶれる面積を小さくして実装時の加圧値を低
くすることにより、半導体チップ１や基板４に無理な力
が加わることを解消し、半導体チップ１や基板４の破壊
をなくし、又実装の信頼性を向上させることができ、歩
留を上げることが実現できた。At this time, in order to absorb variations in the heights of the bumps 3 and the first electrodes 6 and warpage of the semiconductor chip 1 and the substrate 4,
The annular protrusion at the tip of the bump 3 becomes crushed. Next, voltage is applied from the outside via the circuit conductor layer 6, and after confirming that the semiconductor chip 1 operates normally, the voltage is applied through the glass if the substrate 4 is glass, or through the gap if it is alumina. Light-curable insulation resin 7 is irradiated with ultraviolet light.
harden and complete the mounting. In this way, by forming the bump 3 into a shape in which the periphery of the tip protrudes in a particularly annular shape, the surface area of the bump 3 is increased, and alignment of the semiconductor chip 1 and the substrate 4 is facilitated. By reducing the crushing area of the bumps 3 and lowering the pressure applied during mounting, it is possible to eliminate excessive force from being applied to the semiconductor chip 1 and the substrate 4, thereby eliminating damage to the semiconductor chip 1 and the substrate 4. Furthermore, it was possible to improve the reliability of mounting and increase the yield.
発明の効果
以上の様に、本発明によれば、信頼性及び歩留の高い半
導体装置を実現することができる。Effects of the Invention As described above, according to the present invention, a semiconductor device with high reliability and high yield can be realized.
第１図ａは本発明の一実施例の実装前の半導体チップの
上面図、第１図すは実装後の側断面図、第１図Ｃは実装
時の正面図、第２図ａ、ｂは各々従来例の実装前、後の
側断面図である。
１・・・・・・半導体チップ、２・・・・・・第２の電
極、３・・・・・・バンプ、４・・・・・・基板、５・
・・・・・回路導体層、６・・・・・第１の電極、７・
・・・・・接着剤、８・・・・・・保護膜。
代理人の氏名 弁理士 粟 野 重 孝 ほか１名（ｂ
）
第２図
（良）
（ト）FIG. 1a is a top view of a semiconductor chip before mounting according to an embodiment of the present invention, FIG. 1 is a side sectional view after mounting, FIG. 1C is a front view when mounted, and FIGS. 2a and b 2A and 2B are side sectional views of the conventional example before and after mounting, respectively. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Second electrode, 3... Bump, 4... Substrate, 5...
...Circuit conductor layer, 6...First electrode, 7.
...Adhesive, 8...Protective film. Name of agent: Patent attorney Shigetaka Awano and one other person (b
) Figure 2 (Good) (G)
Claims (1)
接続された第一の電極を有する基板と、この基板の前記
第一の電極部に、接着剤を介して固定された半導体チッ
プとを備え、上記半導体チップは、その上記基板側の面
に第二の電極を有し、この第二の電極の上記第一の電極
側には、上記第一の電極に当接するバンプを形成し、こ
のバンプは、その第一の電極への当接面側に、環状また
は断続的な環状の突部を形成した半導体装置。A substrate having a circuit conductor layer and a first electrode connected to the circuit conductor layer on at least one side, and a semiconductor chip fixed to the first electrode portion of the substrate via an adhesive, The semiconductor chip has a second electrode on the surface of the substrate, and a bump that contacts the first electrode is formed on the first electrode side of the second electrode. is a semiconductor device in which an annular or intermittent annular protrusion is formed on the side that contacts the first electrode.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1130841A JPH02309643A (en) | 1989-05-24 | 1989-05-24 | Semiconductor device |
| DE68926448T DE68926448T2 (en) | 1988-10-14 | 1989-10-13 | IMAGE SENSOR AND METHOD FOR THE PRODUCTION THEREOF |
| PCT/JP1989/001059 WO1990004263A1 (en) | 1988-10-14 | 1989-10-13 | Image sensor and method of producing the same |
| EP89911393A EP0393206B1 (en) | 1988-10-14 | 1989-10-13 | Image sensor and method of producing the same |
| US07/476,483 US5065006A (en) | 1988-10-14 | 1989-10-13 | Image sensors with simplified chip mounting |
| US07/739,562 US5138145A (en) | 1988-10-14 | 1991-08-21 | Method for producing image sensors with current flow into chip and with simplified chip mounting |
| US07/884,826 US5266828A (en) | 1988-10-14 | 1992-05-18 | Image sensors with an optical fiber array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1130841A JPH02309643A (en) | 1989-05-24 | 1989-05-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02309643A true JPH02309643A (en) | 1990-12-25 |
Family
ID=15043955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1130841A Pending JPH02309643A (en) | 1988-10-14 | 1989-05-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02309643A (en) |
-
1989
- 1989-05-24 JP JP1130841A patent/JPH02309643A/en active Pending
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