JPH05235084A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05235084A
JPH05235084A JP3653292A JP3653292A JPH05235084A JP H05235084 A JPH05235084 A JP H05235084A JP 3653292 A JP3653292 A JP 3653292A JP 3653292 A JP3653292 A JP 3653292A JP H05235084 A JPH05235084 A JP H05235084A
Authority
JP
Japan
Prior art keywords
bonding pad
bonding
recess
film
lead wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3653292A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Yamada
祥之 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3653292A priority Critical patent/JPH05235084A/en
Publication of JPH05235084A publication Critical patent/JPH05235084A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent a bonding pad from spreading sideways due to an external force applied at bonding so as to enhance the bonding of a lead wire to the bonding pad in strength. CONSTITUTION:An insulating film 2 is formed on a P-type semiconductor substrate 1, and then a conductive film 3 provided with an opening 4 is formed thereon. Then, interlayer insulating films 5 and 6 are formed, and then a bonding pad 7 is provided through a gold plating method. At this point, a recess (groove) 8 of 5mum or so width is formed inside the opening 4. Lastly, a protective film of polyimide is formed. By this setup, distortions of the bonding pad 7 caused by an external pressure at bonding concentrate on the recess 8. The bonding pad 7 is deformed inwardly, centering on the recess 8, so that it hardly spreads sideways.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はボンディングパッドの構
造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonding pad structure.

【０００２】[0002]

【従来の技術】近年の多ピン化にともない、ＴＡＢ（ｔ
ａｐｅ ｆｕｔｏｍａｔｅｄ ｂｏｎｄｉｎｇ）方式が
増加している。半導体チップの最上層配線には厚さ５〜
２０μｍの金めっきが用いられる。表面保護膜は窒化膜
をはじめとする無機膜から、金配線の側壁によく密着
し、ボンディングの際の外部圧力にもクラックが生じな
いポリイミドのような有機系の塗布膜に変っている。2. Description of the Related Art TAB (t
The number of ape fused bonding systems is increasing. The top wiring of the semiconductor chip has a thickness of 5
20 μm gold plating is used. The surface protective film is changed from an inorganic film such as a nitride film to an organic coating film such as polyimide that adheres well to the side wall of the gold wiring and does not crack even under external pressure during bonding.

【０００３】従来のボンディングパッドについて、図３
（ａ）を参照して説明する。FIG. 3 shows a conventional bonding pad.
A description will be given with reference to (a).

【０００４】Ｐ型半導体基板１に熱酸化膜からなる絶縁
膜２を介して導電膜３からなる下層配線が形成されてい
る。その上に形成された層間絶縁膜５，６の開口を通し
て上層配線となるボンディングパッド７が形成されてい
る。さらにボンディングパッド７の縁に沿ってポリイミ
ドからなる有機系塗布膜９が形成されている。A lower wiring made of a conductive film 3 is formed on a P-type semiconductor substrate 1 with an insulating film 2 made of a thermal oxide film interposed therebetween. Bonding pads 7 serving as upper layer wirings are formed through the openings of the interlayer insulating films 5 and 6 formed thereon. Furthermore, an organic coating film 9 made of polyimide is formed along the edge of the bonding pad 7.

【０００５】ボンディングパッド７の横広がりを防ぐた
め、ボンディングパッド７周囲に保護膜となる有機系塗
布膜９が密着して形成されている。リード線をボンディ
ングパッド７に接続するとき、リード線の拡がりは１．
５倍、ボンディングパッド７の拡がりは１．２倍に止め
ることができる。In order to prevent lateral spreading of the bonding pad 7, an organic coating film 9 serving as a protective film is formed in close contact with the periphery of the bonding pad 7. When connecting the lead wire to the bonding pad 7, the spread of the lead wire is 1.
The spread of the bonding pad 7 can be reduced to 5 times and the expansion of the bonding pad 7 to 1.2 times.

【０００６】[0006]

【発明が解決しようとする課題】ボンディングパッドの
周囲に有機塗布膜が形成されているので、ボンディング
の際の圧力により変形しないので、リード線とボンディ
ングパッドとの十分な圧着強度が得られなかった。さら
に大きな圧力を加えてボンディングすると、図３（ｂ）
に示すようにリード線１０の圧着部のくびれた部分１１
に歪が集中して、やがてリード線が断線するという問題
があった。Since the organic coating film is formed around the bonding pad, it is not deformed by the pressure during bonding, so that sufficient pressure bonding strength between the lead wire and the bonding pad cannot be obtained. . When bonding is performed by applying a larger pressure, as shown in FIG.
As shown in FIG.
There was a problem that the strain was concentrated on the wire and eventually the lead wire was broken.

【０００７】[0007]

【課題を解決するための手段】本発明の半導体装置は、
ボンディングパッドのリード線接続面に凹部を備えたも
のである。The semiconductor device of the present invention comprises:
The bonding pad is provided with a recess on the lead wire connecting surface.

【０００８】[0008]

【実施例】本発明の第１の実施例について、図１（ａ）
の平面図およびそのＡ−Ｂ断面図である図１（ｂ）を参
照して説明する。EXAMPLE FIG. 1A shows a first example of the present invention.
Will be described with reference to a plan view of FIG.

【０００９】Ｐ型半導体基板１上に絶縁膜２を形成した
のち、スパッタ法により導電膜３を堆積してからフォト
リソグラフィによりパターニングする。同時に導電膜３
に開口４を形成する。つぎにプラズマＣＶＤ法により層
間絶縁膜５，６を堆積してからフォトリソグラフィによ
り開口４を露出させる。After forming the insulating film 2 on the P-type semiconductor substrate 1, a conductive film 3 is deposited by a sputtering method and then patterned by photolithography. Conductive film 3 at the same time
The opening 4 is formed in the. Next, the interlayer insulating films 5 and 6 are deposited by the plasma CVD method, and then the opening 4 is exposed by photolithography.

【００１０】つぎに金めっき法により厚さ２０μｍのボ
ンディングパッド７を形成する。このときボンディング
パッド７に幅約５μｍの凹部（溝）８が形成される。最
後にポリイミドからなる保護膜９を形成する。Next, a bonding pad 7 having a thickness of 20 μm is formed by a gold plating method. At this time, a recess (groove) 8 having a width of about 5 μm is formed on the bonding pad 7. Finally, the protective film 9 made of polyimide is formed.

【００１１】本実施例では接続時の外部圧力によるボン
ディングパッド７の歪が凹部８の溝に集中する。ボンデ
ィングパッド７は凹部８を中心に内側に変形して、横方
向に拡がることはない。In this embodiment, the strain of the bonding pad 7 due to the external pressure at the time of connection is concentrated in the groove of the recess 8. The bonding pad 7 is deformed inward around the recess 8 and does not expand in the lateral direction.

【００１２】つぎに本発明の第２の実施例について、図
２の平面図を参照して説明する。Next, a second embodiment of the present invention will be described with reference to the plan view of FIG.

【００１３】導電膜を十字型に形成して、ボンディング
パッド８の上に十字型の凹部を８形成する。The conductive film is formed in a cross shape, and a cross-shaped recess 8 is formed on the bonding pad 8.

【００１４】本実施例では組立工程において、リード線
をどの方向からボンディングパッド７に接続しても、ボ
ンディングパッド７の歪が凹部８の溝に集中して内側方
向に変形して、横方向に拡がることはない。In this embodiment, no matter which direction the lead wire is connected to the bonding pad 7 in the assembly process, the strain of the bonding pad 7 concentrates in the groove of the recess 8 and is deformed inward, so that it is laterally deformed. It does not spread.

【００１５】[0015]

【発明の効果】ボンディングパッドのリード線接続部に
幅約５μｍの凹部を設ける。その結果リードボンディン
グ時の外部圧力によって生じるボンデイングパッドの横
方向の拡がりを防止する。ボンディングパッドのピッチ
を狭めることができる。EFFECTS OF THE INVENTION A recess having a width of about 5 μm is provided at the lead wire connecting portion of the bonding pad. As a result, lateral expansion of the bonding pad caused by external pressure during lead bonding is prevented. The pitch of the bonding pad can be narrowed.

【００１６】外部圧力による内側方向の変形による横方
向の拡がりなしにボンディングパッドとリード線との圧
着強度を増大させることができる。[0016] It is possible to increase the pressure bonding strength between the bonding pad and the lead wire without the lateral expansion due to the inward deformation caused by the external pressure.

【００１７】したがってボンディングパッドの溝の幅お
よび形状を制御することにより、、リード線の圧着部付
近のくびれた部分に無理な力が集中するのを防ぐことが
できる。ボンディングパッドの横拡がりを抑えて、十分
な圧着強度を得ることができる。Therefore, by controlling the width and shape of the groove of the bonding pad, it is possible to prevent excessive force from concentrating on the constricted portion of the lead wire near the crimped portion. It is possible to suppress lateral expansion of the bonding pad and obtain sufficient pressure bonding strength.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ）は本発明の第１の実施例を示す平面図で
ある。（ｂ）は（ａ）のＡ−Ｂ断面図である。FIG. 1A is a plan view showing a first embodiment of the present invention. (B) is an AB sectional view of (a).

【図２】本発明の第２の実施例を示す平面図である。FIG. 2 is a plan view showing a second embodiment of the present invention.

【図３】（ａ）は従来のボンディングパッドを示す断面
図である。（ｂ）はボンディングパッドにリード線を接
続した状態を示す平面図である。FIG. 3A is a sectional view showing a conventional bonding pad. (B) is a plan view showing a state in which lead wires are connected to the bonding pads.

【符号の説明】[Explanation of symbols]

１ Ｐ型シリコン基板 ２ 絶縁膜 ３ 導電膜 ４ 開口 ５，６ 層間絶縁膜 ７ ボンディングパッド ８ 凹部 ９ 有機系塗布膜 １０ リード線 １１ くびれた部分 1 P-type silicon substrate 2 Insulating film 3 Conductive film 4 Opening 5, 6 Interlayer insulating film 7 Bonding pad 8 Recess 9 Organic coating film 10 Lead wire 11 Constricted part

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 ボンディングパッドのリード線接続面に
凹部を備えた半導体装置。1. A semiconductor device having a recess on a lead wire connecting surface of a bonding pad.
JP3653292A 1992-02-24 1992-02-24 Semiconductor device Withdrawn JPH05235084A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3653292A JPH05235084A (en) 1992-02-24 1992-02-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3653292A JPH05235084A (en) 1992-02-24 1992-02-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05235084A true JPH05235084A (en) 1993-09-10

Family

ID=12472400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3653292A Withdrawn JPH05235084A (en) 1992-02-24 1992-02-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05235084A (en)

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Legal Events

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A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990518