JPH05218650A - Manufacture of multilayer wiring board - Google Patents
Manufacture of multilayer wiring boardInfo
- Publication number
- JPH05218650A JPH05218650A JP4601292A JP4601292A JPH05218650A JP H05218650 A JPH05218650 A JP H05218650A JP 4601292 A JP4601292 A JP 4601292A JP 4601292 A JP4601292 A JP 4601292A JP H05218650 A JPH05218650 A JP H05218650A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- hole
- substrate
- forming
- plating resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は多層配線板の製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board.
【０００２】[0002]
【従来の技術】多層配線板は例えば次の通りの方法で製
造している。すなわち、先ず触媒入り銅張り積層板にエ
ッチングレジスト層を形成し、エッチング処理をして内
層回路を形成する。次に、その表面に絶縁層及び接着剤
層を順次積層する。接着剤層を積層後、ドリルにより積
層板を貫通する孔を形成する。また、絶縁層と接着剤層
のみを通る非貫通孔をドリルにより形成する。貫通孔及
び非貫通孔を形成後、スクリーン印刷法や写真法によ
り、所定のパターンのめっきレジスト層を形成する。め
っきレジスト層を形成後、無電解めっき法により、表面
及び貫通孔と非貫通孔の壁面に無電解めっき処理等によ
りめっき層を形成し、回路を形成する。2. Description of the Related Art A multilayer wiring board is manufactured, for example, by the following method. That is, first, an etching resist layer is formed on a copper clad laminate containing a catalyst, and an etching process is performed to form an inner layer circuit. Next, an insulating layer and an adhesive layer are sequentially laminated on the surface. After laminating the adhesive layers, holes are formed through the laminated plate with a drill. Further, a non-through hole that passes only the insulating layer and the adhesive layer is formed by a drill. After forming the through holes and the non-through holes, a plating resist layer having a predetermined pattern is formed by a screen printing method or a photographic method. After forming the plating resist layer, a plating layer is formed on the surface and the wall surfaces of the through holes and the non-through holes by an electroless plating method, etc., to form a circuit.
【０００３】[0003]
【発明が解決しようとする課題】しかし、従来の方法で
は、非貫通孔を形成する工程と、めっきレジスト層とを
形成する工程とを別々の装置により別々に行っている。
そのために、装置から装置に運搬する間に基板が損傷し
たり、ゴミ等が付着してめっきレジスト層を形成する際
に不良を生じるおそれのある欠点がある。However, in the conventional method, the step of forming the non-through hole and the step of forming the plating resist layer are separately performed by different devices.
Therefore, there is a drawback that the substrate may be damaged during transportation from device to device and dust or the like may adhere to cause a defect when forming the plating resist layer.
【０００４】本発明の目的は、以上の欠点を改良し、損
傷やめっきレジスト層の不良を低下できる多層配線板の
製造方法を提供するものである。An object of the present invention is to provide a method for manufacturing a multilayer wiring board, which is capable of improving the above-mentioned drawbacks and reducing damages and defective plating resist layers.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記の目的を
達成するために、エキシマレーザーにより非貫通孔とめ
っきレジストパターンとを形成することを特徴とする多
層配線板の製造方法を提供するものである。In order to achieve the above object, the present invention provides a method for manufacturing a multilayer wiring board characterized by forming a non-through hole and a plating resist pattern by an excimer laser. It is a thing.
【０００６】[0006]
【作用】非貫通孔とめっきレジストパターンをエキシマ
レーザーによって形成することにより、別々の装置を用
いる必要がなくなるので、運搬途中で生じる損傷等の不
良を防止できる。By forming the non-through hole and the plating resist pattern by the excimer laser, it is not necessary to use separate devices, and therefore defects such as damages occurring during transportation can be prevented.
【０００７】[0007]
【実施例】以下、本発明を実施例に基づいて説明する。
先ず、図１に示す通り、基板１として触媒入りガラスエ
ポキシ樹脂銅張り積層板を用いる。そしてこの基板１に
エッチングレジストパターンを形成し、エッチング処理
して内層回路２を形成する。次に、図２に示す通り、基
板１の両面にエポキシ樹脂、フィラー、触媒及び硬化剤
からなる絶縁層３を形成する。また、絶縁層３の表面
に、エポキシ樹脂、ニトリルブタジエンゴム、フィラ
ー、触媒及び硬化剤からなる接着剤層４を形成する。接
着剤層４を形成後、図３に示す通り、ドリルを用いて、
基板１を貫通する孔５を形成する。貫通孔５を形成後、
図４に示す通り、接着剤層４の表面に、エポキシ樹脂、
フィラー及び硬化剤からなるめっきレジスト層６を形成
する。めっきレジスト層６を形成後、図５に示す通り、
エキシマレーザーを用いて、外層回路を形成する部分の
めっきレジスト層６を溶解し、めっきレジストパターン
７を形成する。また、このエキシマレーザーを用い、そ
の出力を変えて、めっきレジスト層６、接着剤層４及び
絶縁層３の所定箇所を除去し、非貫通孔８を形成して、
内層回路２を露出させる。さらに、図６に示す通り、無
電解銅めっき処理を行い、外層回路９を形成する。また
同時に、貫通孔５及び非貫通孔８内に各々めっき層１０
及び１１を形成する。EXAMPLES The present invention will be described below based on examples.
First, as shown in FIG. 1, a glass epoxy resin copper clad laminate containing a catalyst is used as the substrate 1. Then, an etching resist pattern is formed on the substrate 1 and an etching process is performed to form the inner layer circuit 2. Next, as shown in FIG. 2, an insulating layer 3 including an epoxy resin, a filler, a catalyst and a curing agent is formed on both surfaces of the substrate 1. Further, the adhesive layer 4 made of epoxy resin, nitrile butadiene rubber, filler, catalyst and curing agent is formed on the surface of the insulating layer 3. After forming the adhesive layer 4, as shown in FIG. 3, using a drill,
A hole 5 penetrating the substrate 1 is formed. After forming the through hole 5,
As shown in FIG. 4, on the surface of the adhesive layer 4, epoxy resin,
A plating resist layer 6 including a filler and a curing agent is formed. After forming the plating resist layer 6, as shown in FIG.
An excimer laser is used to dissolve the plating resist layer 6 in the portion forming the outer layer circuit to form the plating resist pattern 7. Further, by using this excimer laser and changing its output, predetermined portions of the plating resist layer 6, the adhesive layer 4 and the insulating layer 3 are removed, and the non-through holes 8 are formed.
The inner layer circuit 2 is exposed. Further, as shown in FIG. 6, electroless copper plating is performed to form the outer layer circuit 9. At the same time, the plated layer 10 is formed in each of the through holes 5 and the non-through holes 8.
And 11 are formed.
【０００８】次に、実施例と従来例について、めっきレ
ジストパターンと非貫通孔とを形成するのに要する加工
時間を比較する。実施例と従来例の条件は次の通りとす
る。 実施例： イ）基板 ＪＩＳ Ｃ５０１２の図３に示すパターンを用い、内層
回路にこの裏面のパターンを形成し、外層回路に表面の
パターンを形成した片面２層板とする。そして貫通孔は
設けず、内層回路と外層回路とをつなぐ非貫通孔だけを
設ける。 ロ）絶縁層 エポキシ樹脂、フィラー、触媒及び硬化剤からなり、厚
さ５０μｍとする。 ハ）接着剤層 エポキシ樹脂、ニトリルブタジエンゴム、フィラー、触
媒及び硬化剤からなり、厚さ２０μｍとする。 ニ）めっきレジストパターン エポキシ樹脂、フィラー及び硬化剤からなる厚さ３５μ
ｍのめっきレジスト層を形成する。そしてこのめっきレ
ジスト層に、ＫｒＦを発振線とし、波長２４８ｎｍ、照
射エネルギー２５０ｍＪ／cm2 、７０パルスのエキシマ
レーザーを照射して、外層回路のライン幅０．１mmのめ
っきレジストパターンを形成する。１回の照射面積は５
０×５０mmとする。 ホ）非貫通孔 めっきレジスト層、接着剤及び絶縁層に、２１０パルス
とする以外は上記と同一条件でエキシマレーザーを照射
して、径φ０．３mmの非貫通孔を形成する。Next, the working time required to form the plating resist pattern and the non-through holes will be compared between the embodiment and the conventional example. The conditions of the example and the conventional example are as follows. Example: a) Substrate A single-sided, two-layer board is used in which the pattern shown in FIG. 3 of JIS C5012 is used and the back surface pattern is formed on the inner layer circuit and the front surface pattern is formed on the outer layer circuit. Then, the through hole is not provided, and only the non-through hole that connects the inner layer circuit and the outer layer circuit is provided. B) Insulating layer It is made of epoxy resin, filler, catalyst and curing agent and has a thickness of 50 μm. C) Adhesive layer: made of epoxy resin, nitrile butadiene rubber, filler, catalyst and curing agent, and has a thickness of 20 μm. D) Plating resist pattern 35 μm thick consisting of epoxy resin, filler and curing agent
m plating resist layer is formed. Then, this plating resist layer is irradiated with an excimer laser having a wavelength of 248 nm and an irradiation energy of 250 mJ / cm 2 and 70 pulses using KrF as an oscillation line to form a plating resist pattern having a line width of 0.1 mm in the outer layer circuit. The irradiation area of one time is 5
0x50 mm. (E) Non-through hole The plating resist layer, the adhesive and the insulating layer are irradiated with an excimer laser under the same conditions as above except that 210 pulses are used to form a non-through hole having a diameter of 0.3 mm.
【０００９】従来例：実施例と同一のパターンを用い
る。そして内層回路に裏面のパターンを形成した後、絶
縁層及び接着剤層を形成する。その後、ドリルを用いて
非貫通孔を形成する。次に、めっきレジストパターンを
写真法により形成する。これ以外の製造条件は実施例と
同一とする。Conventional example: The same pattern as that of the embodiment is used. Then, after forming a pattern on the back surface in the inner layer circuit, an insulating layer and an adhesive layer are formed. Then, a non-through hole is formed using a drill. Next, a plating resist pattern is formed by a photographic method. The other manufacturing conditions are the same as those in the embodiment.
【００１０】測定の結果、実施例は１．１秒、従来例は
３２秒かかり、前者は後者の約１／２９に短縮される。
なお、実施例ではエキシマレーザーに広がりがあるた
め、１回の照射で複数の非貫通孔を形成できた。As a result of the measurement, the embodiment takes 1.1 seconds, the conventional example takes 32 seconds, and the former is shortened to about 1/29 of the latter.
In the example, since the excimer laser has a spread, it was possible to form a plurality of non-through holes with one irradiation.
【００１１】[0011]
【発明の効果】以上の通り、本発明によれば、非貫通孔
とめっきレジストパターンとをエキシマレーザーにより
形成しているために、運搬途中の損傷やゴミの付着によ
る不良を低減でき、また、これらの加工時間を短縮でき
る多層配線板の製造方法が得られる。As described above, according to the present invention, since the non-through hole and the plating resist pattern are formed by the excimer laser, it is possible to reduce the damage due to damage during transportation or the adhesion of dust, and It is possible to obtain a method for manufacturing a multilayer wiring board that can reduce the processing time.
【図面の簡単な説明】[Brief description of drawings]
【図１】内層回路を形成した基板の断面図を示す。FIG. 1 is a cross-sectional view of a substrate on which an inner layer circuit is formed.
【図２】接着剤層までを形成した基板の断面図を示す。FIG. 2 shows a cross-sectional view of a substrate on which an adhesive layer is formed.
【図３】貫通孔を形成した基板の断面図を示す。FIG. 3 shows a sectional view of a substrate having a through hole formed therein.
【図４】めっきレジスト層を形成した基板の断面図を示
す。FIG. 4 shows a cross-sectional view of a substrate on which a plating resist layer is formed.
【図５】めっきレジストパターン及び非貫通孔を形成し
た基板の断面図を示す。FIG. 5 shows a cross-sectional view of a substrate on which a plating resist pattern and non-through holes are formed.
【図６】外層回路及びめっき層を形成した基板の断面図
を示す。FIG. 6 shows a cross-sectional view of a substrate on which an outer layer circuit and a plating layer are formed.
１…基板、 ２…内層回路、 ３…絶縁層、 ５…貫通
孔、７…めっきレジストパターン、 ８…非貫通孔、
９…外層回路、１０，１１…めっき層。DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Inner layer circuit, 3 ... Insulating layer, 5 ... Through hole, 7 ... Plating resist pattern, 8 ... Non-through hole,
9 ... Outer layer circuit, 10, 11 ... Plating layer.
フロントページの続き (72)発明者 竹田 時定 栃木県芳賀郡二宮町大字久下田1065番地 日立エーアイシー株式会社内 (72)発明者 福里 健志郎 栃木県芳賀郡二宮町大字久下田1065番地 日立エーアイシー株式会社内Front page continued (72) Inventor Tokichi Takeda 1065 Kushita, Ninomiya-cho, Haga-gun, Tochigi Prefecture Hitachi AIC Co., Ltd. In the company
Claims (1)
した後、非貫通孔とめっきレジストパターンとを形成
し、めっき処理により外層回路を形成する多層配線板の
製造方法において、エキシマレーザーより非貫通孔とめ
っきレジストパターンとを形成することを特徴とする多
層配線板の製造方法。1. A method for manufacturing a multilayer wiring board, comprising forming a non-through hole and a plating resist pattern after laminating an insulating layer on a substrate on which an inner layer circuit is formed, and forming an outer layer circuit by plating. A method for manufacturing a multilayer wiring board, comprising forming a non-through hole and a plating resist pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4601292A JPH05218650A (en) | 1992-01-31 | 1992-01-31 | Manufacture of multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4601292A JPH05218650A (en) | 1992-01-31 | 1992-01-31 | Manufacture of multilayer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05218650A true JPH05218650A (en) | 1993-08-27 |
Family
ID=12735151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4601292A Pending JPH05218650A (en) | 1992-01-31 | 1992-01-31 | Manufacture of multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05218650A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007311642A (en) * | 2006-05-19 | 2007-11-29 | Sharp Corp | Method of manufacturing multilayer printed wiring board |
-
1992
- 1992-01-31 JP JP4601292A patent/JPH05218650A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007311642A (en) * | 2006-05-19 | 2007-11-29 | Sharp Corp | Method of manufacturing multilayer printed wiring board |
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