JPH05218137A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05218137A JPH05218137A JP1927992A JP1927992A JPH05218137A JP H05218137 A JPH05218137 A JP H05218137A JP 1927992 A JP1927992 A JP 1927992A JP 1927992 A JP1927992 A JP 1927992A JP H05218137 A JPH05218137 A JP H05218137A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor element
- wiring board
- semiconductor
- inspection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に係わり、特に半導体素子のフェイスダウンボンディン
グの改良をはかった半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device with improved face down bonding of semiconductor elements.
【０００２】[0002]
【従来の技術】近年、半導体集積回路技術の進歩によ
り、端子数が１００を越える半導体素子やパッドピッチ
が１００μｍ以下の半導体素子が出現してきている。2. Description of the Related Art In recent years, with the progress of semiconductor integrated circuit technology, semiconductor devices having more than 100 terminals and a pad pitch of 100 μm or less have appeared.
【０００３】それに伴い半導体素子の実装密度を向上さ
せた半導体装置の製造方法として、図２（ａ）に示すよ
うな配線基板２１に光若しくは熱硬化性の樹脂１５をポ
ッティングした後に、半導体素子１１と配線基板２１を
位置合わせする工程、あるいは逆に半導体素子１１と配
線基板２１を位置合わせした後に、配線基板２１に光若
しくは熱硬化性の樹脂１５をポッティングする工程を行
い、その後図２（ｂ）に示すように半導体素子１１を配
線基板２１に圧接させ、半導体素子１１上のバンプ１２
と配線パターン２２の接触を保ちつつ樹脂１５を硬化
し、接続をとる方法が提案されている。As a method of manufacturing a semiconductor device in which the mounting density of semiconductor elements is improved accordingly, the semiconductor element 11 is formed after potting a light or thermosetting resin 15 on a wiring board 21 as shown in FIG. The step of aligning the wiring board 21 with the wiring board 21 or, conversely, the step of potting the light-curable or thermosetting resin 15 on the wiring board 21 after the semiconductor element 11 and the wiring board 21 are aligned. ), The semiconductor element 11 is brought into pressure contact with the wiring substrate 21, and the bumps 12 on the semiconductor element 11 are
A method has been proposed in which the resin 15 is hardened while maintaining contact between the wiring pattern 22 and the wiring pattern 22 to establish a connection.
【０００４】また、図３（ａ）（ｂ）に示すように半導
体素子１１と配線基板２１を位置合わせし、半導体素子
１１を配線基板２１に圧接した後に、半導体素子１１と
配線基板２１の一部又は隙間に光若しくは熱硬化性樹脂
１５を含浸し、硬化させる方法が提案されている。Further, as shown in FIGS. 3A and 3B, the semiconductor element 11 and the wiring board 21 are aligned, and the semiconductor element 11 is pressed against the wiring board 21. A method of impregnating a part or a gap with a light or thermosetting resin 15 to cure the resin has been proposed.
【０００５】しかしながら、これらの方法にあっては次
のような問題点があった。すなわち、図２のような場
合、半導体素子１１と配線基板２１に介在する樹脂１５
は光若しくは熱硬化性の樹脂のため、硬化後の信頼性は
高いものの半導体素子１１に不良が生じた場合や、実装
工程でのミスにより、接続が得られなかった時に、硬化
した樹脂を除去し半導体素子を取り替えることはきわめ
て困難であった。However, these methods have the following problems. That is, in the case of FIG. 2, the resin 15 interposed between the semiconductor element 11 and the wiring board 21.
Is a light or thermosetting resin, so it has high reliability after curing, but when the semiconductor element 11 has a defect or when a connection cannot be obtained due to an error in the mounting process, the cured resin is removed. However, it is extremely difficult to replace the semiconductor element.
【０００６】また図３のような場合、半導体素子１１を
配線基板２１に圧接した後、樹脂が介在しない状態で半
導体素子１１の動作検査や、半導体素子１１と配線基板
２１との接続検査をすることができるので、不良であっ
た時には、容易に半導体素子を取り替えることができ
る。その後、樹脂を含浸し、硬化させることで信頼性の
高い接続を得ることができる。しかし、このときには樹
脂のない状態で接続をするために、半導体素子１１と配
線基板２１の接続強度が弱く、検査工程や、樹脂含浸工
程での衝撃によって接続がとれてしまうことがあり、信
頼性が低かった。Further, in the case of FIG. 3, after the semiconductor element 11 is pressed against the wiring board 21, an operation inspection of the semiconductor element 11 and a connection inspection between the semiconductor element 11 and the wiring board 21 are performed without resin. Therefore, the semiconductor element can be easily replaced when it is defective. After that, the resin is impregnated and cured to obtain a highly reliable connection. However, at this time, since the connection is made without the resin, the connection strength between the semiconductor element 11 and the wiring board 21 is weak, and the connection may be broken due to the impact in the inspection process or the resin impregnation process. Was low.
【０００７】[0007]
【発明が解決しようとする課題】このように、あらかじ
め光若しくは熱硬化性の樹脂を介在させ、その樹脂の硬
化収縮によって半導体素子を配線基板に実装する方法で
は不良が生じた場合の取り替えが極めて困難であった。
また半導体素子を配線基板に実装した後に樹脂を含浸し
硬化させる方法では、樹脂含浸前の接続強度が弱く、信
頼性が低かった。本発明は、上記問題点を考慮してなさ
れたもので、その目的とすることろは、半導体素子を配
線基板にフェイスダウンで実装することができ、且つ検
査等の結果等に基づき必要に応じ半導体素子の交換を容
易化をはかり得ることができ、且つ接続の強度を増し、
信頼性向上をはかり得る半導体装置およびその製造方法
を提供することにある。As described above, the method of interposing a light or thermosetting resin in advance and mounting the semiconductor element on the wiring substrate by the curing shrinkage of the resin is extremely replaced when a defect occurs. It was difficult.
Further, in a method in which a semiconductor element is mounted on a wiring board and then impregnated with a resin and cured, the connection strength before resin impregnation is weak and the reliability is low. The present invention has been made in view of the above problems, and its purpose is to enable semiconductor elements to be mounted face down on a wiring board, and if necessary, based on the results of inspection, etc. It is possible to facilitate the replacement of semiconductor elements, and increase the strength of the connection,
It is an object of the present invention to provide a semiconductor device capable of improving reliability and a manufacturing method thereof.
【０００８】[0008]
【課題を解決するための手段】本発明は半導体素子を配
線基板上にフェイスダウンで実装する半導体装置の製造
方法において、前記半導体素子と前記配線基板との間に
熱可塑性樹脂を介在させ加熱および加圧により、前記半
導体素子と前記配線基板との電気的接続をとる工程と、
前記半導体素子の動作検査および半導体素子と配線基板
との接続検査を行う工程と，前記検査工程により良品と
判断された場合のみ少なくとも前記半導体素子、前記配
線基板の一部および前記熱可塑性樹脂の露出部を熱硬化
性樹脂で被覆し、加熱により前記半導体素子を前記配線
基板に固着させる工程を含むことを特徴とする半導体装
置の製造方法である。According to the present invention, in a method of manufacturing a semiconductor device in which a semiconductor element is mounted face down on a wiring board, a thermoplastic resin is interposed between the semiconductor element and the wiring board to heat and A step of electrically connecting the semiconductor element and the wiring board by applying pressure,
A step of performing an operation inspection of the semiconductor element and a connection inspection between the semiconductor element and the wiring board, and at least exposing the semiconductor element, a part of the wiring board, and the thermoplastic resin only when the inspection step determines that the product is non-defective. It is a method of manufacturing a semiconductor device, including a step of coating a portion with a thermosetting resin and fixing the semiconductor element to the wiring board by heating.
【０００９】[0009]
【作用】本発明によれば、半導体素子を配線基板に実装
する際に、熱可塑性樹脂を介在させ、その樹脂の硬化に
よって半導体素子と配線基板との接続をとっている為、
樹脂の可塑温度以上に加熱すると接着力が低下するの
で、検査の結果、不良品が発生した場合には容易に半導
体素子の交換ができる。さらに検査の結果、不良品等を
全て除去した後、熱硬化性樹脂で半導体素子を配線基板
に強固に固着する為、極めて信頼性の高い半導体装置を
得ることができる。According to the present invention, when the semiconductor element is mounted on the wiring board, the thermoplastic resin is interposed and the resin is cured to connect the semiconductor element and the wiring board.
If the temperature exceeds the plasticizing temperature of the resin, the adhesive strength decreases, so that if a defective product is found as a result of the inspection, the semiconductor element can be easily replaced. Further, as a result of the inspection, after removing all defective products and the like, the semiconductor element is firmly fixed to the wiring board with the thermosetting resin, so that a highly reliable semiconductor device can be obtained.
【００１０】[0010]
【実施例】以下、本発明の実施例を図面を参照して説明
する。Embodiments of the present invention will be described below with reference to the drawings.
【００１１】図１は本発明の一実施例に係わる半導体装
置の製造工程を示す概略図である。まず、図１（ａ）に
示すごとく、バンプ１２が形成された半導体素子１１と
配線パターン２２が形成された配線基板２１を用意し、
配線基板２１上に熱可塑性樹脂１３をポッティングす
る。次に図１（ｂ）に示すごとく、半導体素子１１と配
線基板２１の位置合わせを行い、加熱ヘッド３１により
半導体素子１１を加熱しながら配線基板２１に押圧し、
バンプ１２を配線パターン２２と接触させ電気的接続を
とる。配線基板２１側は必要に応じてステージ３２を加
熱する。このとき熱可塑性樹脂１３は可塑性の状態にあ
る。ここではポッティングの後に位置合わせを行った
が、この工程は逆でも構わない。FIG. 1 is a schematic view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1A, a semiconductor element 11 having bumps 12 and a wiring board 21 having a wiring pattern 22 are prepared,
The thermoplastic resin 13 is potted on the wiring board 21. Next, as shown in FIG. 1B, the semiconductor element 11 and the wiring board 21 are aligned, and the heating head 31 presses the semiconductor element 11 against the wiring board 21 while heating the semiconductor element 11.
The bump 12 is brought into contact with the wiring pattern 22 to establish electrical connection. The wiring board 21 side heats the stage 32 as needed. At this time, the thermoplastic resin 13 is in a plastic state. Although the positioning is performed after the potting here, this step may be reversed.
【００１２】次に、加熱を除去することによって樹脂１
３の硬化が始まり、加圧除去後も半導体素子１１と配線
基板２１の電気的接続は保たれるのみならず、樹脂の硬
化によって機械的接続をも保つことができる。温度を速
く下げたい場合には空気ブロー等の冷却機構を併用する
と効果的である。The resin 1 is then removed by removing the heat.
The hardening of No. 3 starts, and after the pressure is removed, not only the electrical connection between the semiconductor element 11 and the wiring board 21 can be maintained, but also the mechanical connection can be maintained by the hardening of the resin. When it is desired to lower the temperature quickly, it is effective to use a cooling mechanism such as air blow together.
【００１３】次に、半導体素子１１の動作検査や半導体
素子１１と配線基板２１との接続検査を行う。このとき
異常があり半導体素子１１の交換が必要になった場合に
は、半導体装置１１や配線基板２１を加熱することによ
って熱可塑性樹脂１３は可塑化し、容易に交換ができる
ようになる。接続検査は、半導体素子１１の電源端子と
他の端子間とのダイオードチェックをすることにより簡
便に技能不良を調べる方法もあるが，ここでは，プロー
バーに半導体素子１１を搭載した配線基板２１をセッテ
ィングし、プローブ針→配線パターン２２→半導体素子
１１→配線パターン２２→プローブ針の経路で半導体素
子１１の動作検査を行い，接続の良否を判断した。Next, an operation inspection of the semiconductor element 11 and a connection inspection between the semiconductor element 11 and the wiring board 21 are performed. If the semiconductor element 11 needs to be replaced at this time due to an abnormality, the thermoplastic resin 13 is plasticized by heating the semiconductor device 11 and the wiring board 21, and the replacement becomes easy. For connection inspection, there is a method of simply checking for a technical defect by performing a diode check between the power supply terminal of the semiconductor element 11 and another terminal, but here, the wiring board 21 having the semiconductor element 11 mounted on the prober is set. Then, the operation of the semiconductor element 11 was inspected along the route of probe needle → wiring pattern 22 → semiconductor element 11 → wiring pattern 22 → probe needle to determine whether the connection was good or bad.
【００１４】実装後の検査が正常であれば図１（ｃ）に
示したように熱可塑性樹脂１３を覆うように熱硬化性樹
脂１４を塗布し加熱により硬化させると信頼性が著しく
向上する。If the inspection after mounting is normal, the thermosetting resin 14 is applied so as to cover the thermoplastic resin 13 as shown in FIG.
【００１５】つまり熱可塑性樹脂１３には半導体素子１
１と配線基板２１の電気的接続と機械的接続をとる役目
をもたせ、熱硬化性樹脂１４は機械的接続強度の補強と
耐環境性向上をはかる役目をもたせる。これによって製
品の使用が熱可塑性樹脂１３の可塑化温度以上になって
も熱硬化性樹脂１４によって機械的接続はもちろん電気
的接続も保たれる。また通常熱硬化性樹脂１４は熱可塑
性樹脂１３よりはるかに耐環境性に優れているので信頼
性向上に役立つ。本実施例において、熱可塑性樹脂１３
の量は図１（ｂ）や（ｃ）に示したようにバンプ１２を
覆う量としたが、図１（ｄ）に示したように樹脂量がバ
ンプを覆わない量とした場合でも、半導体素子１１と配
線基板２１の電気的及び機械的接続を保つことができ
る。さらに熱硬化性樹脂１４を塗布すると図１（ｃ）の
構造の時と同様の信頼性を得ることができる。熱硬化性
樹脂１４は粘度を調整することによって、半導体素子１
１と配線基板２１の隙間に充填できる。一般に熱硬化性
樹脂１４の量は図１（ｅ）に示したように、半導体素子
１１を覆っても図１（ｃ）の構造の時と同様の信頼性を
得ることができる。That is, the semiconductor element 1 is formed on the thermoplastic resin 13.
1, and the thermosetting resin 14 serves to reinforce the mechanical connection strength and to improve the environment resistance. As a result, even if the use of the product exceeds the plasticizing temperature of the thermoplastic resin 13, the thermosetting resin 14 maintains not only mechanical connection but also electrical connection. Further, since the thermosetting resin 14 is usually much more excellent in environment resistance than the thermoplastic resin 13, it is useful for improving reliability. In this embodiment, the thermoplastic resin 13
1B and 1C are used to cover the bumps 12. However, even if the amount of resin does not cover the bumps as shown in FIG. The electrical and mechanical connection between the element 11 and the wiring board 21 can be maintained. Further, when the thermosetting resin 14 is applied, the same reliability as in the structure of FIG. 1C can be obtained. By adjusting the viscosity of the thermosetting resin 14, the semiconductor element 1
The gap between 1 and the wiring board 21 can be filled. In general, as shown in FIG. 1E, the amount of the thermosetting resin 14 can cover the semiconductor element 11 and obtain the same reliability as in the structure of FIG. 1C.
【００１６】本実施例についての製造方法、製造条件を
さらに詳しく述べる。半導体素子１１の多くは電極部が
アルミニウム電極となっており、この電極はパッシベー
ション膜の面よりわずかに凹んである。従ってこの半導
体素子を配線基板と接続しても電気的接続はとれない。
つまり電気的接続をとるためには半導体素子の電極をパ
ッシベーション膜より高くするバンプ１２を形成する必
要がある。バンプの形成は、アルミニウム電極上に接着
層や、拡散防止層を設け、電気メッキによりバンプを形
成する湿式ハンプの方法、別の支持基板に前述と同様の
方法でバンプを形成しておき、このバンプを半導体素子
側に転写する転写バンプの方法や、ボールボンディング
の手法を利用してアルミニウム電極上にボールバンプを
形成する方法や、アルミニウム電極上に無電解メッキに
よってバンプを形成する方法や、アルミニウム電極上に
半田に濡れる金属を着膜した後に、溶融した半田槽に浸
漬して形成する方法などがあり、このどれを用いても構
わない。またバンプには金、銅、ニッケルや、スズ・鉛
・インジウム等からなる半田を単独で、あるいは２種以
上のバンプを積層して使用することもできる。The manufacturing method and manufacturing conditions for this embodiment will be described in more detail. Most of the semiconductor elements 11 have aluminum electrodes as electrode portions, and the electrodes are slightly recessed from the surface of the passivation film. Therefore, even if this semiconductor element is connected to the wiring board, electrical connection cannot be established.
That is, it is necessary to form the bumps 12 that make the electrodes of the semiconductor element higher than the passivation film in order to establish electrical connection. To form the bumps, an adhesive layer or a diffusion prevention layer is provided on the aluminum electrode, a wet hump method is used to form the bumps by electroplating, or a bump is formed on another supporting substrate by the same method as described above. A transfer bump method for transferring a bump to a semiconductor element side, a ball bump forming method for forming a ball bump on an aluminum electrode, a method for forming a bump on an aluminum electrode by electroless plating, an aluminum There is a method of depositing a metal that wets the solder on the electrode and then immersing it in a molten solder bath, and any of these may be used. Further, for the bumps, solder made of gold, copper, nickel, tin, lead, indium or the like can be used alone, or two or more kinds of bumps can be stacked and used.
【００１７】本実施例ではアルミニウム電極に活性化処
理を行い、亜鉛置換した後、無電解のニッケルメッキを
しニッケルバンプを形成した。さらに半導体素子をイン
ジウム鉛合金の溶融槽に浸漬し、ニッケルバンプ上にイ
ンジウム鉛バンプを形成した。バンプサイズは７０×７
０μｍ、高さは７μｍ、バンプは１４８個、最小ピッチ
は１１０μｍである。In the present embodiment, the aluminum electrode was subjected to activation treatment, and after substituting with zinc, electroless nickel plating was performed to form a nickel bump. Further, the semiconductor element was dipped in a molten bath of indium lead alloy to form indium lead bumps on the nickel bumps. Bump size is 70 × 7
The height is 0 μm, the height is 7 μm, the number of bumps is 148, and the minimum pitch is 110 μm.
【００１８】本実施例では半導体素子の電極にバンプを
形成したが、バンプを形成する代わりに電極に対応する
部分に導電粒子を配置したり、配線基板側にバンプを形
成する方法を用いてもよい。あるいは、導電粒子が接着
シートより突き出た形状の異方性導電接着シートを用い
て接続をとってもよい。In this embodiment, the bumps are formed on the electrodes of the semiconductor element. However, instead of forming the bumps, conductive particles may be arranged in the portions corresponding to the electrodes, or the bumps may be formed on the wiring board side. Good. Alternatively, the connection may be made by using an anisotropic conductive adhesive sheet having conductive particles protruding from the adhesive sheet.
【００１９】次に、バンプ１２が形成された半導体素子
１１を加熱ヘッド３１に装着し、配線基板２１をステー
ジ３２にセッティングし、この配線基板２１上に熱可塑
性樹脂１３をポッテイングする。熱可塑性樹脂１３の量
は任意でよいが、高い信頼性を得ること、交換の容易さ
を考慮すると、図１（ｄ）で示したように、実装後半導
体素子の中央部のみに樹脂１３が広がる程度の量とする
ことが望ましい。Next, the semiconductor element 11 on which the bumps 12 are formed is mounted on the heating head 31, the wiring board 21 is set on the stage 32, and the thermoplastic resin 13 is potted on the wiring board 21. Although the amount of the thermoplastic resin 13 may be arbitrary, in consideration of obtaining high reliability and easy replacement, as shown in FIG. 1D, the resin 13 is provided only in the central portion of the semiconductor element after mounting. It is desirable that the amount is such that it spreads.
【００２０】熱可塑性樹脂１３の成分はポリエーテルイ
ミド、ポリフェニレンサルファイド、ポリブタジエン、
ポリエチレン、ポリエチレンサルファイド、ポリウレタ
ン、ポリスレレンなど１００℃前後で可塑性を示し、且
つ硬化後接着力の発揮される樹脂であれば任意でよい
が、ここではスチレンブタジエン樹脂を用いた。熱可塑
性樹脂１３はペースト、シート状など任意の状態でよい
が、ここではペースト状の樹脂をポッティングした。熱
可塑性樹脂以外でもガラス転位点（Ｔｇ）が低く１００
℃以下で軟化する樹脂であれば樹脂１３として用いるこ
とができる。たとえばＴｇが４３℃の編成アクリル系紫
外線硬化樹脂を用いた場合にも同様にリペアーができ
た。The components of the thermoplastic resin 13 are polyetherimide, polyphenylene sulfide, polybutadiene,
Any resin may be used, such as polyethylene, polyethylene sulfide, polyurethane, and polysurelen, as long as it exhibits plasticity at about 100 ° C. and exhibits adhesive strength after curing, but a styrene-butadiene resin is used here. The thermoplastic resin 13 may be in an arbitrary state such as a paste or sheet, but here, the paste resin is potted. The glass transition point (Tg) is low, even for thermoplastic resins other than 100.
A resin that can be softened at a temperature equal to or lower than 0 ° C. can be used as the resin 13. For example, even when a knitted acrylic UV curable resin having a Tg of 43 ° C. was used, the repair could be similarly performed.
【００２１】熱可塑性樹脂１３をポッティング後、半導
体素子１１と配線基板２１の位置合わせを行ない、半導
体素子１１を樹脂の可塑温度以上の１５０℃に加熱しな
がら圧接した。加圧力はチップ当り１０kgf とした。そ
の後樹脂を硬化させ、半導体素子と配線基板を接続し
た。After potting the thermoplastic resin 13, the semiconductor element 11 and the wiring board 21 were aligned with each other, and the semiconductor element 11 was pressure-welded while being heated to 150 ° C. which is higher than the plastic temperature of the resin. The pressure applied was 10 kgf per chip. After that, the resin was cured and the semiconductor element and the wiring board were connected.
【００２２】配線基板２１には、ガラス、セラミック、
ガラスエポキシ、金属コア基板、ポリイミド及びフェノ
ール基板などを用いることができ、配線パターン２２と
してはニッケル、銅、チタン、ＩＴＯ（インジウム・ス
ズ・オキサイド）、クロム、アルミニウム、モリブデ
ン、タンタル、タングステン、金、銀の単体、あるいは
これらの合金ないしは復合した金属材料を用いることが
できる。導体パターン２２の形成方法としては、スパッ
タ、蒸着、メッキ及び印刷などが用いられる。ここでは
配線基板材料として厚さ１．１ｍｍのガラス基板を用
い、配線パターン２２としてクロム０．３μｍ、金０．
２μｍを蒸着によって形成したものを用いた。 熱可塑
性樹脂１３を硬化させた段階では製品が高温になると樹
脂の信頼性が下がるので、製品の信頼性を向上させるた
めに、さらに熱可塑性樹脂１３を覆うように熱硬化性樹
脂１４をポッティングし、加熱により硬化させた。ここ
て熱硬化性樹脂１４はエポキシ樹脂、アクリル樹脂、フ
ェノール樹脂、シリコーン樹脂などが用いられるが、他
に光、あるいは常温硬化の樹脂を単独あるいは復合して
用いることもできる。またこれらの樹脂の中には酸化シ
リコン、炭化シリコン、酸化アルミニウムなどの粉体を
混入したものを用いると信頼性向上に好適である。この
様な熱硬化性樹脂１４を塗布し硬化させることによっ
て、熱可塑性樹脂１３が可塑化した場合でも半導体素子
と配線基板との接続は保たれる。The wiring board 21 is made of glass, ceramic,
A glass epoxy, a metal core substrate, a polyimide substrate, a phenol substrate, or the like can be used. As the wiring pattern 22, nickel, copper, titanium, ITO (indium tin oxide), chromium, aluminum, molybdenum, tantalum, tungsten, gold, It is possible to use a simple substance of silver, or an alloy or a metal material obtained by combining them. As a method of forming the conductor pattern 22, sputtering, vapor deposition, plating, printing, or the like is used. Here, a glass substrate having a thickness of 1.1 mm is used as the wiring substrate material, and the wiring pattern 22 is made of chromium 0.3 μm and gold 0.
A film having a thickness of 2 μm formed by vapor deposition was used. At the stage where the thermoplastic resin 13 is cured, the reliability of the resin decreases when the temperature of the product rises. Therefore, in order to improve the reliability of the product, the thermosetting resin 14 is potted so as to cover the thermoplastic resin 13 further. Cured by heating. Here, as the thermosetting resin 14, an epoxy resin, an acrylic resin, a phenol resin, a silicone resin, or the like is used, but it is also possible to use a light- or room-temperature-curing resin alone or in combination. In addition, it is suitable to improve reliability when a powder of silicon oxide, silicon carbide, aluminum oxide, or the like is mixed in these resins. By applying and curing such a thermosetting resin 14, the connection between the semiconductor element and the wiring board is maintained even when the thermoplastic resin 13 is plasticized.
【００２３】本実施例では熱硬化性エポキシ樹脂に粒径
１μｍ以下の酸化シリコン粉末５０重量部を含んだもの
を用意し、熱可塑性樹脂１３を覆うようにディスペンサ
で塗布し、８０℃２時間で硬化させた。樹脂は毛細管現
象によって半導体素子と配線基板の間にも含浸され熱可
塑性樹脂を覆うことができる。In this embodiment, a thermosetting epoxy resin containing 50 parts by weight of silicon oxide powder having a particle size of 1 μm or less is prepared and applied by a dispenser so as to cover the thermoplastic resin 13. Cured. The resin is also impregnated between the semiconductor element and the wiring substrate by the capillarity phenomenon so that the thermoplastic resin can be covered.
【００２４】以上詳述した実施例によって得られた半導
体装置において、半導体素子と配線基板との接続抵抗は
１バンプ当り平均で１００ミリΩであり、接続不良とな
るバンプはなかった。さらに、テストサンプルを作っ
て、−４０℃〜１００℃、各３０分ずつの熱衝撃試験を
行ったところ、１０００サイクル後の接続不良は発生し
なかった。また、７０℃、９０％Ｒ．Ｈ．の高温高湿放
置試験を行ったところ、１０００時間経過後も接続不良
の発生はなかった。In the semiconductor device obtained by the embodiment described in detail above, the connection resistance between the semiconductor element and the wiring board was 100 milliohms per bump on average, and there were no bumps causing connection failure. Furthermore, when a test sample was prepared and subjected to a thermal shock test at −40 ° C. to 100 ° C. for 30 minutes each, the connection failure did not occur after 1000 cycles. Also, 70 ° C., 90% R. H. When the high temperature and high humidity standing test was conducted, no connection failure occurred after 1000 hours.
【００２５】[0025]
【発明の効果】以上詳述したように、本発明によれば、
半導体素子を配線基板に実装する際に、熱可塑性樹脂を
介在させ、その樹脂の硬化によって半導体素子と配線基
板との接続とるので、半導体装置を樹脂の可塑温度以上
に加熱すると接着力が低下するため、検査結果等に基づ
き必要に応じて容易に半導体素子の交換ができる。さら
に接続の信頼性は熱硬化性樹脂によって一層強固なもの
となり信頼性の高い半導体装置を得ることができる。As described in detail above, according to the present invention,
When a semiconductor element is mounted on a wiring board, a thermoplastic resin is interposed and the semiconductor element and the wiring board are connected by hardening of the resin, so the adhesive strength decreases when the semiconductor device is heated above the plasticization temperature of the resin. Therefore, the semiconductor element can be easily replaced as needed based on the inspection result and the like. Further, the reliability of the connection is further strengthened by the thermosetting resin, and a highly reliable semiconductor device can be obtained.
【図１】本発明に係わる半導体装置の製造方法を説明す
るための概略図。FIG. 1 is a schematic diagram for explaining a method of manufacturing a semiconductor device according to the present invention.
【図２】従来の技術による半導体装置の製造方法を説明
するための概略図。FIG. 2 is a schematic diagram for explaining a method of manufacturing a semiconductor device according to a conventional technique.
【図３】従来の技術による半導体装置の製造方法を説明
するための概略図。FIG. 3 is a schematic diagram for explaining a method for manufacturing a semiconductor device according to a conventional technique.
１１ 半導体素子 １２ バンプ １３ 熱可塑性樹脂 １４ 熱硬化性樹脂 ２１ 配線基板 ２２ 配線パターン ３１ 加熱ヘッド ３２ ステージ 11 semiconductor element 12 bump 13 thermoplastic resin 14 thermosetting resin 21 wiring board 22 wiring pattern 31 heating head 32 stage
Claims (1)
ンで実装する半導体装置の製造方法において、前記半導
体素子と前記配線基板との間に熱可塑性樹脂を介在さ
せ、加熱および加圧により、前記半導体素子と前記配線
基板との電気的接続をとる工程と、前記半導体素子の動
作検査および半導体素子と配線基板との接続検査を行う
工程と、 前記検査工程により良品と判断された場合のみ少なくと
も前記半導体素子、前記配線基板の一部および前記熱可
塑性樹脂の露出部を熱硬化性樹脂で被覆し、加熱により
前記半導体素子を前記配線基板に固着させる工程を含む
ことを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which a semiconductor element is mounted face down on a wiring board, wherein a thermoplastic resin is interposed between the semiconductor element and the wiring board, and the semiconductor is heated and pressed. A step of electrically connecting the element and the wiring board, a step of performing an operation inspection of the semiconductor element and a connection inspection of the semiconductor element and the wiring board, and at least the semiconductor only when it is judged as a non-defective product by the inspection step. A method for manufacturing a semiconductor device, which comprises a step of coating an element, a part of the wiring board and an exposed portion of the thermoplastic resin with a thermosetting resin, and fixing the semiconductor element to the wiring board by heating. ..
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1927992A JPH05218137A (en) | 1992-02-05 | 1992-02-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1927992A JPH05218137A (en) | 1992-02-05 | 1992-02-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05218137A true JPH05218137A (en) | 1993-08-27 |
Family
ID=11995006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1927992A Pending JPH05218137A (en) | 1992-02-05 | 1992-02-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05218137A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09153516A (en) * | 1995-11-30 | 1997-06-10 | Sumitomo Bakelite Co Ltd | Semiconductor device and ic chip inspecting method |
| US5651179A (en) * | 1993-09-29 | 1997-07-29 | Matsushita Electric Industrial Co., Ltd. | Method for mounting a semiconductor device on a circuit board |
| JP2002538626A (en) * | 1999-03-03 | 2002-11-12 | インテル・コーポレーション | Controlled collapsed chip connection (C4) integrated circuit package with two different underfill materials |
| US6872635B2 (en) | 2001-04-11 | 2005-03-29 | Sony Corporation | Device transferring method, and device arraying method and image display unit fabricating method using the same |
| JP2008069291A (en) * | 2006-09-15 | 2008-03-27 | Shin Etsu Chem Co Ltd | Liquid epoxy resin composition for sealing semiconductor and semiconductor device |
| US7521797B2 (en) | 2004-03-18 | 2009-04-21 | Seiko Epson Corporation | Method of manufacturing substrate joint body, substrate joint body and electrooptical device |
| JP2009182244A (en) * | 2008-01-31 | 2009-08-13 | Sharp Corp | Method of manufacturing solar battery module |
| JP2011066231A (en) * | 2009-09-17 | 2011-03-31 | Sharp Corp | Solar battery module and method for manufacturing the same |
| WO2012132118A1 (en) * | 2011-03-30 | 2012-10-04 | シャープ株式会社 | Method for manufacturing solar battery cell with wiring board, and method for manufacturing solar battery module |
| CN113299593A (en) * | 2021-05-21 | 2021-08-24 | 錼创显示科技股份有限公司 | Adhesion layer structure and semiconductor structure |
| US11735461B2 (en) | 2021-05-21 | 2023-08-22 | PlayNitride Display Co., Ltd. | Adhesive-layer structure and semiconductor structure |
-
1992
- 1992-02-05 JP JP1927992A patent/JPH05218137A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5651179A (en) * | 1993-09-29 | 1997-07-29 | Matsushita Electric Industrial Co., Ltd. | Method for mounting a semiconductor device on a circuit board |
| US5670826A (en) * | 1993-09-29 | 1997-09-23 | Matsushita Electric Industrial Co., Ltd. | Method for mounting a semiconductor device on a circuit board using a conductive adhesive and a thermosetting resin, and a circuit board with a semiconductor device mounted thereon using the method |
| EP0645805B1 (en) * | 1993-09-29 | 2000-11-29 | Matsushita Electric Industrial Co., Ltd. | Method for mounting a semiconductor device on a circuit board, and a circuit board with a semiconductor device mounted thereon |
| JPH09153516A (en) * | 1995-11-30 | 1997-06-10 | Sumitomo Bakelite Co Ltd | Semiconductor device and ic chip inspecting method |
| JP2002538626A (en) * | 1999-03-03 | 2002-11-12 | インテル・コーポレーション | Controlled collapsed chip connection (C4) integrated circuit package with two different underfill materials |
| US6872635B2 (en) | 2001-04-11 | 2005-03-29 | Sony Corporation | Device transferring method, and device arraying method and image display unit fabricating method using the same |
| US7195687B2 (en) | 2001-04-11 | 2007-03-27 | Sony Corporation | Device transferring method, and device arraying method and image display unit fabricating method using the same |
| US7521797B2 (en) | 2004-03-18 | 2009-04-21 | Seiko Epson Corporation | Method of manufacturing substrate joint body, substrate joint body and electrooptical device |
| JP2008069291A (en) * | 2006-09-15 | 2008-03-27 | Shin Etsu Chem Co Ltd | Liquid epoxy resin composition for sealing semiconductor and semiconductor device |
| JP2009182244A (en) * | 2008-01-31 | 2009-08-13 | Sharp Corp | Method of manufacturing solar battery module |
| JP2011066231A (en) * | 2009-09-17 | 2011-03-31 | Sharp Corp | Solar battery module and method for manufacturing the same |
| WO2012132118A1 (en) * | 2011-03-30 | 2012-10-04 | シャープ株式会社 | Method for manufacturing solar battery cell with wiring board, and method for manufacturing solar battery module |
| JP2012209447A (en) * | 2011-03-30 | 2012-10-25 | Sharp Corp | Manufacturing method of solar cell with wiring board and manufacturing method of solar cell module |
| CN113299593A (en) * | 2021-05-21 | 2021-08-24 | 錼创显示科技股份有限公司 | Adhesion layer structure and semiconductor structure |
| CN113299593B (en) * | 2021-05-21 | 2023-01-10 | 錼创显示科技股份有限公司 | Adhesion layer structure and semiconductor structure |
| US11735461B2 (en) | 2021-05-21 | 2023-08-22 | PlayNitride Display Co., Ltd. | Adhesive-layer structure and semiconductor structure |
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