JPH05190545A - Formation of viahole - Google Patents
Formation of viaholeInfo
- Publication number
- JPH05190545A JPH05190545A JP4006097A JP609792A JPH05190545A JP H05190545 A JPH05190545 A JP H05190545A JP 4006097 A JP4006097 A JP 4006097A JP 609792 A JP609792 A JP 609792A JP H05190545 A JPH05190545 A JP H05190545A
- Authority
- JP
- Japan
- Prior art keywords
- via hole
- resin film
- resistant resin
- photosensitive heat
- viahole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は，感光性耐熱樹脂等の絶
縁樹脂膜に導体回路を形成し, 多層化して薄膜多層回路
を形成する場合の, 絶縁樹脂膜相互の上下の配線パター
ンとの導通をとるためのビアホールの形成方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring pattern above and below insulating resin films when a conductive circuit is formed on an insulating resin film such as a photosensitive heat-resistant resin to form a thin film multilayer circuit. The present invention relates to a method for forming a via hole for establishing conduction.
【０００２】更に詳しくは，そのビアホールが, 蒸着や
スパッタリングによる配線導体膜の形成が有利なよう
に，正のテーパーを付けたビアホールの形成方法に関す
る。近年，電子機器の小型化，高速化に伴い，部品を搭
載するプリント配線基板の高密度化が進んでいる。その
中で，高密度化，高速化に有利な薄膜多層回路基板が注
目されている。More specifically, the present invention relates to a method of forming a via hole having a positive taper so that the formation of a wiring conductor film by vapor deposition or sputtering is advantageous. In recent years, as electronic devices have become smaller and faster, the density of printed wiring boards on which components are mounted has been increasing. Among them, thin-film multilayer circuit boards, which are advantageous for high density and high speed, are drawing attention.
【０００３】薄膜多層回路は，絶縁層と配線導体層とを
交互に形成し，絶縁層にはビアホールを設けて，ビアホ
ールの壁面を導体物質で覆うことによって，上下の配線
導体層間を電気的に接続している。In a thin film multilayer circuit, insulating layers and wiring conductor layers are alternately formed, via holes are provided in the insulating layer, and the wall surface of the via holes is covered with a conductor material to electrically connect the upper and lower wiring conductor layers. Connected.
【０００４】ビアホール側壁の導体層の形成方法は，一
般に，蒸着やスパッタリングにより金属膜を形成する乾
式方法が用いられている。そのため，ビアホール側壁に
欠陥のない均一な金属膜を被覆させるためには，その形
状は絶縁層の上面の開口が，下面の開口より大きい正の
テーパー形状を持ったものとする必要がある。As a method of forming the conductor layer on the side wall of the via hole, a dry method of forming a metal film by vapor deposition or sputtering is generally used. Therefore, in order to cover the side wall of the via hole with a uniform metal film having no defects, it is necessary that the opening on the upper surface of the insulating layer has a positive taper shape larger than the opening on the lower surface.
【０００５】[0005]
【従来の技術】図５は従来例の説明図である。図におい
て，13は層間絶縁層, 14はビアホール, 15は配線導体
層, 16は下層絶縁層の配線導体層, 17は下層絶縁層, 18
は断線部分, 19は薄い部分である。2. Description of the Related Art FIG. 5 is an explanatory view of a conventional example. In the figure, 13 is an interlayer insulating layer, 14 is a via hole, 15 is a wiring conductor layer, 16 is a wiring conductor layer of a lower insulating layer, 17 is a lower insulating layer, 18
Is a broken part and 19 is a thin part.
【０００６】従来，薄膜多層絶縁基板の個々の層間絶縁
層にビアホールを形成する場合，ビアホールを開口しよ
うとする所定の部分に光が透過しないように遮蔽したマ
スクを, 層間絶縁層となる感光性耐熱樹脂膜の上に載
せ，紫外線などで露光する。その後，溶媒により現像す
ることにより，マスクのパターンに従って露光された部
分の樹脂膜だけを残し，露光されない部分はエッチング
されて, 層間絶縁層にビアホールが形成される。Conventionally, when a via hole is formed in each interlayer insulating layer of a thin film multi-layer insulating substrate, a mask that shields light from passing through a predetermined portion where the via hole is to be opened is provided with a photosensitive layer that serves as an interlayer insulating layer. Place it on a heat-resistant resin film and expose it with ultraviolet rays. After that, by developing with a solvent, only the resin film of the exposed portion is left according to the mask pattern, and the unexposed portion is etched to form a via hole in the interlayer insulating layer.
【０００７】図５は層間絶縁層13に開けた種々の形状の
ビアホール14の断面図を示している。図５（ａ）に示し
たものは，基板側の下層絶縁層17の上面に, 下層絶縁層
の配線導体層16を形成し，その上に被着された層間絶縁
層13に開けられたビアホール14が，層間絶縁層13の上面
の開口より下面の開口が小さい正テーパー形状となって
いる。このようなビアホール14に被着された配線導体層
15は，ビアホール14の側壁を覆って下層絶縁層の配線導
体層16に接続されるようになる。FIG. 5 shows sectional views of various shapes of via holes 14 formed in the interlayer insulating layer 13. 5A shows a via hole formed in the interlayer insulating layer 13 formed by forming the wiring conductor layer 16 of the lower insulating layer on the upper surface of the lower insulating layer 17 on the substrate side. Reference numeral 14 has a positive taper shape in which the opening on the lower surface is smaller than the opening on the upper surface of the interlayer insulating layer 13. A wiring conductor layer deposited on such a via hole 14
15 covers the side wall of the via hole 14 and is connected to the wiring conductor layer 16 of the lower insulating layer.
【０００８】一方, 図５（ｂ）に示したものは, 層間絶
縁層13に形成されたビアホール14が, 層間絶縁層13の上
面の開口より下面の開口が大きい逆テーパー形状となっ
ている。そのため, 層間絶縁層13上に被着された配線導
体層15が，ビアホール14の側壁に被着され難く，従っ
て, 下層絶縁層の配線導体層16との間に断線部分18等を
生じて, 電気的に接続され難くなる。On the other hand, in the structure shown in FIG. 5B, the via hole 14 formed in the interlayer insulating layer 13 has an inverse taper shape in which the opening on the lower surface is larger than the opening on the upper surface of the interlayer insulating layer 13. Therefore, the wiring conductor layer 15 deposited on the interlayer insulating layer 13 is hard to be deposited on the side wall of the via hole 14, and therefore, a disconnection portion 18 or the like is generated between the wiring conductor layer 16 of the lower insulating layer, It becomes difficult to be electrically connected.
【０００９】また, 図５（ｃ）に示したものは, 層間絶
縁層13に形成されたビアホール14が, 層間絶縁層14の上
面の開口と下面の開口とがほぼ等しい垂直形状であり，
ビアホール14の側壁に被着される配線導体層15は，図５
（ｂ）に示した配線導体層15よりは被着され易くなる
が, 図５（ａ）に示した配線導体層15に比較して薄い部
分19が生ずる。従って, 下層絶縁層の配線導体層16に対
する接続が電気的に十分でないことがある。In addition, as shown in FIG. 5C, the via hole 14 formed in the interlayer insulating layer 13 has a vertical shape in which the opening on the upper surface and the opening on the lower surface of the interlayer insulating layer 14 are substantially the same.
The wiring conductor layer 15 deposited on the sidewall of the via hole 14 is shown in FIG.
Although it is easier to be deposited than the wiring conductor layer 15 shown in FIG. 5B, a thinner portion 19 is produced as compared with the wiring conductor layer 15 shown in FIG. Therefore, the connection of the lower insulating layer to the wiring conductor layer 16 may not be electrically sufficient.
【００１０】[0010]
【発明が解決しようとする課題】従って，層間絶縁層13
に開けたビアホール14が, 図５（ｂ）や図５（ｃ）のよ
うな形状の場合には，配線導体層15が均一に被着されな
いため，電気的接続が不十分となる問題があった。Therefore, the interlayer insulating layer 13
In the case where the via hole 14 opened in the opening has a shape as shown in FIGS. 5B and 5C, the wiring conductor layer 15 is not evenly deposited, which causes a problem that electrical connection becomes insufficient. It was
【００１１】そのため, 本発明は, 以上の点を鑑みて，
図５（ａ）に示すような，配線導体層15がビアホール14
の側壁にも, 均一に被着し易い正テーパー形状を持った
ビアホール14の形成方法を提供することを目的とする。Therefore, the present invention has been made in view of the above points.
As shown in FIG. 5A, the wiring conductor layer 15 has a via hole 14
It is an object of the present invention to provide a method for forming a via hole 14 having a positive taper shape that is easily and uniformly deposited on the side wall of the via hole.
【００１２】[0012]
【課題を解決するための手段】図１は本発明の原理説明
図である。図において，１は基板, ２は感光性耐熱樹脂
膜，３はガラスマスク，４は開口パターン，５はマスク
パターン, ６は紫外線，７はビアホール，８は底部，９
は上縁，10は傾斜部分である。FIG. 1 illustrates the principle of the present invention. In the figure, 1 is a substrate, 2 is a photosensitive heat resistant resin film, 3 is a glass mask, 4 is an opening pattern, 5 is a mask pattern, 6 is ultraviolet rays, 7 is a via hole, 8 is a bottom part, 9
Is the upper edge and 10 is the inclined part.
【００１３】基板１上の感光性耐熱樹脂膜２の紫外線露
光用に用いるガラスマスク３は，ビアホール７の底部８
に相当する開口部には，開口パターン４が描かれ，その
周縁に，ビアホール７の傾斜部分10に相当するマスクパ
ターン５として，感光性耐熱樹脂膜２の解像度の限界以
下の細い線を間隔を変えて描く等の方法で，マスクパタ
ーン５の濃淡をディジタル的に表現したものを使用す
る。The glass mask 3 used for exposing the photosensitive heat-resistant resin film 2 on the substrate 1 to ultraviolet rays has a bottom portion 8 of the via hole 7.
An opening pattern 4 is drawn in the opening corresponding to, and a thin line below the resolution limit of the photosensitive heat-resistant resin film 2 is provided as a mask pattern 5 corresponding to the inclined portion 10 of the via hole 7 on the periphery thereof. By using a method such as changing and drawing, a digital representation of the light and shade of the mask pattern 5 is used.
【００１４】そして，感光性耐熱樹脂膜２を紫外線６に
より照射した後，現像エッチングすると，図１（ｂ）に
示すように，正テーパー形状を有するビアホール７が形
成できる。Then, the photosensitive heat-resistant resin film 2 is irradiated with ultraviolet rays 6 and then development etching is performed, whereby a via hole 7 having a positive taper shape can be formed as shown in FIG. 1B.
【００１５】即ち，本発明の目的は，基板１上のネガ型
の薄膜回路用感光性耐熱性樹脂膜２への正テーパー付き
ビアホール７の形成において，図１（ａ）に示すよう
に，該感光性耐熱樹脂膜２の露光時に，該ビアホール７
の底部８の最小径の部分は, 完全に遮光した開口パター
ン４を有し，該ビアホール７の上縁９までの側壁の傾斜
部分10は，露光量が徐々に増加するマスクパターン５を
有するガラスマスク３を使用することにより，図２
（ａ）に示すように，前記ガラスマスク３の前記ビアホ
ール７の傾斜部分10を露光する前記マクスクパターン５
が, 複数の細い線11の間隔を密から疎に形成されてお
り, 更に, この細い線11は, 該感光性耐熱樹脂膜２の解
像度以下の幅であることにより，図３に示すように，前
記ガラスマスク３の前記ビアホール７の傾斜部分10を露
光する前記マクスクパターン５が, 該感光性耐熱樹脂膜
２の解像度以下の複数の点12を密から疎に形成されてい
ることにより,また，図１（ａ）の逆パターンとして，
ポジ型の該感光性耐熱樹脂膜２の露光時に，該ビアホー
ル７の底部８の最小径の部分は, 完全に光が透過する開
口パターン４を有し，該ビアホール７の上縁９までの側
壁の傾斜部分10は，露光量が徐々に減少するマスクパタ
ーン５を有するガラスマスク３を使用することにより達
成される。That is, an object of the present invention is to form a positive tapered via hole 7 in a negative type photosensitive resin film 2 for a thin film circuit on a substrate 1 as shown in FIG. When the photosensitive heat resistant resin film 2 is exposed, the via hole 7
The minimum diameter portion of the bottom portion 8 of the glass has an opening pattern 4 which is completely shielded from light, and the inclined portion 10 of the side wall to the upper edge 9 of the via hole 7 has a mask pattern 5 in which the exposure amount gradually increases. By using the mask 3, FIG.
As shown in (a), the mask pattern 5 for exposing the inclined portion 10 of the via hole 7 of the glass mask 3 is exposed.
However, the plurality of thin lines 11 are formed with a dense to sparse spacing, and the thin lines 11 have a width less than the resolution of the photosensitive heat-resistant resin film 2 as shown in FIG. Since the Maxk pattern 5 for exposing the inclined portion 10 of the via hole 7 of the glass mask 3 is formed with a plurality of points 12 below the resolution of the photosensitive heat resistant resin film 2 densely and sparsely, In addition, as an inverse pattern of FIG.
At the time of exposing the positive photosensitive heat-resistant resin film 2, the minimum diameter portion of the bottom 8 of the via hole 7 has an opening pattern 4 through which light is completely transmitted, and the side wall up to the upper edge 9 of the via hole 7. The sloping portion 10 is achieved by using a glass mask 3 having a mask pattern 5 whose exposure dose is gradually reduced.
【００１６】[0016]
【作用】本発明では，上記のように，ビアホール形成用
マスクパターンのビアホール側壁の傾斜部分に細い線，
或いは，小さい点を密から疎に描いたマスクを用いてい
るため，ネガ型の感光性耐熱樹脂膜はその部分が露光量
が次第に増加して露光される。In the present invention, as described above, a thin line is formed on the inclined portion of the side wall of the via hole of the via hole forming mask pattern,
Alternatively, since a mask in which small points are drawn densely and sparsely is used, the negative photosensitive heat-resistant resin film is exposed with the exposure amount gradually increasing.
【００１７】即ち，感光性耐熱樹脂膜は，半導体装置の
製造に用いられる一般のフォトレジスト膜（感光性樹脂
膜）に比べて，解像力が低いため，２μｍ程度の線も点
も感光性耐熱樹脂膜の解像度の限界以下であるため，ビ
アホールの側壁部分での露光量が平均化されて，あたか
も透過量の異なるマスクを使用した場合と同等の効果が
得られる。That is, since the photosensitive heat-resistant resin film has a lower resolution than a general photoresist film (photosensitive resin film) used for manufacturing a semiconductor device, lines and dots of about 2 μm are also formed on the photosensitive heat-resistant resin film. Since the film resolution is below the limit, the exposure dose on the side wall of the via hole is averaged, and the same effect as when using a mask having a different transmission amount is obtained.
【００１８】このため，線が密なところは露光量が少な
く，感光性耐熱樹脂膜の硬化が進んでいないため現像で
エッチングされやすいが，線が疎の部分はそれより硬化
が進んでいるため現像でエッチングされ難くなる。For this reason, since the exposure amount is small where the lines are dense and the photosensitive heat-resistant resin film has not been hardened yet, it is easily etched during development, but the part where the lines are sparse is hardened more than that. Difficult to be etched during development.
【００１９】従って，感光性耐熱樹脂膜の上面（上縁）
から下面（底部）にかけて，現像エッチングレートが異
なってくるため，図１のような正のテーパー形状を持っ
たビアホールが形成される。Therefore, the upper surface (upper edge) of the photosensitive heat-resistant resin film
Since the development etching rate varies from the bottom surface to the bottom surface, a via hole having a positive taper shape as shown in FIG. 1 is formed.
【００２０】[0020]
【実施例】図２は本発明の第１の実施例の説明図であ
る。図において，１は基板，２は感光性耐熱樹脂膜，３
はガラスマスク，４は開口パターン，５はマスクパター
ン, ６は紫外線，７はビアホール，８は底部，９は上
縁，10は傾斜部分，11は細い線, 12は点である。FIG. 2 is an explanatory diagram of the first embodiment of the present invention. In the figure, 1 is a substrate, 2 is a photosensitive heat-resistant resin film, 3
Is a glass mask, 4 is an opening pattern, 5 is a mask pattern, 6 is ultraviolet rays, 7 is a via hole, 8 is a bottom portion, 9 is an upper edge, 10 is an inclined portion, 11 is a thin line, and 12 is a dot.
【００２１】図２（ａ）に示すように，ネガ型の感光性
耐熱樹脂膜２として使用する東レ製の感光性ポリイミド
前駆体ワニス（不揮発分18重量％）「フォトニース」
を, 前処理洗浄を施したSiウエハ等の基板１上に15μｍ
の厚さにスピンコートし, 110℃で１時間のプリベーク
を行う。As shown in FIG. 2 (a), a photosensitive polyimide precursor varnish (nonvolatile content: 18% by weight) made by Toray Co., Ltd. for use as a negative photosensitive heat resistant resin film "photonice"
15 μm on a substrate 1 such as a Si wafer that has been pretreated and washed.
Spin-coated to a thickness of 1 and prebaked at 110 ° C for 1 hour.
【００２２】この感光性耐熱樹脂膜２の上に本発明の図
２（ａ）に示したように，20μｍΦの丸パターン（ビア
ホールの底分に相当）の周縁に，本発明の線幅が２μｍ
で間隔が２μｍと３μｍの同心円状の細い線10のマスク
パターン５が形成されたガラスマスク３をセットし，波
長 356nmの紫外線を露光量 250mJ／cm2 で照射する。As shown in FIG. 2 (a) of the present invention, the line width of the present invention is 2 μm on the periphery of a circular pattern of 20 μmΦ (corresponding to the bottom of the via hole) as shown in FIG. 2 (a) of the present invention.
Then, the glass mask 3 on which the mask pattern 5 of the thin concentric lines 10 having the intervals of 2 μm and 3 μm is formed is set, and the ultraviolet ray having the wavelength of 356 nm is irradiated with the exposure amount of 250 mJ / cm 2 .
【００２３】次に, Ｎ−メチル』ピロリドンで感光性耐
熱樹脂膜２を超音波現像し，エチルアルコールによるリ
ンス洗浄を行った後，350 ℃で１時間の熱処理を行っ
た。熱処理の後，ビアホール７の断面を観察すると，図
２（ｂ）に示すように，15μｍの厚さの感光性耐熱樹脂
膜２に形成されたビアホール７の底部８は20μｍ径に開
口され, 上縁９は38μｍの正テーパー形状のビアホール
７が得られた。Next, the photosensitive heat-resistant resin film 2 was ultrasonically developed with N-methyl "pyrrolidone, rinsed with ethyl alcohol, and then heat-treated at 350 ° C. for 1 hour. When the cross section of the via hole 7 is observed after the heat treatment, as shown in FIG. 2B, the bottom portion 8 of the via hole 7 formed in the photosensitive heat resistant resin film 2 having a thickness of 15 μm is opened to a diameter of 20 μm. At the edge 9, a via hole 7 having a positive taper shape of 38 μm was obtained.
【００２４】比較のために, 従来の20μｍ径のマスクパ
ターン４のみを有するガラスマスク３を用いて露光した
ものは, 図２（ｃ）に示すように，ビアホール７の底部
８が20μｍ径で，上縁９が28μｍ径の太鼓型のスルーホ
ールとなり，配線形成に適しないものであった。For comparison, the one exposed by using the conventional glass mask 3 having only the mask pattern 4 having a diameter of 20 μm has a bottom 8 of the via hole 7 having a diameter of 20 μm as shown in FIG. 2 (c). The upper edge 9 was a drum-shaped through hole with a diameter of 28 μm, which was not suitable for wiring formation.
【００２５】また, 本発明の第２の実施例として，ビア
ホール７の傾斜部分10に解像力以下の点12でマスクパタ
ーン５を構成したものや，第３の実施例として，ビアホ
ール７の底部８の開口パターン４はガラスマスク３の下
面に形成し，ビアホール７の側壁の傾斜部分10のマスク
パターン５はガラスマスク３の上面に形成して，焦点ず
れによる紫外線６の露光量の減少を狙ったマスクを使用
する。In addition, as a second embodiment of the present invention, the mask pattern 5 is formed on the inclined portion 10 of the via hole 7 at the point 12 below the resolving power, and as the third embodiment, the bottom portion 8 of the via hole 7 is formed. The opening pattern 4 is formed on the lower surface of the glass mask 3, and the mask pattern 5 on the inclined portion 10 of the side wall of the via hole 7 is formed on the upper surface of the glass mask 3 to reduce the exposure amount of the ultraviolet rays 6 due to defocus. To use.
【００２６】いずれのガラスマスク３を利用した場合で
も，第１の実施例と同様に，図２（ｂ）のような正テー
パー形状のビアホール７が得られた。一方，本発明の第
４の実施例として，ポジ型の感光性耐熱樹脂膜２を用い
れば，本発明の第１〜第３の実施例で説明したガラスマ
スク３の逆のパターンが使用できる。No matter which glass mask 3 was used, a positive taper-shaped via hole 7 as shown in FIG. 2B was obtained as in the first embodiment. On the other hand, if the positive photosensitive heat-resistant resin film 2 is used as the fourth embodiment of the present invention, the reverse pattern of the glass mask 3 described in the first to third embodiments of the present invention can be used.
【００２７】更に，ガラスマスク３上にマスクパターン
を形成するクロム膜やクロム酸化膜等の厚さを段階的に
薄く調節して，光を徐々に透過する厚さを変えれば，写
真乾板やガラスフィルターと同様に徐々に光の露光量を
減少でき，本発明のマスクとして用いることが可能とな
る。Further, if the thickness of the chrome film or the chrome oxide film forming the mask pattern on the glass mask 3 is adjusted to be small in steps, and the thickness that allows light to be transmitted gradually is changed, a photographic plate or a glass plate can be obtained. Like the filter, the exposure amount of light can be gradually reduced, and the mask can be used in the present invention.
【００２８】[0028]
【発明の効果】本発明によれば，以上説明したように，
露光用のマスクパターンとして，ビアホールの側壁の傾
斜部分に相当するマスクパターンを内側から外側に順
次，露光量を増加したり，減衰したりするパターンにす
るので，ビアホールの側壁の傾斜部分を正テーバーに制
御良く形成でき，このようなビアホールを有する急きそ
う板を用いれば，配線の故障が大幅に改善され, 配線板
の品質が向上し, 信頼性の向上に寄与するところが大き
い。According to the present invention, as described above,
As a mask pattern for exposure, a mask pattern corresponding to the inclined portion of the side wall of the via hole is formed into a pattern that sequentially increases or decreases the exposure amount from the inner side to the outer side. By using a rush board that can be formed with good controllability and has such a via hole, the failure of the wiring can be greatly improved, the quality of the wiring board can be improved, and the reliability can be improved.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明の第１の実施例の説明図FIG. 2 is an explanatory diagram of the first embodiment of the present invention.
【図３】 本発明の第２の実施例の説明図FIG. 3 is an explanatory diagram of a second embodiment of the present invention.
【図４】 本発明の第３の実施例の説明図FIG. 4 is an explanatory diagram of a third embodiment of the present invention.
【図５】 従来例の説明図FIG. 5 is an explanatory diagram of a conventional example.
１ 基板 ２ 感光性耐熱樹脂膜 ３ ガラスマスク ４ 開口パターン ５ マスクパターン ６ 紫外線 ７ ビアホール ８ 底部 ９ 上縁 10 傾斜部分 11 細い線 12 点 1 Substrate 2 Photosensitive Heat-Resistant Resin Film 3 Glass Mask 4 Opening Pattern 5 Mask Pattern 6 Ultraviolet Ray 7 Via Hole 8 Bottom 9 Upper Edge 10 Slope 11 Thin Line 12 Points
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/90 Ｂ 7735−4Ｍ 7352−4Ｍ Ｈ０１Ｌ 21/30 ３６１ Ｖ (72)発明者 宮原 昭一 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication location H01L 21/90 B 7735-4M 7352-4M H01L 21/30 361 V (72) Inventor Shoichi Miyahara Kanagawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki, Japan
Claims (5)
脂膜(2) への正テーパー付きビアホール(7) の形成にお
いて， 該感光性耐熱樹脂膜(2) の露光時に，該ビアホール(7)
の底部(8) の最小径の部分は, 完全に遮光した開口パタ
ーン(4) を有し，該ビアホール(7) の上縁(9)までの側
壁の傾斜部分(10)は，露光量が徐々に増加するマスクパ
ターン(5) を有するガラスマスク(3) を使用することを
特徴とするビアホール形成方法。1. A method for forming a positively tapered via hole (7) in a photosensitive heat-resistant resin film (2) for a thin film circuit on a substrate (1), wherein when the photosensitive heat-resistant resin film (2) is exposed, Beer hall (7)
The minimum diameter part of the bottom part (8) of the bottom has an opening pattern (4) completely shielded from light, and the sloped part (10) of the side wall up to the upper edge (9) of the via hole (7) is exposed to light. A method of forming a via hole, characterized in that a glass mask (3) having a gradually increasing mask pattern (5) is used.
光する前記マクスクパターン(5) が, 複数の細い線(11)
の間隔を密から疎に形成されていることを特徴とする請
求項１記載のビアホール形成方法。2. The mask pattern (5) exposing the inclined portion (10) of the via hole (7) comprises a plurality of thin lines (11).
The via hole forming method according to claim 1, wherein the intervals are formed from dense to sparse.
は, 該感光性耐熱樹脂膜(2) の解像度以下の幅であるこ
とを特徴とする請求項２記載のビアホール形成方法。3. Thin lines (11) of the mask pattern (5)
3. The via hole forming method according to claim 2, wherein the width is less than the resolution of the photosensitive heat resistant resin film (2).
光する前記マクスクパターン(5) が, 該感光性耐熱樹脂
膜(2) の解像度以下の複数の点(12)を密から疎に形成さ
れていることを特徴とする請求項１記載のビアホール形
成方法。4. The mask pattern (5) for exposing the inclined portion (10) of the via hole (7) closely covers a plurality of points (12) below the resolution of the photosensitive heat-resistant resin film (2). The via hole forming method according to claim 1, wherein the via holes are formed sparsely.
脂膜(2) への正テーパー付きビアホール(7) の形成にお
いて， 該感光性耐熱樹脂膜(2) の露光時に，該ビアホール(7)
の底部(8) の最小径の部分は, 完全に光が透過する開口
パターン(4) を有し，該ビアホール(7) の上縁(9) まで
の側壁の傾斜部分(10)は，露光量が徐々に減少するマス
クパターン(5)を有するガラスマスク(3) を使用するこ
とを特徴とするビアホール形成方法。5. Forming a positively tapered via hole (7) in a photosensitive heat-resistant resin film (2) for a thin film circuit on a substrate (1), when exposing the photosensitive heat-resistant resin film (2), Beer hall (7)
The minimum diameter part of the bottom (8) of the via has an aperture pattern (4) that allows complete light transmission, and the sloped part (10) of the side wall to the upper edge (9) of the via hole (7) is exposed. A method for forming a via hole, which comprises using a glass mask (3) having a mask pattern (5) whose amount is gradually reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4006097A JPH05190545A (en) | 1992-01-17 | 1992-01-17 | Formation of viahole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4006097A JPH05190545A (en) | 1992-01-17 | 1992-01-17 | Formation of viahole |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05190545A true JPH05190545A (en) | 1993-07-30 |
Family
ID=11629009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4006097A Withdrawn JPH05190545A (en) | 1992-01-17 | 1992-01-17 | Formation of viahole |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05190545A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003100744A (en) * | 2001-09-21 | 2003-04-04 | Ricoh Co Ltd | Semiconductor device and method of manufacturing the same |
| US6655024B2 (en) | 2001-05-28 | 2003-12-02 | Murata Manufacturing Co., Ltd. | Method of manufacturing a circuit board |
-
1992
- 1992-01-17 JP JP4006097A patent/JPH05190545A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6655024B2 (en) | 2001-05-28 | 2003-12-02 | Murata Manufacturing Co., Ltd. | Method of manufacturing a circuit board |
| JP2003100744A (en) * | 2001-09-21 | 2003-04-04 | Ricoh Co Ltd | Semiconductor device and method of manufacturing the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990408 |