JPH05184134A - Gate circuit for gto - Google Patents
Gate circuit for gtoInfo
- Publication number
- JPH05184134A JPH05184134A JP36006591A JP36006591A JPH05184134A JP H05184134 A JPH05184134 A JP H05184134A JP 36006591 A JP36006591 A JP 36006591A JP 36006591 A JP36006591 A JP 36006591A JP H05184134 A JPH05184134 A JP H05184134A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- circuit
- gto
- cathode
- switching element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Landscapes
- Power Conversion In General (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＧＴＯのゲート回路に係
り、ＧＴＯのゲート、カソード間が短絡故障した場合の
ゲート回路の保護に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GTO gate circuit, and more particularly to protection of the gate circuit when a short circuit occurs between the gate and cathode of the GTO.
【従来の技術】一般に、ＧＴＯのゲート回路はゲートタ
ーンオフ時のゲートドライブ、順阻止期間中のゲート負
バイアスという２つの機能を有し、前者では高di／dt、
高ピーク値の電流出力を得るため、後者ではＧＴＯの誤
点弧を引き起こさないためにいずれの機能においても回
路を極力低インピーダンスとした方が良い。したがっ
て、オフゲート回路の実現に際しては、回路にインピー
ダンス素子を挿入しない構成が広く用いられている。図
４は従来の一般的なオフゲート回路の基本構成図で、タ
ーンゲートドライブ機能とゲート負バイアス機能を共用
した最も簡単な構成である。図４において、制御信号Ｓ
ＣはＧＴＯ３のオフゲート指令時にハイレベル、オンゲ
ート指令時にローレベルとし、スイッチング素子１は制
御信号ＳＣがハイレベルでオン、ローレベルでオフとす
る。スイッチング素子１をオンさせることにより直流電
源２の電圧をＧＴＯ３のカソードに対しゲートが負極性
となるよう印加し、ターンオフゲートドライブ及びゲー
ト負バイアスの機能として動作する。この動作を図５に
より説明する。図５はＧＴＯターンオフ時の回路動作波
形を示し、時刻 t0 でスイッチング素子１をオンさせる
と、ゲートターンオフ動作が始まり、ＧＴＯ３のターン
オフ時間T1を経過後時刻t1からゲート負バイアス状態と
なる。2. Description of the Related Art Generally, a GTO gate circuit has two functions of a gate drive at the time of gate turn-off and a gate negative bias during a forward blocking period.
In order to obtain a high peak current output, in the latter case, it is better to make the circuit as low impedance as possible in any function so as not to cause false firing of the GTO. Therefore, when implementing an off-gate circuit, a configuration in which no impedance element is inserted into the circuit is widely used. FIG. 4 is a basic configuration diagram of a conventional general off-gate circuit, which is the simplest configuration sharing a turn gate drive function and a gate negative bias function. In FIG. 4, the control signal S
C is set to a high level when the GTO 3 has an off-gate command and is set to a low level when the on-gate command is given, and the switching element 1 is turned on when the control signal SC is high level and turned off when the control signal SC is low level. When the switching element 1 is turned on, the voltage of the DC power supply 2 is applied to the cathode of the GTO 3 so that the gate has a negative polarity, and it operates as a function of a turn-off gate drive and a gate negative bias. This operation will be described with reference to FIG. FIG. 5 shows the circuit operation waveform at the time of GTO turn-off. When the switching element 1 is turned on at time t 0 , the gate turn-off operation starts, and after the turn-off time T 1 of GTO 3 elapses, the gate becomes negatively biased from time t 1. ..
【０００２】[0002]
【発明が解決しようとする課題】しかしながら、かよう
なオフゲート回路構成では、ＧＴＯ３のゲート、カソー
ド間短絡故障が発生した場合に直流電源２がスイッチン
グ素子１を通じて連続的に短絡状態となるため、オフゲ
ート回路構成部品が破損するという欠点がある。本発明
は上述した点に鑑みて創案されたもので、その目的とす
るところは、ＧＴＯのゲート、カソード間短絡故障に伴
って２次的に発生するオフゲート回路構成部品の破損を
防止できるＧＴＯのゲート回路を提供することにある。However, in such an off-gate circuit configuration, the DC power supply 2 is continuously short-circuited through the switching element 1 when a short-circuit fault between the gate and the cathode of the GTO 3 occurs, so that the off-gate circuit is formed. It has the drawback of damaging circuit components. The present invention has been made in view of the above points, and an object of the present invention is to prevent damage to the off-gate circuit component that is secondarily generated due to a short circuit between the gate and the cathode of the GTO. It is to provide a gate circuit.
【０００３】[0003]
【課題を解決するための手段】つまり、その目的を達成
する為の手段は、直流電源とスイッチング素子とＧＴＯ
のゲート、カソードが直列に接続されたオフゲート回路
を有するＧＴＯのゲート回路において、前記スイッチン
グ素子を駆動せしめる制御回路と、前記ＧＴＯのゲー
ト、カソード間電圧を検出する電圧検出回路とを設け、
この電圧検出回路の検出した前記ＧＴＯのゲート、カソ
ード間電圧レベルに応動して、前記スイッチング素子を
前記制御回路によってスイッチオフさせるようにしたこ
とにある回路。[Means for Solving the Problems] That is, means for achieving the object are a DC power supply, a switching element, and a GTO.
A gate circuit of the GTO having an off-gate circuit in which the gate and the cathode are connected in series, a control circuit for driving the switching element, and a voltage detection circuit for detecting the voltage between the gate and the cathode of the GTO are provided.
A circuit in which the control circuit switches off the switching element in response to the voltage level between the gate and cathode of the GTO detected by the voltage detection circuit.
【０００４】[0004]
【作用】その作用は、電圧検出回路５において、ゲー
ト、カソード間逆電圧− VGKが所定の値以下であると電
圧レベル判別信号７がオフとなる。一方、図５のゲー
ト、カソード間電圧ＶGK波形でＧＴＯ３のターンオフ時
間T1の間はゲート、カソード間が低インピーダンスであ
り、ほぼ短絡状態のため短絡故障時との区別は困難であ
る。したがって、スイッチング素子の制御回路４におい
ては、制御信号ＳＣがハイレベルとなってから所定の時
間（少なくともT1の時間）までは電圧レベル判別信号７
に無関係にスイッチング素子１をオンさせ、前記所定の
時間経過後、制御信号ＳＣがハイレベルかつ電圧レベル
判別信号７がオフという条件が成立の場合は短絡故障と
判断し、スイッチング素子１をオフさせる。以下、本発
明の一実施例を、図面に基づいて詳述する。[Action] Its action is, in the voltage detection circuit 5, a gate, cathode reverse voltage - the V GK is less than a predetermined value the voltage level discrimination signal 7 is turned off. On the other hand, in the voltage V GK waveform between the gate and the cathode in FIG. 5, the impedance between the gate and the cathode is low during the turn-off time T 1 of the GTO 3, and it is difficult to distinguish it from a short-circuit failure because it is in a short circuit state. Therefore, in the control circuit 4 of the switching element, the voltage level determination signal 7 is kept for a predetermined time (at least the time T 1 ) after the control signal SC becomes high level.
Irrespective of the above, the switching element 1 is turned on, and if the condition that the control signal SC is at the high level and the voltage level determination signal 7 is off after the lapse of the predetermined time, it is determined that a short circuit failure has occurred and the switching element 1 is turned off. .. An embodiment of the present invention will be described in detail below with reference to the drawings.
【０００５】[0005]
【実施例】図１は本発明の一実施例を示すオフゲート回
路の基本構成図で、図４の構成に電圧検出回路５および
スイッチング素子の制御回路４を付加したものである。
図１において、電圧検出回路５はＧＴＯ３のゲート、カ
ソード間逆電圧− VGKを検出し、レベル判別を行うこと
で、電圧レベル判別信号７を得る。スイッチング素子の
制御回路４は、制御信号ＳＣと電圧レベル判別信号７の
２つの入力信号を用いて所定の論理演算を行うことによ
り、スイッチング素子の制御信号６を得る。図２は図１
の具体例で、図中、図１，図４と同符号のものは同じ機
能を有する部分を示す。図２において、電圧検出回路５
は抵抗51，52，フォトカプラ53からなり、フォトカプラ
53の入力側をＧＴＯ３のゲート、カソード間に接続し、
抵抗52はフォトシカプラ53と並列に、抵抗51はカソード
側の入力に直列接続され、フォトカプラ53の出力側は制
御回路４に入力されている。このフォトカプラ53の出力
側、つまり電圧レベル判別信号７は、フォトカプラ53の
出力トランジスタのコレクタを出力としている。他方、
スイッチング素子制御回路４は、一端を電圧レベル判別
信号７の入力、他の部分をＮＡＮＤ回路44の入力側とす
る抵抗41，ダイオード42, コンデンサ43からなる遅延回
路 401と、制御信号ＳＣを入力とするＮＡＮＤ回路44、
更に制御信号ＳＣ並びにＮＡＮＤ回路44の出力を入力と
するＮＡＮＤ回路45と、このＮＡＮＤ回路45の出力を入
力とするスイッチング素子のドライブ回路46によって構
成され、ダイオード42のカソードとコンデンサ43との接
続点に電圧レベル判別信号７が接続される。また、８は
短絡検知信号で、ゲート、カソード間短絡故障検知時に
ローレベルとなる。1 is a basic block diagram of an off-gate circuit showing an embodiment of the present invention, in which a voltage detection circuit 5 and a switching element control circuit 4 are added to the configuration of FIG.
1, the voltage detecting circuit 5 reverse voltage between the gates of GT03, cathode - to detect the V GK, by performing the level judgment, to obtain a voltage level discrimination signal 7. The control circuit 4 for the switching element obtains the control signal 6 for the switching element by performing a predetermined logical operation using the two input signals of the control signal SC and the voltage level determination signal 7. 2 is shown in FIG.
In the figure, the same reference numerals as those in FIGS. 1 and 4 denote the parts having the same functions. In FIG. 2, the voltage detection circuit 5
Is composed of resistors 51, 52 and photocoupler 53.
Connect the input side of 53 between the gate and cathode of GTO3,
The resistor 52 is connected in parallel with the photocoupler 53, the resistor 51 is connected in series to the input on the cathode side, and the output side of the photocoupler 53 is input to the control circuit 4. The output side of the photocoupler 53, that is, the voltage level determination signal 7 is output from the collector of the output transistor of the photocoupler 53. On the other hand,
The switching element control circuit 4 has a delay circuit 401 having a resistor 41, a diode 42, and a capacitor 43, one end of which receives the voltage level determination signal 7 and the other part of which serves as an input side of the NAND circuit 44, and a control signal SC. NAND circuit 44,
Further, it is composed of a NAND circuit 45 which receives the control signal SC and the output of the NAND circuit 44 as an input, and a drive circuit 46 of a switching element which receives the output of the NAND circuit 45 as an input, and the connection point between the cathode of the diode 42 and the capacitor 43. The voltage level discrimination signal 7 is connected to. Further, 8 is a short circuit detection signal, which becomes a low level when a short circuit failure between the gate and the cathode is detected.
【０００６】次に、図３を参照してその作用を説明す
る。図３は図２の回路の動作波形で、実線で示した波形
が正常なターンオフ時、破線で示した波形が短絡故障発
生時である。正常なターンオフの場合、時刻t0で制御信
号ＳＣを立上げると、ＧＴＯ３のターンオフ時間T1の間
はゲート、カソード間逆電圧− VGKが電圧検出回路５の
抵抗51，52で定められた判別レベルに達しないため、フ
ォトカプラ53の出力トランジスタはオフ状態で、電圧レ
ベル判別信号7 は遅延回路 401の抵抗41，コンデンサ43
で定められた時定数によって上昇する。ここで、遅延回
路 401の時定数はターンオフ時間T1に対し十分大きな値
としているので、このターンオフ時間T1の間は電圧レベ
ル判別信号７がＮＡＮＤ回路44の入力スレッショルドレ
ベルに達することはない。次に時刻t1で、カソード、ゲ
ート間逆電圧− VGKが立上り、判別レベルを越えるとフ
ォトカプラ53の出力トランジスタがオンするので遅延回
路 401のコンデンサ43の電荷を放電し、電圧レベル判別
信号７はローレベルとなる。このような動作により短絡
検知信号８はハイレベルを保ち、スイッチング素子制御
信号６は制御信号ＳＣと同一のタイミング波形となる。Next, the operation will be described with reference to FIG. FIG. 3 shows operation waveforms of the circuit of FIG. 2, in which the waveform indicated by the solid line indicates normal turn-off and the waveform indicated by the broken line indicates occurrence of a short-circuit fault. For normal turn-off, when the control signal SC at time t 0 raises during the turn-off time of GT03 T 1 is the gate, cathode reverse voltage - V GK is defined by resistors 51 and 52 of the voltage detection circuit 5 Since the judgment level is not reached, the output transistor of the photocoupler 53 is in the OFF state, and the voltage level judgment signal 7 is the resistance 41 and the capacitor 43 of the delay circuit 401.
It rises according to the time constant defined in. Here, since a sufficiently large value constant with respect to the turn-off time T 1 when the delay circuit 401, during the turn-off time T 1 is not the voltage level discrimination signal 7 reaches the input threshold level of the NAND circuit 44. Next, at time t 1, the cathode, gate reverse voltage - V GK is rising, the output transistor of the photocoupler 53 exceeds the discrimination level is turned to discharge the capacitor 43 of the delay circuit 401, the voltage level discrimination signal 7 becomes low level. By such an operation, the short circuit detection signal 8 maintains a high level, and the switching element control signal 6 has the same timing waveform as the control signal SC.
【０００７】一方、ゲート、カソード間短絡故障が発生
した場合、カソード、ゲート間逆電圧− VGKは判別レベ
ルに達することがないため、電圧レベル判別信号７は遅
延回路 401の時定数により制御信号ＳＣのハイレベルま
で上昇を続け、ＮＡＮＤ回路44の入力スレッショルドレ
ベルに達する時刻t10 で、短絡検知信号８はローレベル
となる。したかって、時刻t10 においてスイッチング素
子の制御信号６もローレベルとなり、スイッチング素子
１をオフさせ、短絡電流をしゃ断する。このことによっ
て、オフゲート回路構成部品の破損を防止する。このよ
うな短絡検知、保護動作を行った後も、同期的に制御信
号ＳＣを与え続けた場合、遅延回路 401のコンデンサ43
の電荷はダイオード42に阻止され、制御信号ＳＣ側には
放電しないため、最初の短絡検知時以降の制御信号ＳＣ
の立上り時においては、遅延なく瞬時に短絡検知信号８
がローレベルになり、スイッチング素子の制御信号６は
ローレベルを保持する。すなわちスイッチング素子の短
絡電流しゃ断は単発現象となる。なお、本発明において
はＧＴＯについて説明を行ったが、サイリスタなどの半
導体素子においても適用されることは言うまでもない。On the other hand, when a gate-cathode short-circuit fault occurs, the cathode-gate reverse voltage −VGK does not reach the discrimination level. Therefore, the voltage level discrimination signal 7 is a control signal depending on the time constant of the delay circuit 401. The short-circuit detection signal 8 becomes low level at time t 10 when the input threshold level of the NAND circuit 44 is reached by continuing to rise to the high level of SC. Therefore, the control signal 6 of the switching element also becomes low level at time t 10 , the switching element 1 is turned off, and the short-circuit current is cut off. This prevents damage to the off-gate circuit components. If the control signal SC is continuously applied synchronously even after performing such a short circuit detection and protection operation, the capacitor 43 of the delay circuit 401
Is blocked by the diode 42 and is not discharged to the control signal SC side, the control signal SC after the first short circuit detection is detected.
When the signal rises, the short circuit detection signal 8
Becomes low level, and the control signal 6 of the switching element maintains low level. That is, the short-circuit current interruption of the switching element is a single-shot phenomenon. Although the GTO has been described in the present invention, it goes without saying that it is also applied to a semiconductor element such as a thyristor.
【０００８】[0008]
【発明の効果】以上説明したように本発明によれば、格
別な回路構成によりＧＴＯのゲート、カソード間短絡故
障に伴って２次的に発生するオフゲート回路構成部品の
破損を防止でき、実用上極めて有用性の高いものであ
る。As described above, according to the present invention, it is possible to prevent the breakage of the off-gate circuit component secondary to the gate-cathode short-circuit failure of the GTO due to the special circuit configuration, which is practical. It is extremely useful.
【０００９】[0009]
【図１】図１は本発明の基本構成図である。FIG. 1 is a basic configuration diagram of the present invention.
【図２】図２は本発明の一実施例を示す回路図である。FIG. 2 is a circuit diagram showing an embodiment of the present invention.
【図３】図３は図２の動作波形説明図である。FIG. 3 is an explanatory diagram of operation waveforms in FIG.
【図４】図４は従来方式の基本構成図である。FIG. 4 is a basic configuration diagram of a conventional method.
【図５】図５は図４の動作波形説明図である。5 is an explanatory diagram of operation waveforms in FIG. 4;
【００１０】[0010]
１ スイッチング素子 ２ 直流電源 ３ ＧＴＯ ４ スイッチング素子制御回路 ５ 電圧検出回路 ６ スイッチング素子制御信号 ７ 電圧レベル判別信号 ８ 短絡検知信号 ＳＣ 制御信号 401 遅延回路 41 抵抗 42 ダイオード 43 コンデンサ 44 ＮＡＮＤ回路 45 ＮＡＮＤ回路 46 スイッチング素子のドライブ回路 51 抵抗 52 抵抗 53 フォトカプラ 1 switching element 2 DC power supply 3 GTO 4 switching element control circuit 5 voltage detection circuit 6 switching element control signal 7 voltage level determination signal 8 short circuit detection signal SC control signal 401 delay circuit 41 resistance 42 diode 43 capacitor 44 NAND circuit 45 NAND circuit 46 Switching element drive circuit 51 Resistor 52 Resistor 53 Photocoupler
Claims (1)
ゲート、カソードが直列に接続されたオフゲート回路を
有するＧＴＯのゲート回路において、前記スイッチング
素子を駆動せしめる制御回路と、前記ＧＴＯのゲート、
カソード間電圧を検出する電圧検出回路とを設け、該電
圧検出回路の検出した前記ＧＴＯのゲート、カソード間
電圧レベルに応動して前記スイッチング素子を前記制御
回路によってスイッチオフさせるようにしたことを特徴
とするＧＴＯのゲート回路。1. A gate circuit of a GTO having a direct current power supply, a switching element, and an off-gate circuit in which a gate and a cathode of the GTO are connected in series, a control circuit for driving the switching element, and a gate of the GTO,
A voltage detection circuit for detecting a voltage between the cathodes is provided, and the switching element is switched off by the control circuit in response to a voltage level between the gate and the cathode of the GTO detected by the voltage detection circuit. Gate circuit of GTO.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36006591A JPH05184134A (en) | 1991-12-26 | 1991-12-26 | Gate circuit for gto |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36006591A JPH05184134A (en) | 1991-12-26 | 1991-12-26 | Gate circuit for gto |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05184134A true JPH05184134A (en) | 1993-07-23 |
Family
ID=18467731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36006591A Pending JPH05184134A (en) | 1991-12-26 | 1991-12-26 | Gate circuit for gto |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05184134A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111416605A (en) * | 2019-01-06 | 2020-07-14 | 广州市金矢电子有限公司 | Semi-controlled device driving device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01278256A (en) * | 1988-04-28 | 1989-11-08 | Fuji Electric Co Ltd | Gate driving circuit for gto thyristor |
-
1991
- 1991-12-26 JP JP36006591A patent/JPH05184134A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01278256A (en) * | 1988-04-28 | 1989-11-08 | Fuji Electric Co Ltd | Gate driving circuit for gto thyristor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111416605A (en) * | 2019-01-06 | 2020-07-14 | 广州市金矢电子有限公司 | Semi-controlled device driving device |
| CN111416605B (en) * | 2019-01-06 | 2024-04-12 | 广州市金矢电子有限公司 | Semi-controlled device driving device |
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