JPH05175658A - Manufacture of thin film multilayer wiring board - Google Patents
Manufacture of thin film multilayer wiring boardInfo
- Publication number
- JPH05175658A JPH05175658A JP3337413A JP33741391A JPH05175658A JP H05175658 A JPH05175658 A JP H05175658A JP 3337413 A JP3337413 A JP 3337413A JP 33741391 A JP33741391 A JP 33741391A JP H05175658 A JPH05175658 A JP H05175658A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- film
- wiring
- resist pattern
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Formation Of Insulating Films (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、層間絶縁層にポリイミ
ドを使用して薄膜多層配線を形成した基板の製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a substrate in which thin film multilayer wiring is formed by using polyimide for an interlayer insulating layer.
【０００２】近年、複数のプリント配線板の相互接続に
使用する大型コンピュータ用マザーボードとして、薄膜
多層配線基板が使用されるようになったが、従来方法で
製造した薄膜多層配線のマザーボードは、製造工程が長
くコスト高であると共に、高密度化の要求に対し配線の
微細化（狭幅化）が困難であった。In recent years, a thin film multilayer wiring board has been used as a motherboard for a large computer used for interconnecting a plurality of printed wiring boards. However, a thin film multilayer wiring motherboard manufactured by a conventional method is manufactured by a manufacturing process. In addition to being long and costly, it has been difficult to make the wiring finer (narrower) in response to the demand for higher density.
【０００３】[0003]
【従来の技術】図６は薄膜多層配線基板の一部の模式断
面図、図７は導体薄膜より配線をパターン形成するレジ
ストパターンの説明図、図８は従来の薄膜多層配線基板
における層間絶縁層の製造方法の説明図である。2. Description of the Related Art FIG. 6 is a schematic sectional view of a part of a thin film multilayer wiring board, FIG. 7 is an explanatory view of a resist pattern for patterning wiring from a conductive thin film, and FIG. 8 is an interlayer insulating layer in a conventional thin film multilayer wiring board. FIG. 6 is an explanatory diagram of a manufacturing method of
【０００４】図６において、薄膜よりパターン形成した
配線が５層である配線基板１は、絶縁基板（セラミック
基板）２の表面に１層目の配線３を形成したのち、１層
目の絶縁層（ポリイミド層）４を形成しその上に、所定
部（ビアホール部）にて配線３に接続する２層目の配線
５を形成する。In FIG. 6, a wiring board 1 having five layers of wiring formed by patterning a thin film has a first wiring 3 formed on the surface of an insulating substrate (ceramic substrate) 2 and then the first insulating layer. A (polyimide layer) 4 is formed, and a second-layer wiring 5 connected to the wiring 3 at a predetermined portion (via hole portion) is formed thereon.
【０００５】次いで、２層目の絶縁層（ポリイミド層）
６を形成しその上に、所定部（ビアホール部）にて配線
５に接続する３層目の配線７を形成したのち、３層目の
絶縁層（ポリイミド層）８を形成しその上に、所定部
（ビアホール部）にて配線７に接続する４層目の配線９
を形成する。Next, the second insulating layer (polyimide layer)
6 is formed, and a third layer wiring 7 connected to the wiring 5 at a predetermined portion (via hole portion) is formed thereon, and then a third insulating layer (polyimide layer) 8 is formed and then, The fourth layer wiring 9 connected to the wiring 7 at a predetermined portion (via hole portion)
To form.
【０００６】しかるのち、４層目の絶縁層（ポリイミド
層）10を形成しその上に、所定部（ビアホール部）にて
配線９に接続する５層目の配線11を形成する。図７にお
いて、12は２層目の配線５を形成するための導体薄膜、
13は導体薄膜12より配線５を形成するためのレジストパ
ターンであり、ポリイミド液を塗布し，それを半焼成し
てからパターニング（露光，現像）し, 本焼成してなる
絶縁層４は、ビアホールの周囲に盛り上がり14ができ
る。After that, a fourth insulating layer (polyimide layer) 10 is formed, and a fifth layer wiring 11 connected to the wiring 9 at a predetermined portion (via hole portion) is formed thereon. In FIG. 7, 12 is a conductor thin film for forming the second layer wiring 5,
Reference numeral 13 is a resist pattern for forming the wiring 5 from the conductor thin film 12, which is formed by applying a polyimide solution, semi-baking it, then patterning (exposure and development), and then baking the insulation layer 4 to form a via hole. There are 14 rises around the area.
【０００７】その結果、レジストパターン13を薄くし例
えば図中に一点鎖線15で示す如くすると、レジストパタ
ーン13は盛り上がり14の頂部内側で薄くなり、盛り上が
り14の頂部近傍で薄膜12が露呈するようになる。かかる
露呈部は、薄膜12より配線５をパターン形成する際に溶
去され、配線５が配線３と接続されなくなる。従って、
従来のレジストパターン13は10μm 以下に薄くすること
ができない。As a result, when the resist pattern 13 is thinned, for example, as shown by a chain line 15 in the figure, the resist pattern 13 becomes thin inside the top of the ridge 14 and the thin film 12 is exposed near the top of the ridge 14. Become. The exposed portion is ablated by the thin film 12 when the wiring 5 is patterned, and the wiring 5 is no longer connected to the wiring 3. Therefore,
The conventional resist pattern 13 cannot be thinned to 10 μm or less.
【０００８】また、従来の各絶縁層４，６，８，10は何
れも２層構成であり、絶縁層４に係わる図８を用いて、
絶縁層４，６，８，10の製造方法を説明する。図８(イ)
において、絶縁基板２の表面に配線３を形成したのち、
配線３の所定部を露呈せしめる第１の絶縁層４-1をパタ
ーン形成する。絶縁層４-1は、ポリイミド液を塗布し，
それを半焼成してからパターニングし，本焼成してな
り、絶縁層４-1のパターニングに際してマスクに塵埃が
被着していると、例えば配線３に貫通するピンホール16
ができる。Further, each of the conventional insulating layers 4, 6, 8 and 10 has a two-layer structure, and referring to FIG. 8 relating to the insulating layer 4,
A method of manufacturing the insulating layers 4, 6, 8 and 10 will be described. Figure 8 (a)
In, after forming the wiring 3 on the surface of the insulating substrate 2,
The first insulating layer 4 -1 exposing a predetermined portion of the wiring 3 is patterned. The insulating layer 4-1 is formed by applying a polyimide solution,
Patterning it after semi-sintered, it was the sintering, the dust mask is deposited upon patterning of the insulating layer 4 -1, pinhole 16 penetrating example to the wiring 3
You can
【０００９】次いで、図８(ロ) に示す如く、絶縁層４-1
の上に第２の絶縁層４-2をパターン形成させると、絶縁
層４が完成する。ポリイミドにてなる絶縁層４-2は、絶
縁層４-1それと同一工程を経て形成させるが、絶縁層４
-1に生じたピンホール16は絶縁層４-2が埋めることにな
る。Next, as shown in FIG. 8B, the insulating layer 4 -1
The insulating layer 4 is completed by patterning the second insulating layer 4-2 . Insulating layer 4 -2 made by polyimide, but is formed through an insulating layer 4 -1 identical step, the insulating layer 4
The pinhole 16 generated at -1 is filled with the insulating layer 4-2 .
【００１０】次いで、図８(ハ) に示す如く導体薄膜12を
被着したのち、薄膜12の不要部を溶去すると、図８(ニ)
に示す如き配線５が形成される。絶縁層４-2にできたピ
ンホール18は絶縁層６が埋めることになり、絶縁層６，
８，10と配線７，９，11を絶縁層４および配線５と同様
に形成し、図６に示す配線基板１が完成する。Next, as shown in FIG. 8C, after depositing the conductor thin film 12, the unnecessary portion of the thin film 12 is melted away.
The wiring 5 is formed as shown in FIG. Pinhole 18 made in the insulating layer 4 -2 becomes the insulating layer 6 is filled, the insulating layer 6,
8 and 10 and wirings 7, 9 and 11 are formed in the same manner as the insulating layer 4 and the wiring 5, and the wiring board 1 shown in FIG. 6 is completed.
【００１１】[0011]
【発明が解決しようとする課題】層間絶縁層の信頼性を
低下させることなく薄膜多層回路のコストを低減には、
工程の簡略が必要であり、層間絶縁層について工程を簡
略化するには、従来の絶縁層と同等の信頼性を確保し単
層化すればよいことになる。In order to reduce the cost of the thin film multilayer circuit without lowering the reliability of the interlayer insulating layer,
The process needs to be simplified, and in order to simplify the process for the interlayer insulating layer, it is sufficient to secure the same level of reliability as that of the conventional insulating layer and form a single layer.
【００１２】また、配線の微細化については、導体薄膜
に形成するレジストパターンを10μm 以下 (例えば数μ
m 程度) に薄くすれば可能になる。しかしながら、絶縁
層のピンホールを絶縁材で埋めるため２層とした従来の
製造方法では、絶縁層の単層化が不可能であり、下部配
線と上部配線とを接続させるビアホール部における必要
性から決められた従来のレジストパターンは、薄くでき
ないという問題点があった。For fine wiring, the resist pattern formed on the conductor thin film should be 10 μm or less (for example, several μm).
It becomes possible if it is thinned to about m). However, with the conventional manufacturing method in which the pinholes of the insulating layer are filled with the insulating material to form two layers, it is impossible to make the insulating layer into a single layer, and it is necessary to form the via holes for connecting the lower wiring and the upper wiring. There is a problem that the determined conventional resist pattern cannot be thinned.
【００１３】[0013]
【課題を解決するための手段】図１は本発明方法の概要
を説明するための図であり、(イ) 〜(ハ) は２重露光によ
るポリイミド絶縁層の単層化方法の説明図、(ニ),(ホ) は
ポリイミド絶縁層の上に導体パターンを形成する方法の
説明図である。FIG. 1 is a diagram for explaining the outline of the method of the present invention, and (a) to (c) are explanatory views of a method for forming a single layer of a polyimide insulating layer by double exposure, (D) and (e) are explanatory views of a method for forming a conductor pattern on a polyimide insulating layer.
【００１４】図１(イ) において、絶縁基板には配線３を
形成したのち、感光性ポリイミド液を塗布し半焼成した
ポリイミド膜21を被着し、ポリイミド膜21より所定の絶
縁層を形成する遮光パターン23が形成されたマスク22を
ポリイミド膜21に重ね、ポリイミド膜21のパターン形成
に必要な光エネルギの第１の照射光24にてコンタクト露
光する。In FIG. 1A, after the wiring 3 is formed on the insulating substrate, a polyimide film 21 applied with a photosensitive polyimide solution and semi-baked is applied to form a predetermined insulating layer from the polyimide film 21. A mask 22 having a light-shielding pattern 23 formed thereon is overlapped on the polyimide film 21, and contact exposure is performed with a first irradiation light 24 having light energy required for patterning the polyimide film 21.
【００１５】次いで、図１(ロ) に示すように、遮光パタ
ーン23より広範囲に遮光する遮光パターン26が形成され
たマスク25をポリイミド膜21に重ね、少なくともポリイ
ミド膜21の表層部を感光せしめる光エネルギの第２の照
射光27にてプロキシミテー露光する。Then, as shown in FIG. 1B, a mask 25 having a light-shielding pattern 26 for shielding light in a wider area than the light-shielding pattern 23 is laid on the polyimide film 21, and at least the surface layer of the polyimide film 21 is exposed to light. Proximity exposure is performed with the second irradiation light 27 of energy.
【００１６】次いで、ポリイミド膜21を現像処理して図
１(ハ) に示すように、従来の絶縁層４に相当する絶縁層
28を形成したのち、図１(ニ) に示すように、導体薄膜12
を被着し、上部配線パターンに対応し, 絶縁層28の上に
上部配線を形成するのに必要な厚さの第１のレジストパ
ターン29を形成し、絶縁層28の所定部 (ビアホール部)
のレジストパターン29に第２のレジストパターン30を重
ねて形成させる。Next, the polyimide film 21 is subjected to a development treatment, and as shown in FIG. 1C, an insulating layer corresponding to the conventional insulating layer 4.
After forming 28, as shown in FIG.
A first resist pattern 29 having a thickness necessary to form the upper wiring on the insulating layer 28 corresponding to the upper wiring pattern, and a predetermined portion (via hole portion) of the insulating layer 28.
The second resist pattern 30 is formed on the resist pattern 29 of FIG.
【００１７】しかるのち、レジストパターン29および30
を用いて導体薄膜12の露呈部を溶去し、レジストパター
ン29および30を除去すると図１(ホ) に示すように、配線
５が完成する。After that, the resist patterns 29 and 30 are formed.
The exposed portion of the conductor thin film 12 is removed by using the resist, and the resist patterns 29 and 30 are removed, whereby the wiring 5 is completed as shown in FIG.
【００１８】以下同様に、従来の配線７，９，11および
絶縁層６，８，10に相当する配線と絶縁層をパターン形
成し、図６に示す配線基板１と同様な薄膜多層配線基板
が完成することになる。Similarly, the conventional wirings 7, 9 and 11 and the wirings and insulating layers corresponding to the insulating layers 6, 8 and 10 are patterned to form a thin film multilayer wiring board similar to the wiring board 1 shown in FIG. It will be completed.
【００１９】[0019]
【作用】上記手段によれば、２重露光によって絶縁層の
単層化が可能となり、そのことによって絶縁層形成工程
が簡易化される。さらに、絶縁層の上に形成した配線形
成用レジストパターンを薄くすることが可能となり、そ
のことによって絶縁層の上に形成する配線の微細化を可
能にする。According to the above means, the insulating layer can be made into a single layer by double exposure, which simplifies the insulating layer forming step. Further, the wiring forming resist pattern formed on the insulating layer can be made thin, which enables miniaturization of the wiring formed on the insulating layer.
【００２０】[0020]
【実施例】図２は本発明方法の実施例による層間絶縁層
を形成する主要工程図、図３は本発明方法の実施例によ
るレジストパターンを形成する主要工程図、図４は図２
に示す２重露光方法の詳細説明図、図５は図２に示す２
層レジストの詳細説明図である。FIG. 2 is a main process diagram for forming an interlayer insulating layer according to an embodiment of the method of the present invention, FIG. 3 is a main process diagram for forming a resist pattern according to an embodiment of the method of the present invention, and FIG.
2 is a detailed explanatory view of the double exposure method shown in FIG.
It is a detailed explanatory view of a layer resist.
【００２１】図２(イ) において、絶縁基板２の表面に薄
膜配線（下部配線）３を形成したのち、図２(ロ) に示す
ように、配線３を覆うポリイミド膜21を被着する。ポリ
イミド液を塗布し半焼成してなるポリイミド膜21は、厚
さが10〜50μm 程度であり、この厚さは、従来の絶縁層
４-1または４-2の本焼成前の厚さと同程度である。In FIG. 2A, after the thin film wiring (lower wiring) 3 is formed on the surface of the insulating substrate 2, a polyimide film 21 covering the wiring 3 is deposited as shown in FIG. 2B. Polyimide film 21 of polyimide solution was applied made by semi-baked is about 10~50μm thickness, this thickness conventional insulating layers 4 -1 or 4 -2 thickness approximately equal before the firing Is.
【００２２】次いで、図２(ハ) に示す如く、ポリイミド
膜21より絶縁層を形成するのに必要な遮光パターン23が
形成されたマスク22をポリイミド膜21に重ね、ポリイミ
ド膜21のパターン形成に必要な光エネルギ、例えば 200
〜500mJ/cm2 の第１の照射光24にてコンタクト露光す
る。Next, as shown in FIG. 2C, a mask 22 having a light-shielding pattern 23 necessary for forming an insulating layer from the polyimide film 21 is overlaid on the polyimide film 21 to form the pattern of the polyimide film 21. The required light energy, eg 200
Contact exposure is performed with the first irradiation light 24 of about 500 mJ / cm 2 .
【００２３】次いで、図２(ニ) に示す如く、マスク22に
替えて遮光パターン23より適当な広範囲に遮光する遮光
パターン26が形成されたマスク25をポリイミド膜21に重
ね、少なくともポリイミド膜21の表層部を感光せしめる
光エネルギ、例えば50〜500mJ/cm2 の第２の照射光27に
てプロキシミテー露光する。Next, as shown in FIG. 2D, a mask 25 having a light-shielding pattern 26 that shields light in a more appropriate area than the light-shielding pattern 23 is formed on the polyimide film 21 in place of the mask 22, and at least the polyimide film 21 is covered. Proximity exposure is performed with light energy that sensitizes the surface layer portion, for example, second irradiation light 27 of 50 to 500 mJ / cm 2 .
【００２４】かかるマスク22および25を使用した２重露
光において、ネガ型の感光性ポリイミド膜21の感光部が
非溶去性となり、図４(イ) に示す如く、遮光パターン23
の対向部分21-1が溶去可能である。しかし、図示する如
くマスク22に塵埃31が被着していると、塵埃31に対応す
る部分21-2も溶去可能であり、その儘で現像すればピン
ホールが形成されることになる。In the double exposure using the masks 22 and 25, the photosensitive portion of the negative photosensitive polyimide film 21 becomes non-dissolvable, and the light shielding pattern 23 is formed as shown in FIG.
The facing portion 21 -1 of is capable of being removed. However, as shown in the figure, when the dust 31 is adhered to the mask 22, the portion 21 -2 corresponding to the dust 31 can also be melted away, and a pinhole will be formed if development is carried out at the same time.
【００２５】そこで、図４(ロ) に示すようにマスク25を
使用して２回目の露光を行うと、マスク22の塵埃31と同
一部分のマスク25に塵埃が被着する可能性は、確率的に
殆ど零であり、従って、塵埃31による非感光部21-2は２
回目の露光によって感光し、、非感光部21-2によるピン
ホールが形成されないことになる。Therefore, when the mask 25 is used for the second exposure as shown in FIG. 4B, the possibility that the dust may adhere to the mask 25 at the same portion as the dust 31 of the mask 22 is high. Is almost zero, and therefore the non-photosensitive portion 21 -2 due to the dust 31 is 2
The second exposure causes exposure, and no pinhole is formed by the non-exposed area 21 -2 .
【００２６】従って、２重露光したポリイミド膜21を現
像し本焼成すると、図４(ホ) に示す如くピンホールがな
く、従来の絶縁層４の約1/２の厚さの絶縁層28が形成さ
れることになる。Therefore, when the double-exposed polyimide film 21 is developed and main-baked, there is no pinhole as shown in FIG. 4 (e), and the insulating layer 28 having a thickness of about 1/2 of the conventional insulating layer 4 is formed. Will be formed.
【００２７】以下、絶縁層28と同様に、従来の絶縁層
６，８，10に相当する絶縁層を形成した多層配線基板
は、層間絶縁層の形成工程が従来方法より簡易となり、
かつ、比較的高価であるポリイミド液の使用量が半減す
る。Hereinafter, similar to the insulating layer 28, in the multilayer wiring board in which the insulating layers corresponding to the conventional insulating layers 6, 8 and 10 are formed, the step of forming the interlayer insulating layer is simpler than that of the conventional method.
Moreover, the amount of the relatively expensive polyimide liquid used is halved.
【００２８】図３(イ) において、絶縁層28を形成した絶
縁基板２には、絶縁層28を覆う例えば銅の導体薄膜12を
被着したのち、図３(ロ) に示すように、絶縁層28の上に
導体薄膜12より配線を形成可能な厚さ、例えば厚さ１〜
４μm であるレジストパターン29を形成する。In FIG. 3 (a), an insulating substrate 28 on which an insulating layer 28 is formed is coated with a conductor thin film 12 of copper, for example, which covers the insulating layer 28. Then, as shown in FIG. A thickness capable of forming wiring from the conductor thin film 12 on the layer 28, for example, a thickness of 1 to
A resist pattern 29 of 4 μm is formed.
【００２９】かかるレジストパターン29は、図７を用い
て説明した如くビアホール部では薄過ぎるため、図３
(ハ) および図５に示す如く、該ビアホール部ではレジス
トパターン29に所望厚さ、例えば厚さ５〜10μm のレジ
ストパターン30を積層形成させる。すると、レジストパ
ターン29が薄くなって露呈する導体薄膜12を、レジスト
パターン30が覆うようになる。Since the resist pattern 29 is too thin in the via hole as described with reference to FIG.
As shown in (c) and FIG. 5, a resist pattern 30 having a desired thickness, for example 5 to 10 μm, is laminated on the resist pattern 29 in the via hole portion. Then, the resist pattern 30 covers the exposed conductor thin film 12 in which the resist pattern 29 becomes thin.
【００３０】しかるのち、レジストパターン29,30 を使
用して導体薄膜12の露呈部を溶去すると、図３(ニ) に示
す如き配線５が形成される。以下、配線５と同様に、従
来の配線７，９，11に相当する配線を形成した多層配線
基板は、絶縁層の上に形成する配線の微細化が可能であ
り、下部配線と上部配線との接続が確保されることにな
る。Then, when the exposed portions of the conductor thin film 12 are removed by using the resist patterns 29 and 30, the wiring 5 as shown in FIG. 3D is formed. Hereinafter, similar to the wiring 5, the multilayer wiring board on which the wirings corresponding to the conventional wirings 7, 9 and 11 are formed allows the wirings formed on the insulating layer to be miniaturized, and the lower wirings and the upper wirings can be formed. Will be secured.
【００３１】[0031]
【発明の効果】以上説明したように本発明方法によれ
ば、従来の絶縁層と同等の信頼性を確保し層間絶縁層の
単層化が可能となり、そのことによって絶縁層の製造工
程が簡易化し工程数が10〜20％減少すると共に、比較的
高価なポリイミド液の使用量が従来の1/２になる。さら
に、絶縁層の上に形成する配線を５μm 以下に微細化可
能とし、従来より高密度の配線を形成できるようにした
効果がある。As described above, according to the method of the present invention, the same level of reliability as that of the conventional insulating layer can be secured and the interlayer insulating layer can be made into a single layer, which simplifies the manufacturing process of the insulating layer. The number of processes is reduced by 10 to 20%, and the amount of relatively expensive polyimide liquid used is halved compared to the conventional amount. Further, there is an effect that the wiring formed on the insulating layer can be miniaturized to 5 μm or less so that the wiring can be formed with a higher density than ever before.
【図１】 本発明方法の概要を説明するための図であ
る。FIG. 1 is a diagram for explaining an outline of a method of the present invention.
【図２】 本発明方法の実施例による層間絶縁層を形成
する主要工程図である。FIG. 2 is a main process diagram of forming an interlayer insulating layer according to an embodiment of the method of the present invention.
【図３】 本発明方法の実施例によるレジストパターン
を形成する主要工程図である。FIG. 3 is a main process diagram for forming a resist pattern according to an embodiment of the method of the present invention.
【図４】 図２に示す２重露光方法の詳細説明図であ
る。FIG. 4 is a detailed explanatory diagram of the double exposure method shown in FIG.
【図５】 図２に示す２層レジストの詳細説明図であ
る。5 is a detailed explanatory view of the two-layer resist shown in FIG.
【図６】 薄膜多層配線基板の一部の模式断面図であ
る。FIG. 6 is a schematic sectional view of a part of a thin film multilayer wiring board.
【図７】 導体薄膜より配線をパターン形成するレジス
トパターンの説明図である。FIG. 7 is an explanatory diagram of a resist pattern for forming a wiring pattern from a conductive thin film.
【図８】 従来の薄膜多層配線基板における層間絶縁層
の製造方法の説明図である。FIG. 8 is an explanatory view of a method for manufacturing an interlayer insulating layer in a conventional thin film multilayer wiring board.
２は絶縁基板 ３は下部配線 ５は上部配線 21は感光性ポリイミド膜 22は第１の露光マスク 23は第１の露光マスクの遮光パターン 24は第１の照射光 25は第２の露光マスク 26は第２の露光マスクの遮光パターン 28は層間絶縁層 29は第１のレジストパターン 30は第２のレジストパターン 2 is the insulating substrate 3 is the lower wiring 5 is the upper wiring 21 is the photosensitive polyimide film 22 is the first exposure mask 23 is the light shielding pattern of the first exposure mask 24 is the first irradiation light 25 is the second exposure mask 26 Is a light-shielding pattern of the second exposure mask 28 is an interlayer insulating layer 29 is a first resist pattern 30 is a second resist pattern
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/46 Ｎ 6921−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H05K 3/46 N 6921-4E
Claims (4)
薄膜配線(3,5) を多層形成するのに際し、下部配線(3)
を形成した絶縁基板(2) の表面に感光性ポリイミド膜(2
1)を被着し、該ポリイミド膜(21)より所定の絶縁層(28)
を形成する遮光パターン(23)が形成された第１の露光マ
スク(22)を該ポリイミド膜(21)に重ね、該絶縁層(28)の
パターン形成に必要な第１の照射光(24)にてコンタクト
露光し、該遮光パターン(23)より大形の遮光パターン(2
6)が形成された第２の露光マスク(25)を該ポリイミド膜
(21)に重ね、少なくとも該ポリイミド膜(21)の表層部を
感光させる第２の照射光(27)にてプロキシミテー露光
し、該ポリイミド膜(21)を現像し該絶縁層(28)を形成す
ることを特徴とした薄膜多層配線基板の製造方法。1. A polyimide is used for an interlayer insulating layer (28),
When forming thin film wiring (3, 5) in multiple layers, lower wiring (3)
The photosensitive polyimide film (2
1) is deposited, and a predetermined insulating layer (28) is formed from the polyimide film (21).
A first exposure mask (22) on which a light-shielding pattern (23) for forming a film is formed on the polyimide film (21), and a first irradiation light (24) necessary for patterning the insulating layer (28). Contact exposure with a light-shielding pattern (23) that is larger than the light-shielding pattern (23).
The second exposure mask (25) on which 6) is formed is used as the polyimide film.
Proximity exposure with a second irradiation light (27) which overlaps with (21) and sensitizes at least the surface layer portion of the polyimide film (21), and develops the polyimide film (21) to form the insulating layer (28). A method of manufacturing a thin-film multilayer wiring board, characterized by forming the same.
１の照射光(24)の照度の約１／５であることを特徴とす
る請求項１記載の薄膜多層配線基板の製造方法。2. The thin-film multilayer wiring board according to claim 1, wherein the illuminance of the second irradiation light (27) is about ⅕ of the illuminance of the first irradiation light (24). Manufacturing method.
薄膜配線(3,5) を多層形成するのに際し、絶縁基板(2)
に下部配線(3) を形成したのち、該下部配線(3) の所定
部を露呈せしめる透孔があいた絶縁層(28)を形成し、露
呈する該下部配線(3) の所定部に接続する上部配線用の
導体薄膜(12)を該絶縁層(28)の上に被着し、該絶縁層(2
8)の上に上部配線(5) を形成するのに必要な厚さの第１
のレジスト膜を該導体薄膜の上に被着し、該第１のレジ
スト膜の不要部を除去して第１のレジストパターン(29)
を形成し、該透孔とその周囲を覆って形成された該第１
のレジストパターン(29)の上に第２のレジストパターン
(30)を形成し、該第２のレジストパターン(30)が積層さ
れない該第１のレジストパターン(29)および該第２のレ
ジストパターン(30)が積層された該第１のレジストパタ
ーン(29)を用いて該導体薄膜(12)の露呈部を除去するこ
とを特徴とする薄膜多層配線基板の製造方法。3. The interlayer insulating layer (28) is made of polyimide,
Insulating substrate (2) for forming multiple layers of thin film wiring (3, 5)
After the lower wiring (3) is formed on the lower wiring (3), an insulating layer (28) having a through hole for exposing a predetermined portion of the lower wiring (3) is formed and connected to the predetermined portion of the lower wiring (3) to be exposed. A conductor thin film (12) for upper wiring is applied onto the insulating layer (28), and the insulating layer (2)
1) of the thickness needed to form the top wiring (5) on top of 8)
First resist pattern (29) by depositing the resist film of 1) on the conductor thin film and removing unnecessary portions of the first resist film.
The first hole formed to cover the through hole and its surroundings.
Second resist pattern on the resist pattern (29) of
(30) and the first resist pattern (29) in which the second resist pattern (30) is not laminated and the first resist pattern (29) in which the second resist pattern (30) is laminated. ) Is used to remove the exposed portion of the conductor thin film (12).
を１〜４μm 程度とし、前記第２のレジストパターン(3
0)の厚さを５〜10μm 程度とすることを特徴とする請求
項３記載の薄膜多層配線基板の製造方法。4. The first resist pattern (29) has a thickness of about 1 to 4 μm, and the second resist pattern (3) is formed.
The method of manufacturing a thin-film multilayer wiring board according to claim 3, wherein the thickness of (0) is about 5 to 10 µm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3337413A JPH05175658A (en) | 1991-12-20 | 1991-12-20 | Manufacture of thin film multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3337413A JPH05175658A (en) | 1991-12-20 | 1991-12-20 | Manufacture of thin film multilayer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05175658A true JPH05175658A (en) | 1993-07-13 |
Family
ID=18308404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3337413A Withdrawn JPH05175658A (en) | 1991-12-20 | 1991-12-20 | Manufacture of thin film multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05175658A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007514201A (en) * | 2003-12-12 | 2007-05-31 | ヒューレット−パッカード デベロップメント カンパニー エル．ピー． | Method for forming a depression in the surface of a photoresist layer |
-
1991
- 1991-12-20 JP JP3337413A patent/JPH05175658A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007514201A (en) * | 2003-12-12 | 2007-05-31 | ヒューレット−パッカード デベロップメント カンパニー エル．ピー． | Method for forming a depression in the surface of a photoresist layer |
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