JPH05109978A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05109978A
JPH05109978A JP3269644A JP26964491A JPH05109978A JP H05109978 A JPH05109978 A JP H05109978A JP 3269644 A JP3269644 A JP 3269644A JP 26964491 A JP26964491 A JP 26964491A JP H05109978 A JPH05109978 A JP H05109978A
Authority
JP
Japan
Prior art keywords
semiconductor chips
gap
time
mold resin
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3269644A
Other languages
Japanese (ja)
Inventor
Masaki Waki
政樹 脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3269644A priority Critical patent/JPH05109978A/en
Priority to US07/961,171 priority patent/US5530292A/en
Publication of JPH05109978A publication Critical patent/JPH05109978A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent a crack or the like from occurring on a package at the time of packaging by providing a gap between two semiconductor chips and filling the gap with mold resin at the time of resin molding. CONSTITUTION:Ends of tape leads 5A, 5B which have been subjected to lea- folding working in TAB are thermo-compression-bonded to both faces of an outer lead 6a of a lead frame having a center opening. The other ends of the tape leads 5A, 5B are connected to semiconductor chips 3A, 3B via bumps 4. A gap 8 is formed at this time between rear faces of the semiconductor chips 3A, 3B depending on a degree of leg folding. Therefore, at the time of resin molding, the gap 3 is filled with mold resin 7 flowing in it. Thus, moisture cannot enter the rear faces of the semiconductor chips 3A, 3B, so that occurrence of void or thermal stress at the time of packaging a substrate can be suppressed, as well as an increase in a contact area with the mold resin 7 can improve adhesion with the mold resin 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、複数の半導体チップを
有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of semiconductor chips.

【０００２】近年、電子機器等の小型化に伴い、ＩＣが
高密度化されると共に、一つのパッケージ内に複数の半
導体チップを搭載するチップ・オン・チップ構造のもの
がある。そのため、パッケージングにあたり、実装時に
クラック等を生じないようにする必要がある。[0002] In recent years, there has been a chip-on-chip structure in which a plurality of semiconductor chips are mounted in one package while the density of ICs has been increased along with the miniaturization of electronic devices and the like. Therefore, in packaging, it is necessary to prevent cracks and the like from occurring during mounting.

【０００３】[0003]

【従来の技術】図５に、従来の半導体装置の構成図を示
す。図５において、複数の半導体チップを有する半導体
装置１A は、リードフレーム２の中央開口部分にシリコ
ンで形成される第１及び第２の半導体チップ３A ，３B
が位置する。この第１及び第２の半導体チップ３A ，３
B は、互いのシリコン背面が接合した状態である。2. Description of the Related Art FIG. 5 is a block diagram of a conventional semiconductor device. In FIG. 5, a semiconductor device 1 A having a plurality of semiconductor chips has first and second semiconductor chips 3 A and 3 B formed of silicon in a central opening of a lead frame 2.
Is located. The first and second semiconductor chips 3 A , 3
B is a state where the silicon back surfaces are bonded to each other.

【０００４】また、第１及び第２の半導体チップ３A ，
３B の両表面にはバンプ４を備えており、それぞれ足曲
げ加工されたテープリード５A ，５B の一端に接続（イ
ンナ・リード・ボンディング）される。そして、テープ
リード５A ，５B の他端はリードフレーム２のアウタリ
ード６に熱圧着（アウタ・リード・ボンディング）さ
れ、モールド樹脂７によりパッケージングされる。例え
ば、表面実装するためには、アウタリード６がＬ型（Ｊ
型でも可）形状に加工される。Further, the first and second semiconductor chips 3 A ,
Bumps 4 are provided on both surfaces of 3 B , and are connected (inner lead bonding) to one end of the tape leads 5 A and 5 B which are bent. The other ends of the tape leads 5 A and 5 B are thermocompression-bonded (outer lead bonding) to the outer leads 6 of the lead frame 2 and packaged with the molding resin 7. For example, for surface mounting, the outer leads 6 are L-shaped (J
It can be processed into a shape.

【０００５】[0005]

【発明が解決しようとする課題】しかし、上述の半導体
装置１A は、半導体チップ３A ，３B の背面同士を接合
させているが、実際には微小の凹凸があり、完全に隙間
なく接合されているものではなく、微小の隙間を有する
ものである。従って、樹脂モールド後、２つの半導体チ
ップ３A ，３B の背面の隙間に水分が進入したり、モー
ルド樹脂７との密着が不十分となり、基板等への実装時
のストレスによってパッケージにクラック等を生じると
いう問題がある。However, in the above-described semiconductor device 1 A , the back surfaces of the semiconductor chips 3 A and 3 B are bonded to each other, but in reality, there are minute irregularities, and the bonding is completely without gaps. It is not the one that has been formed but has a minute gap. Therefore, after the resin molding, water enters the gap between the back surfaces of the two semiconductor chips 3 A and 3 B , or the adhesion with the molding resin 7 becomes insufficient, and the package is cracked due to the stress during mounting on the substrate or the like. There is a problem that occurs.

【０００６】そこで、本発明は上記課題に鑑みなされた
もので、実装時のパッケージのクラック等を防止する半
導体装置を提供することを目的とする。Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device which prevents a crack or the like of a package during mounting.

【０００７】[0007]

【課題を解決するための手段】上記課題は、背面を接合
させた２つの半導体チップとアウタリードとをテープリ
ードにより接続した後、樹脂モールドを行う半導体装置
において、前記２つの半導体チップの背面間に間隙部を
形成させ、該間隙部を形成した該２つの半導体チップを
少なくとも１段設けることにより解決される。SUMMARY OF THE INVENTION In a semiconductor device in which two semiconductor chips having their back surfaces joined to each other and outer leads are connected by a tape lead and then resin molding is performed, the above-mentioned problems are solved between the back surfaces of the two semiconductor chips. This is solved by forming a gap and providing at least one stage of the two semiconductor chips having the gap.

【０００８】[0008]

【作用】上述のように、２つの半導体チップ間に間隙部
を形成している。従って、樹脂モールド時、この間隙部
にモールド樹脂が廻り込んで充填されることになる。As described above, the gap is formed between the two semiconductor chips. Therefore, at the time of resin molding, the mold resin wraps around and fills the gap.

【０００９】これにより、半導体チップの背面に水分の
進入やボイドの発生を回避することが可能となり、基板
実装時における熱ストレスの発生が抑られ、クラック等
の発生を防止することが可能となる。This makes it possible to prevent moisture from entering the back surface of the semiconductor chip and the generation of voids, suppress the occurrence of thermal stress during mounting on the substrate, and prevent the occurrence of cracks and the like. ..

【００１０】[0010]

【実施例】図１に、本発明の第１の実施例の構成図を示
す。なお、以下、図５と同一の構成部分には同一の符号
を付す。FIG. 1 is a block diagram of the first embodiment of the present invention. In addition, hereinafter, the same components as those in FIG. 5 are denoted by the same reference numerals.

【００１１】図１において、半導体装置１B は、中央開
口部を有するリードフレームのアウタリード６a の両面
上に、ＴＡＢ（TapeAutomated Bonding) における足曲
げ加工されたテープリード５A ，５B の一端が熱圧着に
より固着される。[0011] In FIG. 1, the semiconductor device 1 B is on both sides on the outer lead 6 a lead frame having a central opening, one end of the TAB foot in (TapeAutomated Bonding) bent tape lead 5 A, 5 B It is fixed by thermocompression bonding.

【００１２】また、テープリード５A ，５B の他端は、
バンプ４を介して第１及び第２の半導体チップ３A ，３
B と接続される。そして、モールド樹脂７によりモール
ドされる。The other ends of the tape leads 5 A and 5 B are
The first and second semiconductor chips 3 A , 3 via the bumps 4
Connected with B. Then, it is molded with the molding resin 7.

【００１３】この場合、テープリード５A ，５B の足曲
げ加工は、一断面略クランク形状に金型等の打抜き等に
より形成されるもので、打抜き時に足曲げ加工の度合い
がある程度設定される。すなわち、この足曲げの度合い
により、半導体チップ３A ，３B の背面間の間隙部８が
形成され、例えば幅数十μｍに形成される。そして、樹
脂モールド時には、この間隙部８にモールド樹脂７が廻
り込み充填されるものである。In this case, the foot bending of the tape leads 5 A and 5 B is performed by punching a metal mold or the like into a substantially one-section crank shape, and the degree of foot bending is set to some extent during punching. .. That is, the gap portion 8 between the back surfaces of the semiconductor chips 3 A and 3 B is formed depending on the degree of this foot bending, and is formed to have a width of several tens of μm, for example. Then, at the time of resin molding, the mold resin 7 is circulated and filled in the gap portion 8.

【００１４】そして、樹脂モールド後、リードフレーム
２のアウタリード６a が表面実装用のＬ型に折曲され
る。なお、本実施例以下では総て表面実装用のリードを
示しているが、Ｌ型（Ｊ型）に折曲せずにリード挿入用
としても同様である。[0014] Then, after the resin molding, the outer lead 6 a of the lead frame 2 is bent in the L-shaped for surface mounting. Although all the leads for surface mounting are shown in the present embodiment and the following, the same applies to leads for insertion without being bent into an L type (J type).

【００１５】このような半導体装置１B は、間隙部８に
モールド樹脂７が充填されることから、半導体チップ３
A ，３B の背面に水分が進入することがなく、ボイドの
発生や基板実装時の熱ストレスの発生を抑えることがで
きる。また、水分が進入することがなく、モールド樹脂
７との接触面積が増えることから、該モールド樹脂７と
の密着性が良好となり、半導体装置の信頼性を向上させ
ることができる。In such a semiconductor device 1 B , since the gap 8 is filled with the mold resin 7, the semiconductor chip 3
A, 3 without moisture from entering the back of the B, it is possible to suppress the generation of heat stress during development and board mounting voids. Further, since moisture does not enter and the contact area with the mold resin 7 increases, the adhesion with the mold resin 7 becomes good, and the reliability of the semiconductor device can be improved.

【００１６】次に、図２に、本発明の第２の実施例の構
成図を示す。図２における半導体装置１C は、２つの半
導体チップ３A ，３Bのそれぞれの背面に窒化膜９A ，
９B を形成したものである。この窒化膜９A ，９B の形
成は、例えばシリコンの半導体チップ３A ，３B の背面
にチッ素ガスを供給し、プラズマ放電により励起して薄
膜を形成するプラズマＣＶＤ（Chemical Vapor Deposit
ion)により行われる。このように、半導体チップ３A ，
３B の背面に窒化膜９A ，９B を形成することにより、
該背面とモールド樹脂７との密着性をさらに向上させる
ことができる。Next, FIG. 2 shows a block diagram of a second embodiment of the present invention. The semiconductor device 1 C shown in FIG. 2 has a nitride film 9 A on the back surface of each of the two semiconductor chips 3 A and 3 B.
9 B is formed. The nitride films 9 A and 9 B are formed, for example, by plasma CVD (Chemical Vapor Deposit) in which nitrogen gas is supplied to the back surface of the semiconductor chips 3 A and 3 B made of silicon and is excited by plasma discharge to form a thin film.
ion). In this way, the semiconductor chip 3 A ,
By forming the nitride films 9 A and 9 B on the back surface of 3 B ,
The adhesion between the back surface and the mold resin 7 can be further improved.

【００１７】なお、本実施例では窒化膜について述べた
が、イミド系膜（例えばスピンコート）、窒素酸化膜、
シリコン酸化膜等でもよい。Although the nitride film has been described in this embodiment, an imide film (for example, spin coating), a nitrogen oxide film,
It may be a silicon oxide film or the like.

【００１８】次に、図３に、本発明の第３の実施例の構
成図を示す。図３の半導体装置１D は、図２における半
導体チップ３A ，３Bの背面に形成された窒化膜９A ，
９B 間に固着部材（接着剤）１０を設けたものである。
この固着部材１０は、樹脂モールド時に２つの半導体チ
ップ３A ，３B の位置を安定させて間隙部８を確保する
ためのもので、該間隙部８の固着部材１０以外の部分に
モールド樹脂７を充填させ、水分の進入等を確実に防止
することができるものである。Next, FIG. 3 shows a block diagram of a third embodiment of the present invention. The semiconductor device 1 D shown in FIG. 3 has a nitride film 9 A formed on the back surface of the semiconductor chips 3 A , 3 B shown in FIG.
A fixing member (adhesive) 10 is provided between 9 B.
The fixing member 10 is for stabilizing the positions of the two semiconductor chips 3 A and 3 B during resin molding to secure the gap portion 8. The fixing resin 10 is provided on the portion other than the fixing member 10 of the gap portion 8 with the molding resin 7. It is possible to reliably prevent the entry of water and the like by filling the

【００１９】なお、固着部材１０は、絶縁性、導電性の
何れでもよく、導電性とした場合には接地系を同一する
ことにより電気的特性を安定させることができる。The fixing member 10 may be either insulative or conductive, and if it is conductive, the electrical characteristics can be stabilized by using the same grounding system.

【００２０】次に、図４に、本発明の第４の実施例の構
成図を示す。図４における半導体装置１E は、アウタリ
ード６b の一方面上に、背面間に間隙部８を形成した半
導体チップ３A ，３b をテープリード５A ，１１A によ
りバンプ４を介して接続する。また、アウタリード６b
の他方面上に、背面間に間隙部８を形成した半導体チッ
プ３C ，３D をテープリード５B ，１１B にバンプ４を
介して接続する。Next, FIG. 4 shows a block diagram of a fourth embodiment of the present invention. The semiconductor device 1 E in FIG. 4, on one side of the outer lead 6 b, connecting the semiconductor chip 3 A, 3 b forming the gap 8 between the back via the bumps 4 by the tape lead 5 A, 11 A .. Also, the outer lead 6 b
The semiconductor chips 3 C and 3 D having the gap portion 8 formed between the rear surfaces on the other surface of are connected to the tape leads 5 B and 11 B via the bumps 4.

【００２１】そして、モールド樹脂７により、モールド
した後、表面実装用としてアウタリード６b を「Ｊ」型
形状に折曲加工したものである。After molding with the molding resin 7, the outer leads 6 b are bent into a “J” shape for surface mounting.

【００２２】すなわち、本実施例の半導体装置１E は、
図１の２つの半導体チップを２段に構成したものであ
り、同様の効果を有する。また、図２に示すような半導
体チップ３A 〜３D の背面に窒化膜等を形成してもよ
く、間隙部８に固着部材１０を介在させても同様の効果
を有するものである。That is, the semiconductor device 1 E of this embodiment is
The two semiconductor chips of FIG. 1 are configured in two stages and have the same effect. Further, a nitride film or the like may be formed on the back surface of the semiconductor chips 3 A to 3 D as shown in FIG. 2, and the same effect can be obtained even if the fixing member 10 is interposed in the gap portion 8.

【００２３】[0023]

【発明の効果】以上のように本発明によれば、２つの半
導体チップの背面間に間隙部を形成し、適宜背面のそれ
ぞれに膜を形成することにより、モールド樹脂等との密
着性を良好にして実装時のパッケージのクラック等を防
止することができ、半導体装置の信頼性を向上させるこ
とができる。As described above, according to the present invention, a gap portion is formed between the back surfaces of two semiconductor chips, and a film is formed on each of the back surfaces as appropriate, so that the adhesion with the mold resin or the like is improved. Thus, it is possible to prevent cracks and the like in the package during mounting and improve the reliability of the semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例の構成図である。FIG. 1 is a configuration diagram of a first embodiment of the present invention.

【図２】本発明の第２の実施例の構成図である。FIG. 2 is a configuration diagram of a second embodiment of the present invention.

【図３】本発明の第３の実施例の構成図である。FIG. 3 is a configuration diagram of a third embodiment of the present invention.

【図４】本発明の第４の実施例の構成図である。FIG. 4 is a configuration diagram of a fourth embodiment of the present invention.

【図５】従来の半導体装置の構成図である。FIG. 5 is a configuration diagram of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１A 〜１E 半導体装置 ２ リードフレーム ３A 〜３D 半導体チップ ４ バンプ ５A ，５B ，１１A ，１１B テープリード ６a ，６b アウタリード ７ モールド樹脂 ８ 間隙部 ９a ，９b 窒化膜 １０ 固着部材1 A to 1 E Semiconductor device 2 Lead frame 3 A to 3 D Semiconductor chip 4 Bump 5 A , 5 B , 11 A , 11 B Tape lead 6 a , 6 b Outer lead 7 Mold resin 8 Gap 9 a , 9 b Nitriding Membrane 10 fixing member

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 背面を接合させた２つの半導体チップ
（３A 〜３D ）とアウタリード（６a ，６b ）とをテー
プリード（５A ，５B ，１１A ，１１B ）により接続し
た後、樹脂モールドを行う半導体装置において、 前記２つの半導体チップ（３A 〜３D ）の背面間に間隙
部（８）を形成させ、 該間隙部（８）を形成した該２つの半導体チップ（３A
〜３D ）を少なくとも１段設けることを特徴とする半導
体装置。1. Two semiconductor chips (3 A to 3 D ) whose back surfaces are bonded to each other and outer leads (6 a , 6 b ) are connected by tape leads (5 A , 5 B , 11 A , 11 B ). After that, in a semiconductor device in which resin molding is performed, a gap portion (8) is formed between the back surfaces of the two semiconductor chips (3 A to 3 D ), and the two semiconductor chips () having the gap portion (8) are formed. 3 A
Wherein a is provided at least one stage to 3 D). 【請求項２】 前記２つの半導体チップ（３A 〜３D ）
の背面のそれぞれに所定の膜（９A ，９B ）を形成する
ことを特徴とする請求項１記載の半導体装置。2. The two semiconductor chips (3 A to 3 D )
2. The semiconductor device according to claim 1, wherein a predetermined film (9 A , 9 B ) is formed on each of the back surfaces of the. 【請求項３】 前記２つの半導体チップ（３A 〜３D ）
の背面間に固着部材（１０）を設けることを特徴とする
請求項１又は２記載の半導体装置。3. The two semiconductor chips (3 A to 3 D )
3. The semiconductor device according to claim 1, wherein a fixing member (10) is provided between the back surfaces of the two.
JP3269644A 1990-03-15 1991-10-17 Semiconductor device Pending JPH05109978A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3269644A JPH05109978A (en) 1991-10-17 1991-10-17 Semiconductor device
US07/961,171 US5530292A (en) 1990-03-15 1992-10-16 Semiconductor device having a plurality of chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3269644A JPH05109978A (en) 1991-10-17 1991-10-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05109978A true JPH05109978A (en) 1993-04-30

Family

ID=17475222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3269644A Pending JPH05109978A (en) 1990-03-15 1991-10-17 Semiconductor device

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JP (1) JPH05109978A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5724233A (en) * 1993-07-09 1998-03-03 Fujitsu Limited Semiconductor device having first and second semiconductor chips with a gap therebetween, a die stage in the gap and associated lead frames disposed in a package, the lead frames providing electrical connections from the chips to an exterior of the packag
JP2001035994A (en) * 1999-07-15 2001-02-09 Toshiba Corp Semiconductor integrated-circuit device and system substratte
KR100483500B1 (en) * 1996-03-06 2006-05-04 제너랄 세미컨덕터 아일랜드 A frame for the fabrication of electronic components, a fabrication method of such components and components obtained thereby

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5724233A (en) * 1993-07-09 1998-03-03 Fujitsu Limited Semiconductor device having first and second semiconductor chips with a gap therebetween, a die stage in the gap and associated lead frames disposed in a package, the lead frames providing electrical connections from the chips to an exterior of the packag
KR100483500B1 (en) * 1996-03-06 2006-05-04 제너랄 세미컨덕터 아일랜드 A frame for the fabrication of electronic components, a fabrication method of such components and components obtained thereby
JP2001035994A (en) * 1999-07-15 2001-02-09 Toshiba Corp Semiconductor integrated-circuit device and system substratte

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