JP3115432B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3115432B2 JP3115432B2 JP04284415A JP28441592A JP3115432B2 JP 3115432 B2 JP3115432 B2 JP 3115432B2 JP 04284415 A JP04284415 A JP 04284415A JP 28441592 A JP28441592 A JP 28441592A JP 3115432 B2 JP3115432 B2 JP 3115432B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- external lead
- thermal expansion
- stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、基板に外部リードを
接合する際に熱ストレスの影響を受けないようにする半
導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which is not affected by thermal stress when connecting external leads to a substrate.
【０００２】[0002]
【従来の技術】図４は従来の半導体装置の構成を示す断
面図である。図において、１はＩＣチップ５を収納した
パッケージ４から導出され所定の形状に曲げられた外部
リード、２は実装するための基板、３は外部リード１と
基板２の接合部、４はパッケージ、５はＩＣチップ、６
はＩＣチップ５を取り付けるダイパット、７はＩＣチッ
プ５と外部リード１をつなぐ金線である。また、図中、
Ｗは半導体装置の全幅、ｗは外部リード１の基板２への
接合間隔である。2. Description of the Related Art FIG. 4 is a sectional view showing the structure of a conventional semiconductor device. In the drawing, reference numeral 1 denotes an external lead which is led out of a package 4 accommodating an IC chip 5 and is bent into a predetermined shape, 2 denotes a substrate for mounting, 3 denotes a joint between the external lead 1 and the substrate 2, 4 denotes a package, 5 is an IC chip, 6
Is a die pad for attaching the IC chip 5, and 7 is a gold wire connecting the IC chip 5 and the external lead 1. In the figure,
W is the total width of the semiconductor device, and w is the bonding interval of the external lead 1 to the substrate 2.
【０００３】次に作用について説明する。半導体装置
は、外部リード１を所定の形状に曲げた後、半田等の接
合剤によって外部リード１が基板２に接合され、電気的
及び機械的に接合固定される。Next, the operation will be described. In the semiconductor device, after the external lead 1 is bent into a predetermined shape, the external lead 1 is bonded to the substrate 2 by a bonding agent such as solder, and is electrically and mechanically fixed.
【０００４】[0004]
【発明が解決しようとする課題】従来の半導体装置は以
上の様に構成されているので、半導体装置を基板２に取
り付けた後、熱ストレスを受けると、基板２と半導体装
置の熱膨張係数の違いから外部リード１と基板２の接合
面に応力が生じ、外部リード１の接合間隔がある程度以
上広くなると剥離してしまう等の問題があった。すなわ
ち、接合時は高温となって膨張し、その後、収縮する
が、収縮の差が大きいと剥離してしまう。Since the conventional semiconductor device is constructed as described above, when the semiconductor device is mounted on the substrate 2 and subjected to thermal stress, the thermal expansion coefficient of the substrate 2 and the semiconductor device is reduced. Due to the difference, stress is generated on the joint surface between the external lead 1 and the substrate 2, and there is a problem that the external lead 1 peels off when the joint interval between the external leads 1 is increased to a certain extent or more. In other words, at the time of joining, the material expands at a high temperature and then contracts.
【０００５】この発明は上記の様な問題点を解決するた
めになされたもので、熱膨張係数の違いによって外部リ
ードと基板との接合面の剥離が起こらないようにする半
導体装置を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device capable of preventing separation of a bonding surface between an external lead and a substrate due to a difference in thermal expansion coefficient. Aim.
【０００６】[0006]
【０００７】[0007]
【課題を解決するための手段】この発明に係る半導体装
置は、ＩＣチップを収納したパッケージ両端から導出し
た相対する外部リードの基板への接合端部を装置の下部
中央線に沿って互い違いに配列して基板上に接合したも
のである。In a semiconductor device according to the present invention , bonding ends of opposing external leads to a substrate derived from both ends of a package containing an IC chip are alternately arranged along a lower center line of the device. And bonded on the substrate.
【０００８】[0008]
【０００９】[0009]
【作用】この発明における半導体装置は、外部リードの
基板への接合端部を装置の下部中央線に沿って互い違い
に配列して基板上に接合することにより、外部リードの
接合間隔をゼロにし基板の熱膨張を無関係にして、半導
体装置の熱膨張のみの応力が接合部に加わるようにして
応力を低減させる。In the semiconductor device according to the present invention , the bonding ends of the external leads are reduced to zero by arranging the bonding ends of the external leads to the substrate alternately along the lower center line of the device and bonding them to the substrate. Irrespective of the thermal expansion of the semiconductor device, the stress is reduced by applying only the thermal expansion stress of the semiconductor device to the joint.
【００１０】[0010]
【実施例】実施例１．以下、この発明の一実施例を図に
ついて説明する。図１において、１は外部リード、２は
基板、３は外部リード１と基板２の接合部、４はパッケ
ージ、５はＩＣチップ、６はＩＣチップを取り付けるダ
イパット、７はＩＣチップと外部リードをつなぐ金線で
ある。また、Ｗは半導体装置の全幅、ｗは外部リードの
基板への接合間隔である。[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is an external lead, 2 is a substrate, 3 is a junction between the external lead 1 and the substrate 2, 4 is a package, 5 is an IC chip, 6 is a die pad for attaching an IC chip, and 7 is an IC chip and an external lead. It is a gold wire to connect. W is the total width of the semiconductor device, and w is the bonding interval of the external lead to the substrate.
【００１１】次に作用について説明する。通常、半導体
装置と基板の熱膨張率の比はおよそ１対４であり、基板
の方が４倍ほど熱膨張率が大きい。従って、半導体装置
の全幅Ｗに対して、相対する外部リード１と基板２の接
合間隔ｗが４分の１になる様に、外部リード１を成形し
て半導体装置の下部中央付近の基板２上に接合すること
により、理論上、熱膨張による応力の発生が無く、外部
リードと基板の接合面での剥離は生じない。Next, the operation will be described. Usually, the ratio of the thermal expansion coefficients of the semiconductor device and the substrate is about 1: 4, and the thermal expansion coefficient of the substrate is about four times larger. Accordingly, the external lead 1 is formed on the substrate 2 near the lower center of the semiconductor device so that the bonding interval w between the external lead 1 and the substrate 2 is 1/4 of the entire width W of the semiconductor device. In theory, no stress is generated due to thermal expansion, and no separation occurs at the joint surface between the external lead and the substrate.
【００１２】実施例２．上記実施例１では、熱膨張によ
る外部リード１と基板２の接合部にかかる応力が理論上
ゼロになる場合で、かつ半導体装置よりも基板２の熱膨
張率が大きい場合を示したが、逆に、半導体装置の方が
熱膨張率が大きい場合でも同じ考え方が使える。Embodiment 2 FIG. In the first embodiment, the case where the stress applied to the joint between the external lead 1 and the substrate 2 due to thermal expansion is theoretically zero and the coefficient of thermal expansion of the substrate 2 is larger than that of the semiconductor device is shown. In addition, the same concept can be used even when the semiconductor device has a higher coefficient of thermal expansion.
【００１３】図２はこの発明の実施例２を示す図であ
り、半導体装置と基板の熱膨張率の比が５対４の場合を
示している。この場合、ｗ＝５／４Ｗとなる様に外部リ
ード１を成形すれば良い。FIG. 2 is a view showing Embodiment 2 of the present invention, and shows a case where the ratio of the coefficient of thermal expansion between the semiconductor device and the substrate is 5: 4. In this case, the external lead 1 may be formed so that w = 5 / 4W.
【００１４】実施例３．上記実施例１，２は、熱膨張に
よる外部リード１と基板２の接合部に係る応力が理論上
ゼロの場合を示したが、ゼロでなくてもなるべくゼロに
近づける工夫をすれば応力が低減される。図３にその一
例を示す。これは、外部リード１の接合間隔をゼロにし
て、基板２の熱膨張を無関係にし、半導体装置の熱膨張
のみの応力が外部リード１の接合部に加わるものであ
る。この場合、外部リード１の接合部は半導体装置の下
部中央線に沿って基板２上に互い違いに配列されてい
る。Embodiment 3 FIG. Embodiments 1 and 2 show the case where the stress on the joint between the external lead 1 and the substrate 2 due to thermal expansion is theoretically zero. Is done. FIG. 3 shows an example. This is to make the bonding interval of the external leads 1 zero, make the thermal expansion of the substrate 2 irrelevant, and apply only the thermal expansion stress of the semiconductor device to the bonding portion of the external leads 1. In this case, the joints of the external leads 1 are alternately arranged on the substrate 2 along the lower center line of the semiconductor device.
【００１５】[0015]
【００１６】[0016]
【発明の効果】以上のように、この発明によれば、外部
リードの基板への接合端部を装置の下部中央線に沿って
互い違いに配列して基板上に接合するので、外部リード
の接合間隔をゼロにし基板の熱膨張を無関係にして、半
導体装置の熱膨張のみの応力が接合部に加わるようにし
て応力を低減させることができるという効果がある。As described above , according to the present invention , since the joining ends of the external leads to the substrate are alternately arranged along the lower center line of the device and joined to the substrate, the external leads are joined. There is an effect that the stress can be reduced by setting the interval to zero and making the thermal expansion of the substrate irrelevant and applying only the thermal expansion stress of the semiconductor device to the joint.
【図１】この発明の実施例１による半導体装置を示す断
面図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
【図２】この発明の実施例２による半導体装置を示す断
面図である。FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図３】この発明の実施例３による半導体装置を示す断
面図である。FIG. 3 is a sectional view showing a semiconductor device according to Embodiment 3 of the present invention;
【図４】従来の半導体装置を示す断面図である。FIG. 4 is a sectional view showing a conventional semiconductor device.
１ 外部リード ２ 基板 ３ 外部リードと基板の接合部 ４ パッケージ ５ ＩＣチップ DESCRIPTION OF SYMBOLS 1 External lead 2 Substrate 3 Joint part of external lead and substrate 4 Package 5 IC chip
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 1/18 H01L 23/50 H01R 4/02 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H05K 1/18 H01L 23/50 H01R 4/02
Claims (1)
ら導出した相対する外部リードの基板への接合端部を装
置の下部中央線に沿って互い違いに配列して基板上に接
合したことを特徴とする半導体装置。The present invention is characterized in that bonding ends of opposite external leads derived from both ends of a package containing an IC chip to a substrate are alternately arranged along a lower center line of the device and bonded to the substrate. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04284415A JP3115432B2 (en) | 1992-10-22 | 1992-10-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04284415A JP3115432B2 (en) | 1992-10-22 | 1992-10-22 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000026473A Division JP2000232195A (en) | 2000-02-03 | 2000-02-03 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06132625A JPH06132625A (en) | 1994-05-13 |
| JP3115432B2 true JP3115432B2 (en) | 2000-12-04 |
Family
ID=17678267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04284415A Expired - Fee Related JP3115432B2 (en) | 1992-10-22 | 1992-10-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3115432B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6186947U (en) * | 1984-11-12 | 1986-06-07 | ||
| US4623577A (en) * | 1985-02-01 | 1986-11-18 | Allied Corporation | Circuit board made from cross-linked polycyanurate polymer, thermoplastic polymer and polyaramid fiber |
-
1992
- 1992-10-22 JP JP04284415A patent/JP3115432B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06132625A (en) | 1994-05-13 |
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