JPH0510992A

JPH0510992A - Phase difference measurement device

Info

Publication number: JPH0510992A
Application number: JP16675791A
Authority: JP
Inventors: Hideki Yoshitake; 英樹吉武; Yoshifumi Matsuoka; 芳文松岡
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 1991-07-08
Filing date: 1991-07-08
Publication date: 1993-01-19
Anticipated expiration: 2015-06-26
Also published as: JP3055225B2

Abstract

PURPOSE:To obtain a phase difference measurement device capable of exactly measuring even with the variation in the frequency of measured signals A1, A2. CONSTITUTION:Measured signals A1 and A2 are converted with wave rectifiers 1 and 2 to square waves V1 and V2 and a pulse V3 corresponding to the phase difference is formed by taking an exclusive logical sum. V3 is counted with standard clock pulse (first counter 7). On the other hand, V1 is counted with a second counter using the standard clock pulse. The quatient of the count value from the first counter 7 devided (devider 21) by the count value from the second counter 8 is the phase difference. A lead/lag decision unit 11 decides the lead and lag of the phase. A signal processor 9 outputs the above phase difference and the lead and lag of the phase as the phase difference measurement value.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は位相差計測装置に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference measuring device.

【０００２】[0002]

【従来の技術】従来の位相差計測装置の構成を図３に示
し、その測定原理を図３および図４に基づいて説明す
る。二つの被測定信号Ａ１，Ａ２をそれぞれ波形整形器
１２，１３に入力する。波形整形器１２，１３は入力信
号が正の時Ｈ（レベルがハイのこと、以下同様）を、負
の時Ｌ（レベルがロウのこと、以下同様）を出力するも
ので、被測定信号Ａ１，Ａ２はそれぞれＶ１，Ｖ２のよ
うに矩形波に変換される。排他的論理和回路１４と論理
積回路１５でＶ１，Ｖ２よりＡ１，Ａ２の位相差に相当
する位相差パルスＶ３を生成する。基準クロックパルス
発生器１９からの基準クロックパルスＣＫと位相差パル
スＶ３を論理積回路１６に入力し、その出力をカウンタ
１７に入力して位相差Ｖ３をデジタル値に変換する。カ
ウンタ１７による位相差のカウントはＶ１の立ち下がり
で終了するので、信号処理部１８ではＶ１の立ち下がり
後、カウンタ１７のカウント値を取り込み、ある比例定
数を掛けて位相差を算出し位相計測値とする。その後次
のカウント開始前にカウンタ１７をリセットする。位相
の進み遅れについてはＶ１よりＶ２が進んでいる時は
Ｈ、逆の時はＬを出力する進み遅れ判別器２０の出力信
号により信号処理部１８で判断し、位相差に正負符号を
付加する。図４は図３における各部の入力電圧，出力電
圧の波形を示している。2. Description of the Related Art The structure of a conventional phase difference measuring apparatus is shown in FIG. 3, and its measuring principle will be described with reference to FIGS. The two measured signals A1 and A2 are input to the waveform shapers 12 and 13, respectively. The waveform shapers 12 and 13 output H (when the level is high, the same applies hereinafter) when the input signal is positive, and L (when the level is low, apply similarly below) when the input signal is negative. , A2 are converted into rectangular waves like V1 and V2, respectively. The exclusive OR circuit 14 and the AND circuit 15 generate a phase difference pulse V3 corresponding to the phase difference between A1 and A2 from V1 and V2. The reference clock pulse CK from the reference clock pulse generator 19 and the phase difference pulse V3 are input to the AND circuit 16, and the output thereof is input to the counter 17 to convert the phase difference V3 into a digital value. Since the counting of the phase difference by the counter 17 ends at the falling edge of V1, the signal processing unit 18 fetches the count value of the counter 17 after the falling edge of V1 and calculates the phase difference by multiplying it by a certain proportional constant to obtain the phase measurement value. And After that, the counter 17 is reset before the start of the next counting. Regarding the lead or lag of the phase, the signal processing unit 18 makes a decision by the output signal of the lead / lag discriminator 20 which outputs H when V2 is ahead of V1 and outputs L when V2 is ahead, and adds a positive / negative sign to the phase difference. .. FIG. 4 shows the waveforms of the input voltage and the output voltage of each part in FIG.

【０００３】[0003]

【発明が解決しようとする課題】従来の位相差計測装置
では、二つの被測定信号の位相差のずれの時間幅を基準
クロックパルスでカウントすることにより計測を行って
いたので、固定の周波数でしか計測できなかった。ま
た、被測定信号の周波数が変動する場合は計測誤差を生
じていた。In the conventional phase difference measuring apparatus, the measurement is performed by counting the time width of the phase difference shift between the two signals under measurement with the reference clock pulse. I could only measure. Moreover, when the frequency of the signal under measurement fluctuates, a measurement error occurs.

【０００４】本発明は計測周波数の制限をなくし、被測
定信号の周波数が変動しても誤差を生じることなく計測
可能な位相差計測装置を提供することを目的としてい
る。An object of the present invention is to provide a phase difference measuring device which eliminates the limitation of the measurement frequency and can perform measurement without causing an error even if the frequency of the signal under measurement changes.

【０００５】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明の位相差計測装置は、第１および第２の交流
入力を矩形波Ｖ１およびＶ２に変換する第１および第２
の波形整形器と、このＶ１とＶ２を入力とする排他的論
理和回路と、この排他的論理和回路の出力とＶ１を入力
としてＶ１とＶ２の位相差Ｖ３を出力する第１の論理積
回路と、基準クロックパルス発生器と、基準クロックパ
ルスとＶ３を入力としてＶ３の期間に含まれる基準クロ
ックパルスを出力する第２の論理積回路と、この第２の
論理積回路から出力された基準クロックパルスをカウン
トする第１のカウンタと、基準クロックパルスとＶ１を
入力としてＶ１の期間に含まれる基準クロックパルスを
出力する第３の論理積回路と、この第３の論理積回路か
ら出力された基準クロックパルスをカウントする第２の
カウンタと、上記第１のカウンタのカウント値を第２の
カウンタのカウント値で割った値を出力する割り算器
と、上記第１および第２のカウンタを１周期ごとにリセ
ットする手段と、Ｖ１とＶ２を入力とし両者の進み遅れ
の関係を符号で出力する進み遅れ判別器とを備え、上記
割り算器の出力および進み遅れ判別器の出力を第１およ
び第２の交流入力の位相差計測値として出力している。In order to achieve the above object, the phase difference measuring apparatus of the present invention has first and second phase difference measuring devices for converting first and second AC inputs into rectangular waves V1 and V2.
Waveform shaper, an exclusive OR circuit which receives V1 and V2 as inputs, and a first AND circuit which outputs the output of this exclusive OR circuit and V1 as a phase difference V3 between V1 and V2. A reference clock pulse generator, a second AND circuit which receives the reference clock pulse and V3 and outputs a reference clock pulse included in the period V3, and a reference clock output from the second AND circuit. A first counter that counts pulses, a third AND circuit that inputs a reference clock pulse and V1 and outputs a reference clock pulse included in a period of V1, and a reference that is output from the third AND circuit. A second counter for counting clock pulses; a divider for outputting a value obtained by dividing the count value of the first counter by the count value of the second counter; And a lead / lag discriminator for inputting V1 and V2 and outputting the relation between the leading and trailing delays of both with a sign, and the output of the divider and the output of the lead / lag discriminator. Is output as a phase difference measurement value of the first and second AC inputs.

【０００６】[0006]

【作用】本発明は上記した構成で、二つのカウント値の
割り算で位相差を求めるので、被測定周波数が変動して
も測定誤差を生じない。According to the present invention, the phase difference is obtained by dividing the two count values with the above-described structure, so that a measurement error does not occur even if the frequency to be measured fluctuates.

【０００７】[0007]

【実施例】以下、本発明の実施例を図１，図２に沿って
詳細に説明する。二つの被測定信号Ａ１，Ａ２をそれぞ
れ第１および第２の波形整形器１，２に入力する。波形
整形器１，２は入力信号が正の時Ｈを、負の時Ｌを出力
するもので、被測定信号Ａ１，Ａ２はそれぞれＶ１，Ｖ
２のように矩形波に変換される。排他的論理和回路３と
第１の論理積回路４でＶ１，Ｖ２よりＡ１，Ａ２の位相
差に相当する位相差パルスＶ３を生成する。基準クロッ
クパルス発生器１０からの基準クロックパルスＣＫと位
相差パルスＶ３を第２の論理積回路５に入力しその出力
を第１のカウンタ７に入力して位相差Ｖ３をデジタル値
Ｖ７に変換する。一方波形整形器１の出力Ｖ１と基準ク
ロックパルスＣＫを第３の論理積回路６に入力しその出
力を第２のカウンタ８に入力してＶ１のパルス幅をデジ
タル値Ｖ８に変換する。割り算器２１は第１のカウンタ
７のカウント値Ｖ７を第２のカウンタ８のカウント値Ｖ
８で割り位相差の半周期（１８０°）に対する比率を求
める。カウンタ７，８のカウントはＶ１の立ち下がり時
点で終了するので、信号処理部９ではＶ１の立ち下がり
後、割り算器２１の出力値（Ｖ７／Ｖ８）を取り込み、
以下に示す演算によって位相差を算出し位相計測値とす
る。Embodiments of the present invention will be described in detail below with reference to FIGS. The two signals under test A1 and A2 are input to the first and second waveform shapers 1 and 2, respectively. The waveform shapers 1 and 2 output H when the input signal is positive, and output L when the input signal is negative, and the measured signals A1 and A2 are V1 and V, respectively.
It is converted into a rectangular wave like 2. The exclusive OR circuit 3 and the first AND circuit 4 generate a phase difference pulse V3 corresponding to the phase difference between A1 and A2 from V1 and V2. The reference clock pulse CK and the phase difference pulse V3 from the reference clock pulse generator 10 are input to the second AND circuit 5, and the output thereof is input to the first counter 7 to convert the phase difference V3 into a digital value V7. .. On the other hand, the output V1 of the waveform shaper 1 and the reference clock pulse CK are input to the third AND circuit 6, and the output thereof is input to the second counter 8 to convert the pulse width of V1 into a digital value V8. The divider 21 compares the count value V7 of the first counter 7 with the count value V7 of the second counter 8.
Divide by 8 to obtain the ratio of the phase difference to the half cycle (180 °). Since the counts of the counters 7 and 8 are finished at the falling edge of V1, the signal processing unit 9 fetches the output value (V7 / V8) of the divider 21 after the falling edge of V1.
The phase difference is calculated by the following calculation and used as the phase measurement value.

【０００８】位相差（°）＝１８０°×Ｖ７／Ｖ８その後次のカウント開始前にカウンタ７，８をリセット
する。位相の進み遅れについては、Ｖ１よりＶ２が進ん
でいる時はＨ、逆の時はＬを出力する進み遅れ判別器１
１の出力信号により信号処理部９で判断し、位相差に正
負符号を付加する。また上記信号処理部９の構成の一例
としてはハードウェアをマイクロコンピュータにて構成
し上記処理をソフトウェアによって行うようにしてもよ
い。図２は図１における各部の入力電圧，出力電圧の波
形の時間的経過を示すものである。Phase difference (°) = 180 ° × V7 / V8 After that, the counters 7 and 8 are reset before the start of the next counting. Regarding the phase lead / lag, a lead / lag discriminator 1 that outputs H when V2 is ahead of V1 and outputs L when V2 is ahead of V1
The signal processing unit 9 makes a determination based on the output signal of 1 and adds a sign to the phase difference. Further, as an example of the configuration of the signal processing unit 9, the hardware may be configured by a microcomputer and the above processing may be performed by software. FIG. 2 shows the time course of the waveforms of the input voltage and the output voltage of each part in FIG.

【０００９】なお、被測定信号の位相差の変動や被測定
信号のノイズ等により測定値が安定しない場合は毎回の
位相差の平均値を求めて位相計測値としてもよい。If the measured value is not stable due to fluctuations in the phase difference of the signal under measurement, noise in the signal under measurement, etc., the average value of the phase difference for each time may be obtained and used as the phase measurement value.

【００１０】[0010]

【発明の効果】以上のように本発明によれば、位相差を
被測定周波数に無関係に計測することができ、また被測
定周波数が変動しても測定誤差を生じない位相差計測装
置を提供することができる。As described above, according to the present invention, it is possible to measure a phase difference regardless of the frequency to be measured, and to provide a phase difference measuring device which does not cause a measurement error even if the frequency to be measured fluctuates. can do.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の位相差計測装置の構成を示すブロック
図FIG. 1 is a block diagram showing a configuration of a phase difference measuring device of the present invention.

【図２】本発明の位相差計測装置の動作を説明するタイ
ミングチャートFIG. 2 is a timing chart explaining the operation of the phase difference measuring device of the present invention.

【図３】従来の位相差計測装置の構成を示すブロック図FIG. 3 is a block diagram showing a configuration of a conventional phase difference measuring device.

【図４】従来の位相差計測装置の動作を説明するタイミ
ングチャートFIG. 4 is a timing chart illustrating the operation of a conventional phase difference measuring device.

【符号の説明】[Explanation of symbols]

１第１の波形整形器２第２の波形整形器３排他的論理和回路４第１の論理積回路５第２の論理積回路６第３の論理積回路７第１のカウンタ８第２のカウンタ９信号処理部（カウンタをリセットする手段）１０基準クロックパルス発生器１１進み遅れ判別器２１割り算器Ａ１第１の交流入力Ａ２第２の交流入力 1 1st waveform shaper 2 2nd waveform shaper 3 Exclusive OR circuit 4 1st AND circuit 5 5 2nd AND circuit 6 3rd AND circuit 7 1st counter 8 2nd Counter 9 Signal processing unit (means for resetting the counter) 10 Reference clock pulse generator 11 Lead / lag discriminator 21 Divider A1 First AC input A2 Second AC input

Claims

【特許請求の範囲】【請求項１】第１および第２の交流入力を矩形波Ｖ１お
よびＶ２に変換する第１および第２の波形整形器と、こ
のＶ１とＶ２を入力とする排他的論理和回路と、この排
他的論理和回路の出力とＶ１を入力としてＶ１とＶ２の
位相差Ｖ３を出力する第１の論理積回路と、基準クロッ
クパルス発生器と、基準クロックパルスとＶ３を入力と
してＶ３の期間に含まれる基準クロックパルスを出力す
る第２の論理積回路と、この第２の論理積回路から出力
された基準クロックパルスをカウントする第１のカウン
タと、基準クロックパルスとＶ１を入力としてＶ１の期
間に含まれる基準クロックパルスを出力する第３の論理
積回路と、この第３の論理積回路から出力された基準ク
ロックパルスをカウントする第２のカウンタと、上記第
１のカウンタのカウント値を第２のカウンタのカウント
値で割った値を出力する割り算器と、上記第１および第
２のカウンタを１周期ごとにリセットする手段と、Ｖ１
とＶ２を入力とし両者の進み遅れの関係を符号で出力す
る進み遅れ判別器とを備え、上記割り算器の出力および
進み遅れ判別器の出力を第１および第２の交流入力の位
相差計測値として出力する位相差計測装置。Claims: What is claimed is: 1. First and second waveform shapers for converting first and second alternating current inputs into rectangular waves V1 and V2, and exclusive logic having these V1 and V2 as inputs. An OR circuit, a first AND circuit that outputs the phase difference V3 between V1 and V2 by using the output of this exclusive OR circuit and V1 as an input, a reference clock pulse generator, and a reference clock pulse and V3 as inputs. A second AND circuit that outputs the reference clock pulse included in the period of V3, a first counter that counts the reference clock pulse output from the second AND circuit, and the reference clock pulse and V1 are input. A third AND circuit for outputting the reference clock pulse included in the period V1 as a signal, a second counter for counting the reference clock pulse output from the third AND circuit, and A divider that outputs a value obtained by dividing the count value of the first counter by the count value of the second counter; a means for resetting the first and second counters every cycle;
And V2 as an input, and a lead / lag discriminator that outputs a lead / lag relationship between the two with a sign. The output of the divider and the output of the lead / lag discriminator are the phase difference measurement values of the first and second AC inputs. Phase difference measuring device that outputs as.