JPH0487341A - Polycrystalline silicon thin-film transistor - Google Patents
Polycrystalline silicon thin-film transistorInfo
- Publication number
- JPH0487341A JPH0487341A JP20288790A JP20288790A JPH0487341A JP H0487341 A JPH0487341 A JP H0487341A JP 20288790 A JP20288790 A JP 20288790A JP 20288790 A JP20288790 A JP 20288790A JP H0487341 A JPH0487341 A JP H0487341A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- polycrystalline silicon
- tft
- tpt
- mobility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 25
- 239000010409 thin film Substances 0.000 title claims description 3
- 239000000758 substrate Substances 0.000 claims abstract description 45
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims 1
- 239000010453 quartz Substances 0.000 abstract description 12
- 238000010438 heat treatment Methods 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 4
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Chemical compound [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052810 boron oxide Inorganic materials 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000203 mixture Substances 0.000 abstract description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 22
- 239000010410 layer Substances 0.000 description 11
- 239000011521 glass Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005984 hydrogenation reaction Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多結晶シリコンの薄膜トランジスタ（以下ＴＰ
Ｔという）の基板に係り、特に大面積の基板上に多数個
のＴＰＴを形成する場合に適したＴＰＴ用の基板；二関
する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a polycrystalline silicon thin film transistor (hereinafter referred to as TP).
A substrate for TPT, which is particularly suitable for forming a large number of TPTs on a large-area substrate;
近年、液晶表示装置の駆動スイッチ素子や密着型イメー
ジセンサの駆動回路用素子として有用である多結晶シリ
コンを用いたＴＰＴの研究が進んでいる。In recent years, research has been progressing on TPT using polycrystalline silicon, which is useful as a drive switch element for liquid crystal display devices and a drive circuit element for contact image sensors.
これら多結晶シリコンを用いたＴＰＴを形成する基板と
して、従来石英基板が用いられていたが。A quartz substrate has conventionally been used as a substrate for forming TPT using polycrystalline silicon.
最近、６００℃以下の製造工程でも多結晶シリコンＴＰ
Ｔの作成が可能となり、低コストのガラス基板２例えば
コーニング社製のコーニング７０５９（商品番号）が用
いられるようになった。Recently, polycrystalline silicon TP can be used even in manufacturing processes at temperatures below 600°C.
It has become possible to create T, and a low-cost glass substrate 2 such as Corning 7059 (product number) manufactured by Corning Corporation has come to be used.
ところが、ＴＰＴの製造工程には複数回の熱処理とマス
クパターニングが繰り返されるため、特に大面積の基板
に多数個の多結晶シリコンＴＰＴを同時（−作成する場
合、基板の熱膨張係数が大きいと問題を生ずる。However, since the TPT manufacturing process involves repeating heat treatment and mask patterning multiple times, problems arise especially when creating a large number of polycrystalline silicon TPTs on a large substrate at the same time, especially if the substrate has a large coefficient of thermal expansion. will occur.
即ち、複数回のパターニングと熱処理を繰り返す時、熱
膨張状態の基板が元に戻らないうち（二。That is, when patterning and heat treatment are repeated multiple times, the thermally expanded substrate does not return to its original state (2).
次のマスク合せを行うこととなり、マスクの位置合わせ
が不正確になって製品の歩留りが著しく悪化する。The next mask alignment will be performed, and the mask alignment will become inaccurate, resulting in a significant deterioration in product yield.
後述の第１表に示す如く、ガラス基板では石英基板；二
比較して、その熱膨張係数は１桁以上も多く上記の問題
点を生じ易い。As shown in Table 1 below, glass substrates have thermal expansion coefficients that are one order of magnitude higher than those of quartz substrates, and are more likely to cause the above-mentioned problems.
一方９石英基板を用いると、上記の問題点は解決される
が２石英のコストが高いため、製品のコストアップとな
り、特に大面積基板Ｃ二は不適である０
従りて２本発明の目的は、多結晶シリコンＴＰＴの基板
として、低コストで、熱膨張係数が小さく、耐熱性のあ
る基板を提供するものである。On the other hand, if a quartz substrate is used, the above problems are solved, but the high cost of quartz increases the cost of the product, making it particularly unsuitable for large-area substrates. provides a polycrystalline silicon TPT substrate that is low cost, has a small coefficient of thermal expansion, and is heat resistant.
上記目的を達成するため２本発明者は鋭意研究の結果、
多結晶シリコンＴＰＴの基板として。In order to achieve the above object, the inventors of the present invention have conducted extensive research,
As a substrate for polycrystalline silicon TPT.
Ｓｉｇｈを８０〜９９．５％含有する材料を用いること
；二より２石英基板と同様に熱膨張係数が小さく。Use a material containing 80 to 99.5% Sigh; it has a small coefficient of thermal expansion similar to the 2-2 quartz substrate.
耐熱性があり、しかも石英基板より格段にコストを下げ
た製品を作成し得ることを見出した。We have discovered that it is possible to create a product that is heat resistant and at a much lower cost than a quartz substrate.
本発明の一実施例を第１図、第２図を参照して説明する
。An embodiment of the present invention will be described with reference to FIGS. 1 and 2.
第１図は本発明のＴＰＴの断面構造図、第２図は該ＴＰ
Ｔの製造工程説明図である。FIG. 1 is a cross-sectional structural diagram of the TPT of the present invention, and FIG. 2 is a sectional view of the TPT of the present invention.
It is a manufacturing process explanatory diagram of T.
図中、１は本発明の材料を用いた基板、２は多結晶シリ
コン膜、２−１．２−２はｎ＋型領領域あって、各々ソ
ース領域、ドレイン領域として作用する。３はゲート酸
化膜、４はゲート電極、５は酸化シリコン（ＳｉＯｚ）
から成る層間絶縁膜、６はアルミニウム（ＡＪ）配線層
、７は窒化シリコン膜、８は５ｉ（ｈ膜を示す。In the figure, 1 is a substrate made of the material of the present invention, 2 is a polycrystalline silicon film, and 2-1, 2-2 are n+ type regions, which act as a source region and a drain region, respectively. 3 is a gate oxide film, 4 is a gate electrode, 5 is silicon oxide (SiOz)
6 is an aluminum (AJ) wiring layer, 7 is a silicon nitride film, and 8 is a 5i (h film).
本発明においては多結晶シリコンＴＰＴを作成する基板
として、約８０〜９９．５％の８ｉ（ｈを含有する材料
２例えば、コーニング社製の商品番号７９１３の基板を
用いるものである。なお他の組成としては酸化ホウ素（
ＢｚＯｓ）、酸化アルミニウム（ｋｌｘ Ｏｓ ） 、
酸化バリウム（Ｂａｄ）が含まれる。In the present invention, a material 2 containing approximately 80 to 99.5% 8i (h), for example, a substrate manufactured by Corning Corporation, product number 7913, is used as a substrate for producing a polycrystalline silicon TPT. The composition is boron oxide (
BzOs), aluminum oxide (klxOs),
Contains barium oxide (Bad).
本発明の材料は第１表（−示す如く、熱膨張係数。The materials of the present invention are shown in Table 1 (-coefficient of thermal expansion as shown).
ＴＰＴの多結晶シリコン層中の電子の移動度において２
石英基板を用いた場合と遜色なく、シかもコスト：二お
いて石英基板の約１／、ｏですむＴＰＴを得ることが出
来る。The electron mobility in the polycrystalline silicon layer of TPT is 2.
It is possible to obtain a TPT that is comparable to the case where a quartz substrate is used, and costs about 1/2 of the cost of a quartz substrate.
動度は、後述のＴＰＴの製造工程（二おいて、アモルフ
ァスシリコン層を固相成長させる際の熱処理条件２二よ
っては望決定され、高温での熱処理がその移動度を増加
するものと考えられる。各基板材料；；よる固相成長条
件を第２表に示す。The mobility is determined by the heat treatment conditions during the solid phase growth of the amorphous silicon layer in the TPT manufacturing process (2) described below, and it is thought that heat treatment at high temperature increases the mobility. Table 2 shows the solid phase growth conditions for each substrate material.
第２表からも明らかな如く２本発明の基板を用いること
（＝より２石英基板と同様に同相成長の際に高温におけ
る熱処理が可能となり、それによって多結晶シリコン層
中の電子の移動度を大きくすることができ２本発明によ
り得られたＴＰＴの特性を向上させることができる。As is clear from Table 2, by using the substrate of the present invention (=2), it is possible to perform heat treatment at high temperatures during in-phase growth, similar to the quartz substrate, thereby increasing the mobility of electrons in the polycrystalline silicon layer. 2. The characteristics of the TPT obtained by the present invention can be improved.
なお２本発明で用いる基板の５ｉＯｚの含有量は。Note that the content of 5iOz in the substrate used in the present invention is as follows.
８０％未満であるとその熱膨張係数が大きくなりすぎ、
９９．５％以上；二なると、その材料のコストが高価に
なりすぎる。If it is less than 80%, the coefficient of thermal expansion will be too large,
99.5% or more; otherwise, the cost of the material becomes too expensive.
次に本発明の多結晶シリコンＴＰＴの製造工程を第２図
を参照しつつ説明する。Next, the manufacturing process of the polycrystalline silicon TPT of the present invention will be explained with reference to FIG.
（Ｉ） コーニング社製の商品番号７９１３の基板１
上（二減圧ＣＶＤ法で、基板温度５６０℃でアモルファ
スシリコン膜を例えば約１０００Ｘ堆積する。次にこの
アモルファスシリコン膜をＮ２９３囲気中で６００℃５
０時間熱処理後、さらに９５０℃で１時間熱処理し、固
相成長させて多結晶シリコン膜２とする。(I) Board 1 manufactured by Corning Corporation, product number 7913
Above (2) Deposit an amorphous silicon film at a substrate temperature of about 1000X using a low pressure CVD method at a substrate temperature of 560°C.Next, deposit this amorphous silicon film at 600°C in an N293 atmosphere.
After the heat treatment for 0 hour, the polycrystalline silicon film 2 is further heat treated at 950° C. for 1 hour to achieve solid phase growth.
（ＩＩ） この多結晶シリコン膜２（二第１のホトマ
スりを用いてパターニングを行い、島状にエツチングす
る（第２図（ａ）参照）。(II) This polycrystalline silicon film 2 (patterned using second photolithography and etched into an island shape (see FIG. 2(a)).
１）次にスパッタ法により、 ８ｉ（ｈから成るゲー
ト酸化膜３を例えば約５００Ｘの厚さに形成後。1) Next, a gate oxide film 3 made of 8i (h) is formed to a thickness of about 500X, for example, by sputtering.
減圧ＣＶＤ法で多結晶シリコン膜４′を２例えば約１０
００〜３０００Ｘ堆積する。Polycrystalline silicon film 4' is deposited by low pressure CVD method to
00-3000X deposit.
側 これらの２層を第２のホトマスクを用いてパターニ
ングを行い、ゲート電極４を形成する（第２図（１））
参照）。Side These two layers are patterned using a second photomask to form the gate electrode 4 (Fig. 2 (1))
reference).
閏 形成したゲート電極４をマスクとして、自己整合法
で、リン（Ｐ）イオンの注入を行い、ソース領域２−１
．ドレイン領域２−２を形成する。Using the formed gate electrode 4 as a mask, phosphorus (P) ions are implanted by a self-alignment method to form the source region 2-1.
．． A drain region 2-2 is formed.
（資） さらに注入したＰイオンの活性化を、約６００
℃の窒素雰囲気中で行い１次；ニスバッタ法で８ｉ （
ｈ膜から成る層間絶縁膜５を約１０００Ｘの厚さに形成
する（第２図（Ｃ）参照）。(Capital) Furthermore, the activation of the implanted P ions was
℃ in a nitrogen atmosphere; 8i (
An interlayer insulating film 5 made of an H film is formed to a thickness of about 1000× (see FIG. 2(C)).
■ この層間絶縁膜５に第３のホトマスクを用いてパタ
ーニングを行い、コンタクト窓を形成し。(2) This interlayer insulating film 5 is patterned using a third photomask to form a contact window.
Ｍ層を蒸着法またはスパッタ法により形成し。The M layer is formed by vapor deposition or sputtering.
約４５０℃で３０分間シンターする。Sinter at approximately 450°C for 30 minutes.
６１ＤＡＪ層に第４のホトマスクを用いてパターニング
を行い＋ＡＪ配線層６を形成する（第２図（ｄ）参照）
。The 61DAJ layer is patterned using a fourth photomask to form the +AJ wiring layer 6 (see FIG. 2(d)).
.
■ 水素化のための窒化シリコン膜７をプラズマＣＶＤ
法で１例えば２０００Ｘ堆積する（第２図（ｅ）参照）
。■ Plasma CVD silicon nitride film 7 for hydrogenation
Deposit 1, for example, 2000X using a method (see Figure 2(e)).
.
（３）次にテトラエトキシシラン（ＴＥＯ８’）を用い
るオゾンＣＶＤ法で、ピンホールの少ない緻密な５ｉＣ
ｈ膜８を堆積後、熱処理を施して、水素化処理し、第１
図の如き構造のＴＰＴとする。(3) Next, using the ozone CVD method using tetraethoxysilane (TEO8'), a dense 5iC with few pinholes was formed.
After depositing the h film 8, heat treatment is performed, hydrogenation treatment is performed, and the first
The TPT has a structure as shown in the figure.
上記実施例の製造工程からも明らかな如く、多結晶シリ
コンＴＰＴを作成するのに４回のホトマスクを使用して
パターニングを行い（工程ＩＩ、ＩＶ。As is clear from the manufacturing process of the above example, patterning was performed using a photomask four times to create the polycrystalline silicon TPT (steps II and IV).
■、■参照）、少くとも６回の熱処理（工程Ｉ。(see ■, ■), heat treatment at least six times (step I).
■、■、Ｘ参照）を行うことになり、基板の熱膨張係数
が太きいと、第１のホトマスクと第４のホトマスクの位
置合せが正確に行われなくなる。特に大面積の基板を用
いて多数個のＴＰＴを作成する場合に不都合が起り易い
が２本発明の基板を用いることにより解決できた。(see (1), (2), and In particular, inconveniences are likely to occur when a large number of TPTs are produced using a large-area substrate, but these problems can be solved by using the substrate of the present invention.
なお、上記実施例においては多結晶シリコンＴＰＴの製
造工程において保護膜を２層にして水素化処理を行う例
（二ついて説明したが１本発明はこれに限られず、Ｐイ
オンの活性化抜水素化処理を行い、酸化シリコン膜から
なる層間絶縁膜を形成する方法等、他の工程で製造する
こともできるのは云うまでもない。In addition, in the above-mentioned example, in the manufacturing process of polycrystalline silicon TPT, the protective film is made into two layers and the hydrogenation treatment is performed (although two layers were explained, the present invention is not limited to this, and Needless to say, it can be manufactured using other processes, such as a method of performing a chemical treatment and forming an interlayer insulating film made of a silicon oxide film.
本発明の如く多結晶シリコンＴＰＴを製造する基板とし
てＳｉ ０２の含有率が８０〜９９．５％という高い基
板を用いること（二より、熱膨張係数が小さく耐熱性が
あるので、従来のガラス基板を用いたものよりマスク合
せが容易かつ正確に出来る。従って、製品の特性および
歩留りを著しく向上させ・、ことができる。しかも電子
の移動度を、これまた前記ガラス基板を用いたものより
大きくできるのでこの点からも高性能のものとなる。As a substrate for manufacturing polycrystalline silicon TPT as in the present invention, a substrate with a high content of Si02 of 80 to 99.5% is used (secondly, because it has a small coefficient of thermal expansion and is heat resistant, it is better to use a substrate than a conventional glass substrate). Mask alignment is easier and more accurate than when using a glass substrate.Therefore, product characteristics and yield can be significantly improved.Furthermore, the electron mobility can also be made higher than when using a glass substrate. Therefore, from this point of view as well, it has high performance.
しかも該基板のコストが低いので、従来用いられていた
石英基板より約１／□。のコストで製造することか出来
る。Moreover, since the cost of the substrate is low, it is approximately 1/□ compared to the conventionally used quartz substrate. It can be manufactured at a cost of
特にこれらの効果は大面積の基板を用いた場合に顕著で
ある。These effects are particularly noticeable when a large-area substrate is used.
【図面の簡単な説明】
第１図は本発明の多結晶シリコンＴＰＴの断面構造図。
第２図は本発明のＴＰＴの製造工程説明図である０
１・・・本発明の基板、 ２・・・多結晶シリコン膜
。
２−１．２−２・・・ソース、ドレイン領域。
３・・・ゲート酸化膜、 ４・・・ゲート電極。
５・・・層間絶縁膜、 ６・・・Ｍ配線層。
７・・・窒化シリコン膜、８・・・８ｉ（ｈ［。
特許出願人 ティーデイ−ケイ株式会社代理人弁理士
山谷晧榮（外１名）
第２図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional structural diagram of the polycrystalline silicon TPT of the present invention. FIG. 2 is an explanatory diagram of the manufacturing process of TPT of the present invention. 0 1...Substrate of the present invention, 2... Polycrystalline silicon film. 2-1.2-2... Source, drain region. 3... Gate oxide film, 4... Gate electrode. 5... Interlayer insulating film, 6... M wiring layer. 7...Silicon nitride film, 8...8i (h[. Patent applicant: TDT-K Co., Ltd., patent attorney, Akira Yamatani (1 other person) Figure 2
Claims (1)
＿２）を含有する材料を用いたことを特徴とする多結晶
シリコン薄膜トランジスタ。As a substrate, 80-99.5% silicon oxide (SiO
A polycrystalline silicon thin film transistor characterized by using a material containing __2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20288790A JPH0487341A (en) | 1990-07-31 | 1990-07-31 | Polycrystalline silicon thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20288790A JPH0487341A (en) | 1990-07-31 | 1990-07-31 | Polycrystalline silicon thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0487341A true JPH0487341A (en) | 1992-03-19 |
Family
ID=16464849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20288790A Pending JPH0487341A (en) | 1990-07-31 | 1990-07-31 | Polycrystalline silicon thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0487341A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6441468B1 (en) | 1995-12-14 | 2002-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US6867434B2 (en) | 1995-11-17 | 2005-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix electro-luminescent display with an organic leveling layer |
-
1990
- 1990-07-31 JP JP20288790A patent/JPH0487341A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867434B2 (en) | 1995-11-17 | 2005-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix electro-luminescent display with an organic leveling layer |
| US6441468B1 (en) | 1995-12-14 | 2002-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US6445059B1 (en) | 1995-12-14 | 2002-09-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| KR100386204B1 (en) * | 1995-12-14 | 2003-06-09 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semicondoctor device |
| US6787887B2 (en) | 1995-12-14 | 2004-09-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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