JPH02199842A - Manufacture of thin-film field-effect transistor element - Google Patents
Manufacture of thin-film field-effect transistor elementInfo
- Publication number
- JPH02199842A JPH02199842A JP1913289A JP1913289A JPH02199842A JP H02199842 A JPH02199842 A JP H02199842A JP 1913289 A JP1913289 A JP 1913289A JP 1913289 A JP1913289 A JP 1913289A JP H02199842 A JPH02199842 A JP H02199842A
- Authority
- JP
- Japan
- Prior art keywords
- film
- amorphous
- insulating film
- amorphous semiconductor
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 17
- 239000010409 thin film Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000010408 film Substances 0.000 claims abstract description 114
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 47
- 238000005530 etching Methods 0.000 abstract description 25
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 21
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 230000001681 protective effect Effects 0.000 abstract description 3
- 229960002050 hydrofluoric acid Drugs 0.000 description 22
- 238000010306 acid treatment Methods 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 101100276210 Rhizobium meliloti (strain 1021) cya2 gene Proteins 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は絶縁性基板上に設けられた薄膜電界効果型トラ
ンジスタ素子の製造方法に関し、特にアクティブマトリ
ックス型液晶デイスプレィに好適な製造が容易な薄膜電
界効果型トランジスタ素子の製造方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film field effect transistor element provided on an insulating substrate, and in particular to a method for manufacturing a thin film field effect transistor element that is easy to manufacture and is suitable for active matrix type liquid crystal displays. The present invention relates to a method for manufacturing a field effect transistor element.
壁掛はカラーテレビに代表される薄型パネルデイスプレ
ィとして、薄膜電界効果型トランジスタを一方のガラス
基板に一つ一つ画素のスイッチとしてアレイ化したアク
ティブマトリックス型液晶デイスプレィの研究開発が活
発に行なわれている。このデイスプレィの実用化のため
には、量産時も製造歩留まりが減少しないようなプロセ
スマージンの大きい製造方法の開発が重要である。Wall-mounted displays are thin panel displays such as color TVs, and research and development is actively being conducted on active matrix liquid crystal displays, in which thin-film field-effect transistors are arrayed on one glass substrate, each as a switch for each pixel. There is. In order to put this display into practical use, it is important to develop a manufacturing method with a large process margin so that manufacturing yield does not decrease even during mass production.
第２図に従来の逆スタッガード型薄膜電界効果型トラン
ジスタの製造プロセスを示す。以下、この従来の製造プ
ロセスについて説明する。絶縁性基板２１上に金属でゲ
ート電極２２を形成する（第２図（ａ）＞ 、次に、プ
ラズマＣＶＤ法によりゲート絶縁ＪＩｅ１２３として窒
化シリコンや酸化シリコンのような絶縁膜を形成する。FIG. 2 shows a manufacturing process for a conventional inverted staggered thin film field effect transistor. This conventional manufacturing process will be explained below. A gate electrode 22 is formed of metal on an insulating substrate 21 (FIG. 2(a)). Next, an insulating film such as silicon nitride or silicon oxide is formed as a gate insulator JIe 123 by plasma CVD.
さらに、非晶質半導体として例えばアモルファスＳ ｉ
２４゜上部絶縁膜・２５を順次堆積させる（第２図（
ｂ））。この上部絶縁膜２５はゲート絶縁膜と同様に窒
化シリコン膜や酸化シリコン膜が用いられる。Furthermore, as an amorphous semiconductor, for example, amorphous Si
A 24° upper insulating film 25 is sequentially deposited (see Fig. 2).
b)). This upper insulating film 25 is made of a silicon nitride film or a silicon oxide film, similar to the gate insulating film.
次に上部絶縁膜２５をゲート電極２２上の一部を残して
、不用部分をエツチング除去する（第２図（Ｃ））。こ
こで、露出したアモルファス５ｉ２４の表面をフッ酸を
用いて清浄化し、ただちにｎ＋アモルファス５ｉ２６と
金属膜２７を成膜する（第２図（ｄ））、金属膜２７と
ｎ＋アモルファスＳＬをエツチング加工することにより
ソース２８とドレイン２９を形成する（第２図（ｅ））
。最後に、不用な部分のアモルファス５ｉ２４をエツチ
ング除去することにより、トランジスタが完成する。Next, unnecessary portions of the upper insulating film 25 are removed by etching, leaving a portion on the gate electrode 22 (FIG. 2(C)). Here, the exposed surface of the amorphous 5i24 is cleaned using hydrofluoric acid, and the n+ amorphous 5i26 and metal film 27 are immediately formed (FIG. 2(d)).The metal film 27 and the n+ amorphous SL are etched. By this, a source 28 and a drain 29 are formed (FIG. 2(e)).
. Finally, unnecessary portions of the amorphous layer 5i24 are removed by etching to complete the transistor.
従来の逆スタッガード型薄膜電界効果型トランジスタの
製造プロセスの問題点は、ｎ ＋アモルファスＳｌを成
膜する前に行なうアモルファス５ｔ２４の表面を清浄化
するためのフッ酸処理である。これは、アモルファスＳ
ｉ表面に形成されている酸化膜等を除去し、ソース・ト
レインコンタクトのオーミック性を改善するために行な
っている。しかし、この工程で上部絶縁膜２５がフッ酸
によりエツチングされることを防ぐため、フッ酸の濃度
を薄くし、処理時間の短くしている。このため、アモル
ファス５ｉ２４の表面状態によってはフッ酸処理が不十
分になり、オーミックコンタクトが形成できす、再現性
や歩留まりが悪い問題があった。A problem with the conventional manufacturing process for inverted staggered thin film field effect transistors is the hydrofluoric acid treatment to clean the surface of the amorphous 5t24 before forming the n + amorphous Sl film. This is amorphous S
This is done to remove the oxide film etc. formed on the i surface and improve the ohmic properties of the source/train contact. However, in order to prevent the upper insulating film 25 from being etched by hydrofluoric acid in this step, the concentration of hydrofluoric acid is reduced and the processing time is shortened. For this reason, depending on the surface condition of the amorphous 5i24, the hydrofluoric acid treatment may be insufficient, making it impossible to form an ohmic contact, resulting in poor reproducibility and yield.
本発明はこのような問題点を解決し、歩留りよく薄膜電
界効果トランジスタを作製することを目的としている、
〔課題を解決するための手段〕
本発明の薄膜電界効果型トランジスタ素子の製造方法は
、絶縁性基板上にゲート電極、ゲート絶縁膜、非晶質半
導体膜、上部絶縁膜を順次形成し、前記ゲート電極上以
外の部分の前記上部絶縁膜を除去した後、ソース及びド
レイン電極を形成する薄膜電界効果型トランジスタ素子
の製造方法において、前記上部絶縁膜の上に第２の非晶
質半導体膜を形成し、前記ゲート電極上以外の部分の前
記第２の非晶質半導体膜と前記上部絶縁膜を除去し、前
記ソース及びトレイン電極を形成し、最後に前記第２の
非晶質半導体膜を除去する工程を含むことを特徴として
いる。The present invention aims to solve these problems and manufacture thin film field effect transistors with high yield. [Means for Solving the Problems] The method for manufacturing a thin film field effect transistor element of the present invention includes A gate electrode, a gate insulating film, an amorphous semiconductor film, and an upper insulating film are sequentially formed on an insulating substrate, and after removing the upper insulating film in a portion other than on the gate electrode, a source and a drain electrode are formed. In the method for manufacturing a thin film field effect transistor element, a second amorphous semiconductor film is formed on the upper insulating film, and a portion of the second amorphous semiconductor film other than on the gate electrode and the upper part are separated from each other. The method is characterized by including the steps of removing the insulating film, forming the source and train electrodes, and finally removing the second amorphous semiconductor film.
本発明は上部絶縁膜がフッ酸処理でエツチングされるの
を防止するために、上部絶縁膜の上に第２の非晶質半導
体膜を形成し、この第２の非晶質半導体膜をフッ酸によ
るエツチングのストッパーとして利用する点に特徴があ
る。In the present invention, in order to prevent the upper insulating film from being etched by hydrofluoric acid treatment, a second amorphous semiconductor film is formed on the upper insulating film, and this second amorphous semiconductor film is then etched with fluoric acid. Its unique feature is that it can be used as a stopper for acid etching.
まず、本発明の逆スタッガード型薄膜電界効果型トラン
ジスタの製造プロセスについて説明する。第１図に本発
明の製造プロセスを示す、絶縁性基板１１上に金属でゲ
ート電極１２を形成する（第１図（ａ＞）、次に、プラ
ズマＣＶＤ法によりゲート絶縁膜１３として窒化シリコ
ンや酸化シリコンのような絶縁膜を形成する。さらに、
非晶質半導体層としてアモルファス５ｉ１４．上部絶縁
膜１５を順次堆積させる（第１図（ｂ））、この上部絶
縁膜１５はゲート絶縁膜と同様に窒化シリコン膜や酸化
シリコン膜が用いられる０本発明では、上部絶縁Ｍ１５
をフッ酸処理でエツチングされるのを防ぐために、上部
絶縁膜１５の上にさらに第２の非晶質半導体膜１を形成
する１１次に第２の非晶質半導体１１１１と上部絶縁膜
２５をゲート電極２２上のパターンのみを残しズ、不用
部分をエツチング除去する（第１図（Ｃ））、このエツ
チングは例えばまず非晶質半導体膜が速い条件で非晶質
半導体膜をドライエツチングし、次に上部絶縁膜が速い
条件で上部絶縁膜をドライエツチングでエツチングする
ことにより再現性、制御性よく加工することができる。First, the manufacturing process of the inverted staggered thin film field effect transistor of the present invention will be explained. FIG. 1 shows the manufacturing process of the present invention. A gate electrode 12 is formed of metal on an insulating substrate 11 (FIG. 1 (a>). Next, a gate insulating film 13 made of silicon nitride or silicone is formed by plasma CVD. Form an insulating film such as silicon oxide.Furthermore,
Amorphous 5i14. as the amorphous semiconductor layer. An upper insulating film 15 is sequentially deposited (FIG. 1(b)). This upper insulating film 15 is made of a silicon nitride film or a silicon oxide film like the gate insulating film. In the present invention, the upper insulating film 15 is
In order to prevent etching by hydrofluoric acid treatment, a second amorphous semiconductor film 1 is further formed on the upper insulating film 15. Next, the second amorphous semiconductor 1111 and the upper insulating film 25 are formed. Only the pattern on the gate electrode 22 is left, and unnecessary parts are removed by etching (FIG. 1(C)). This etching may be done, for example, by first dry etching the amorphous semiconductor film under conditions where the amorphous semiconductor film is fast; Next, the upper insulating film can be etched with good reproducibility and controllability by etching the upper insulating film by dry etching under conditions where the upper insulating film is fast.
ここで、露出したアモルファス５１１４の表面をフッ酸
を用いて清浄化し、なだち嫁ｎ＋アモルファス５ｉ１６
と金属膜１７を成膜する（第１図（ｄ））、金属膜１７
とｎ＋アモルファスＳＬをエツチング加工することによ
りソース２８とドレイン２９を形成するく第２図（ｅ）
）、この時、上部絶縁膜上の第２の非晶質半導体層はｎ
＋アモルファスシリコンのエツチング工程で連続してエ
ッチン、グされるｌｆ＆に、不用な部分のアモルファス
Ｓｔをエツチング除去することにより、トランジスタが
完成する。Here, the exposed surface of amorphous 5114 is cleaned using hydrofluoric acid, and Nadachi Yome n + Amorphous 5i16
and a metal film 17 (FIG. 1(d)).
By etching the n+ amorphous SL, the source 28 and drain 29 are formed (Fig. 2(e)).
), at this time, the second amorphous semiconductor layer on the upper insulating film is n
+A transistor is completed by etching away unnecessary portions of amorphous St in lf&, which is continuously etched in the amorphous silicon etching step.
ここで、第２の非晶質半導体膜１の役割について詳細に
説明する。第１図（ｃ）において上部絶縁［１５を除去
した後に現われるアモルファスＳｉ表面はレジストプロ
セスによる有機物汚染や酸化膜ができている。このため
、表面の特別な処理をせずにソース、ドレイン電極を形
成すると、ｎ＋層を用いてコンタクト抵抗が大きくなり
、オーミック電極にならない、アモルファスシリコン表
面の清浄化プロセスは再現性よく良好なトランジスタ特
性を得るのに必要不可決のものである。Here, the role of the second amorphous semiconductor film 1 will be explained in detail. In FIG. 1(c), the amorphous Si surface that appears after removing the upper insulator [15] has organic contamination and an oxide film formed by the resist process. For this reason, if source and drain electrodes are formed without special surface treatment, the contact resistance will increase using the n+ layer and the amorphous silicon surface will not become an ohmic electrode. It is indispensable to obtain the characteristic.
量産性に向き、確実な清浄化プロセスとして、フッ酸処
理がある。これは、適当な濃度のフッ酸で表面の酸化膜
をエツチングすることにより、表面の汚染も取り除ける
ため、非常に有効なプロセスである。しかし、プラズマ
ＣＶＤで作製した窒化シリコン膜やシリコン酸化膜はフ
ッ酸によるエツチングレートが非常に速いため、Ｓｉ表
面が清浄化される程度のフッ酸処理でも上部絶縁膜がエ
ツチングされてしまう。これまでは上部絶縁膜が無くな
らない程度にフッ酸濃度を薄くし、処理時間を短くして
清浄化処理を行なっている。そのなめ、アモルファスシ
リコン表面が十分清浄化されず、コンタクト特性の再現
性が悪かったり、面内で不均一性が発生したりして、歩
留まりの低下を引き起こす、そこで、フッ酸ではエツチ
ングされ難い第２の非晶質半導体膜、例えばアモルファ
スシリコン膜を上部絶縁膜の上に形成することにより、
フッ酸処理を十分行なうことができる。この第２の非晶
質半導体膜には、フッ酸に対するエツチングレートが遅
ければなんでもよく、例えばアモルファスシリコン膜を
使うことができる。Hydrofluoric acid treatment is a reliable cleaning process suitable for mass production. This is a very effective process because surface contamination can be removed by etching the oxide film on the surface with hydrofluoric acid at an appropriate concentration. However, since the etching rate of silicon nitride films and silicon oxide films produced by plasma CVD with hydrofluoric acid is very high, the upper insulating film is etched even when the hydrofluoric acid treatment is sufficient to clean the Si surface. Up to now, the cleaning process has been carried out by reducing the concentration of hydrofluoric acid to the extent that the upper insulating film is not lost and by shortening the processing time. As a result, the amorphous silicon surface is not sufficiently cleaned, resulting in poor reproducibility of contact characteristics and non-uniformity within the surface, resulting in a decrease in yield. By forming a second amorphous semiconductor film, for example, an amorphous silicon film, on the upper insulating film,
Hydrofluoric acid treatment can be carried out sufficiently. This second amorphous semiconductor film may be of any material as long as it has a slow etching rate with respect to hydrofluoric acid; for example, an amorphous silicon film may be used.
本発明の上部絶縁膜のエツチング防止層として非晶質半
導体を使用することにより、ｎ＋アモルファスＳｉ形成
前のフッ酸処理を十分行える。その結果、基板全体で再
現性よくソース・ドレインのオーミックコンタクトが形
成できるようになり、良好なＯＮ電流の均一性が得られ
る。By using an amorphous semiconductor as the etching prevention layer of the upper insulating film of the present invention, the hydrofluoric acid treatment before forming n+ amorphous Si can be carried out sufficiently. As a result, source/drain ohmic contacts can be formed over the entire substrate with good reproducibility, and good ON current uniformity can be obtained.
本発明の実施例について第１図を用いながら説明する。 An embodiment of the present invention will be described with reference to FIG.
絶縁性基板１１としてホウゲイ酸ガラス板を用いた。洗
浄後、絶縁性基板１１上にスパッタ法によりクロミウム
を厚さ１１００ｎ成膜し、フォトリソグラフィ法を用い
てゲート電極１２を形成する。ここでは、ゲート電極材
料としてクロミウムを用いたが他の材料、例えばアルミ
ニウムやタンタル等の他の金属でもよい。A borosilicate glass plate was used as the insulating substrate 11. After cleaning, a chromium film with a thickness of 1100 nm is formed on the insulating substrate 11 by sputtering, and a gate electrode 12 is formed using photolithography. Although chromium is used here as the gate electrode material, other materials such as aluminum, tantalum, and other metals may be used.
次に、プラズマＣＶＤ法を用いてゲート絶縁膜１３、ア
モルファス５ｉ１４．上部絶縁膜１５を順次成膜する。Next, the gate insulating film 13, amorphous 5i14. The upper insulating film 15 is sequentially formed.
ゲート絶縁膜１３には膜厚４００ｎｍの窒化シリコン膜
を用いた。成膜条件は、Ｓ ｉ Ｈ４とＮＨ，を原料ガ
スとして、流量比１ニア、真空度１００Ｐａ、高周波電
力密度０．２Ｗ ／ ３ ” 、基板温度２５０’Ｃで
あり、本条件で光学バンドギャップ５．４ｅＶの良好な
絶縁性を有する窒化シリコン膜が得られる。ここでは、
窒化シリコン膜を用いたが他の絶縁材料、例えば酸化シ
リコン、五酸化タンタル等の絶縁膜でもよい。A silicon nitride film with a thickness of 400 nm was used as the gate insulating film 13. The film forming conditions were as follows: S i H4 and NH were used as source gases, flow rate ratio was 1 near, vacuum degree was 100 Pa, high frequency power density was 0.2 W/3'', and substrate temperature was 250'C. Under these conditions, the optical band gap was 5. A silicon nitride film having good insulation properties of .4eV is obtained.Here,
Although a silicon nitride film is used, other insulating materials such as silicon oxide, tantalum pentoxide, etc. may be used.
アモルファス５ｉ１４は、Ｓ ｉ Ｈ４ガスを原料とし
、真空度１００Ｐａ、高周波電力密度０．０２Ｗ ／
ｃｔａ ２．基板温度２５０℃の条件で厚さ１１００ｎ
成膜した０次に、上部絶縁膜１５として、ゲート絶縁膜
１３と同じ条件で窒化シリコン膜を膜厚１１００ｎ成膜
した。上部絶縁膜１５は他の絶縁材料でもよい、ここで
は、プラズマＣＶＤ法を用いて、ゲート絶縁膜、アモル
ファスｓｉ、上部絶縁膜の３層を形成しているが、光Ｃ
ＶＤ法、スパッタ法等の他の成膜方法を用いてもよい。Amorphous 5i14 uses S i H4 gas as a raw material, has a vacuum degree of 100 Pa, and a high frequency power density of 0.02 W /
cta 2. Thickness 1100n at substrate temperature 250℃
Next, as the upper insulating film 15, a silicon nitride film was formed to a thickness of 1100 nm under the same conditions as the gate insulating film 13. The upper insulating film 15 may be made of other insulating materials.Here, three layers of the gate insulating film, amorphous Si, and the upper insulating film are formed using the plasma CVD method.
Other film forming methods such as VD method and sputtering method may be used.
次に、本発明の特徴である上部絶縁膜１５のエツチング
保護膜として、第２の非晶質半導体層１を膜厚２０ｎｍ
形成する。第２の非晶質半導体層の材料は例えばアモル
ファスｓｉでもよい、成膜方法もスパッタ法で形成して
もよい。Next, as an etching protection film for the upper insulating film 15, which is a feature of the present invention, a second amorphous semiconductor layer 1 is formed to a thickness of 20 nm.
Form. The material of the second amorphous semiconductor layer may be, for example, amorphous Si, and the film may be formed by sputtering.
次に、フォトリングラフィ法を用いてゲート電極の形状
にフォトレジスト膜を形成し、このフ才トレジスト膜を
マスクにして、アモルファスＳｉのエツチング速度が速
いエツチング条件で第２のアモルファスＳｉｌをエツチ
ングする。引続き逆に絶縁膜が速いエツチング条件に切
り替え上部絶縁膜をバターニングする。Next, a photoresist film is formed in the shape of the gate electrode using a photolithography method, and using this photoresist film as a mask, a second amorphous Sil is etched under etching conditions that allow for a high etching rate of the amorphous Si. . Subsequently, the etching conditions for the insulating film are changed to fast etching conditions, and the upper insulating film is patterned.
フォトレジスト膜の剥離後、アモルファス５ｔ１４の表
面の清浄化のために、１％ＨＦ液に１分間浸すフッ酸処
理を行なう、従来は上部絶縁膜１５をエツチングしない
ように０．０５％ＨＦ液に３０秒浸す処理しか行えなか
った。After peeling off the photoresist film, in order to clean the surface of the amorphous 5t 14, a hydrofluoric acid treatment is performed by dipping it in a 1% HF solution for 1 minute. Conventionally, it was soaked in a 0.05% HF solution to avoid etching the upper insulating film 15. I was only able to perform a 30 second soaking process.
このフッ酸処理後、ただちにプラズマＣＶＤ法を用いて
ｎ１アモルファス５ｉ１６．スパッタ法を用いてソース
・ドレインとなるクロミウムから成る金属膜１７を形成
する。ｎ＋アモルファスＳｉ １６の成膜は、ＰＨ，を
０．５％混合したＳｉＨ，を原料ガスに用い、真空度１
００Ｐａ、高周波電力密度０ 、０２ Ｗ／ ｃｙａ２
．基板温度２５０℃の条件で厚さ５Ｑｎｍ成膜した。ク
ロミウム１７の膜厚は１５０ｎｍである。Immediately after this hydrofluoric acid treatment, n1 amorphous 5i16. A metal film 17 made of chromium that will become the source and drain is formed using a sputtering method. To form a film of n+ amorphous Si 16, SiH mixed with 0.5% of PH was used as the raw material gas, and the degree of vacuum was 1.
00Pa, high frequency power density 0, 02W/cya2
．． A film with a thickness of 5 Qnm was formed at a substrate temperature of 250°C. The film thickness of chromium-17 is 150 nm.
ここで、フォトリソグラフィ法によりソース・ドレイン
の形状にフォトレジスト膜を形成し、電極となるクロミ
ウム１７をウェットエツチング法によりバターニングす
る。引き続き、ｎ＋アモルファスＳｔ １６と上部絶縁
膜１５を保護する第２の非晶質半導体であるアモルファ
スＳｉｌをドライエツチング法により連続してエツチン
グし、ソース・ドレイン１８．１９が形成される。この
２層は同一の条件でエツチングできるため、上部保護膜
１５のフッ酸処理の保護膜としてアモルファスＳｉｌを
用いてもエツチング工程の増加はない、最後に、アモル
ファスＳｉ １４の不用な部分をエツチング除去し、ト
ランジスタが完成する。Here, a photoresist film is formed in the shape of a source/drain by photolithography, and chromium 17, which will become an electrode, is patterned by wet etching. Subsequently, the n+ amorphous St 16 and the amorphous Sil, which is the second amorphous semiconductor that protects the upper insulating film 15, are continuously etched by dry etching to form the source/drain 18 and 19. Since these two layers can be etched under the same conditions, there is no increase in the etching process even if amorphous Sil is used as a protective film for the hydrofluoric acid treatment of the upper protective film 15.Finally, unnecessary portions of the amorphous Si 14 are removed by etching. The transistor is completed.
このような製造プロセスで作製した薄膜電界効果型トラ
ンジスタはフッ酸処理が十分長くできるため、ソース・
ドレインのオーミックコンタクトが確実に実現できその
結果、基板内で２５０１１Ｉｍ角の範囲でＯＮ電流の分
布が２０％以内に入り、良好な均一性が得られた。Thin-film field-effect transistors manufactured using this manufacturing process can be treated with hydrofluoric acid for a sufficiently long time, so the source and
The ohmic contact of the drain was reliably realized, and as a result, the ON current distribution was within 20% within a 25011 Im square area within the substrate, and good uniformity was obtained.
本発明は上部絶縁膜のエツチング防止層とじて非晶質半
導体膜を使用することにより、ｎ＋アモルファスＳｉ形
成前のフッ酸処理を十分行える。In the present invention, by using an amorphous semiconductor film as the etching prevention layer of the upper insulating film, the hydrofluoric acid treatment before forming n+ amorphous Si can be carried out sufficiently.
その結果、基板全体で再現性よくソース・ドレインのオ
ーミックコンタクトが形成できるようになり、良好なＯ
Ｎ電流の均一性が得られる。As a result, source/drain ohmic contacts can be formed with good reproducibility over the entire substrate, resulting in good O
Uniformity of N current can be obtained.
第１図は、本発明の薄膜電界効果型トランジスタの製造
工程図、第２図は、従来の薄膜電界効果型トランジスタ
の製造工程図をそれぞれ示す。
図において、
１１．２１・・・絶縁性基板、１２．２２・・・ゲート
電極、１３．２３・・・ゲート絶縁膜、１４．２４・・
・アモルファスＳｉ、１５．２５・・・上部絶縁膜、１
・・・第２の非晶質半導体膜、１６．２６・・・ｎ＋ア
モルファスＳｔ、１７．２７・・・金属膜、１８．２８
・・・ソース、１９．２９・・・ドレインをそれぞれ示
す。FIG. 1 shows a manufacturing process diagram of a thin film field effect transistor of the present invention, and FIG. 2 shows a manufacturing process diagram of a conventional thin film field effect transistor. In the figure, 11.21... Insulating substrate, 12.22... Gate electrode, 13.23... Gate insulating film, 14.24...
・Amorphous Si, 15.25... Upper insulating film, 1
...Second amorphous semiconductor film, 16.26...n+ amorphous St, 17.27...Metal film, 18.28
. . . source, 19.29 . . . drain, respectively.
Claims (1)
体膜、上部絶縁膜を順次形成し、前記ゲート電極上以外
の部分の前記上部絶縁膜を除去した後、ソース及びドレ
イン電極を形成する薄膜電界効果型トランジスタ素子の
製造方法において、前記上部絶縁膜の上に第２の非晶質
半導体膜を形成し、前記ゲート電極上以外の部分の前記
第２の非晶質半導体膜と前記上部絶縁膜を除去し、前記
ソース及びドレイン電極を形成し、最後に前記第２の非
晶質半導体膜を除去する工程を有することを特徴とした
薄膜電界効果型トランジスタ素子の製造方法。A gate electrode, a gate insulating film, an amorphous semiconductor film, and an upper insulating film are sequentially formed on an insulating substrate, and after removing the upper insulating film in a portion other than on the gate electrode, a source and a drain electrode are formed. In the method for manufacturing a thin film field effect transistor element, a second amorphous semiconductor film is formed on the upper insulating film, and a portion of the second amorphous semiconductor film other than on the gate electrode and the upper part are separated from each other. A method for manufacturing a thin film field effect transistor element, comprising the steps of removing an insulating film, forming the source and drain electrodes, and finally removing the second amorphous semiconductor film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1913289A JPH02199842A (en) | 1989-01-27 | 1989-01-27 | Manufacture of thin-film field-effect transistor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1913289A JPH02199842A (en) | 1989-01-27 | 1989-01-27 | Manufacture of thin-film field-effect transistor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02199842A true JPH02199842A (en) | 1990-08-08 |
Family
ID=11990941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1913289A Pending JPH02199842A (en) | 1989-01-27 | 1989-01-27 | Manufacture of thin-film field-effect transistor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02199842A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03148136A (en) * | 1989-11-02 | 1991-06-24 | Matsushita Electric Ind Co Ltd | Semiconductor element and manufacture thereof |
| EP0542279A1 (en) * | 1991-11-15 | 1993-05-19 | Casio Computer Company Limited | Thin-film transistor with a protective layer and method of manufacturing the same |
| KR100359796B1 (en) * | 1996-01-25 | 2003-01-15 | 엘지.필립스 엘시디 주식회사 | Thin film transistor for liquid crystal display and liquid crystal display |
| JP2011205105A (en) * | 2011-04-22 | 2011-10-13 | Casio Computer Co Ltd | Thin film transistor and method of manufacturing the same |
-
1989
- 1989-01-27 JP JP1913289A patent/JPH02199842A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03148136A (en) * | 1989-11-02 | 1991-06-24 | Matsushita Electric Ind Co Ltd | Semiconductor element and manufacture thereof |
| EP0542279A1 (en) * | 1991-11-15 | 1993-05-19 | Casio Computer Company Limited | Thin-film transistor with a protective layer and method of manufacturing the same |
| US5427962A (en) * | 1991-11-15 | 1995-06-27 | Casio Computer Co., Ltd. | Method of making a thin film transistor |
| KR100359796B1 (en) * | 1996-01-25 | 2003-01-15 | 엘지.필립스 엘시디 주식회사 | Thin film transistor for liquid crystal display and liquid crystal display |
| JP2011205105A (en) * | 2011-04-22 | 2011-10-13 | Casio Computer Co Ltd | Thin film transistor and method of manufacturing the same |
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