JPH04598B2 - - Google Patents
Info
- Publication number
- JPH04598B2 JPH04598B2 JP58178074A JP17807483A JPH04598B2 JP H04598 B2 JPH04598 B2 JP H04598B2 JP 58178074 A JP58178074 A JP 58178074A JP 17807483 A JP17807483 A JP 17807483A JP H04598 B2 JPH04598 B2 JP H04598B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode layer
- lower electrode
- layer
- silicon
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 10
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical group [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 13
- 239000003990 capacitor Substances 0.000 description 12
- 230000015654 memory Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
(ア) 発明の技術分野
本発明は、半導体装置、より詳しく述べるなら
ば、MOSダイナミツクRAM（ランダムアクセス
メモリ）の半導体メモリに関するものである。DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a semiconductor device, and more specifically, to a semiconductor memory such as a MOS dynamic RAM (random access memory).
(イ) 技術の背景
半導体メモリは近年ますます大容量化が進み、
MOSメモリの高集積化が図られている。MOSメ
モリの高集積化のために、メモリセルを１個の
MOSトランジスタと１個のキヤパシタとからな
るダイナミツク型の１トランジスタ型セルで構成
することは好ましい。この１トランジスタ型セル
においては、読み出し信号である読み出し、書込
みビツト線の電圧変化を大きくするためには、キ
ヤパシタの容量値とビツト線の浮遊容量値との比
を限られた面積内でできるだけ大きくすべきであ
る。(b) Technology background Semiconductor memories have become increasingly large in capacity in recent years.
MOS memory is becoming highly integrated. In order to increase the integration density of MOS memory, memory cells are reduced to one
It is preferable to use a dynamic one-transistor cell consisting of a MOS transistor and one capacitor. In this one-transistor type cell, in order to increase the voltage change of the read/write bit line, which is a read signal, the ratio of the capacitance value of the capacitor to the stray capacitance value of the bit line is made as large as possible within a limited area. Should.
(ウ) 従来技術と問題点
キヤパシタの容量値を大きくするために、キヤ
パシタの誘電体層に酸化シリコン（SiO2）の代
りに酸化タンタル（Ta2O5）を使用することが提
案された。このことは、Ta2O5の比誘電率は22〜
28で、SiO2の3.9と比べて非常に大きく。それだ
け小さなセル面積でも大きな電気量を蓄積するこ
とができるからである。(C) Prior art and problems In order to increase the capacitance value of a capacitor, it has been proposed to use tantalum oxide (Ta 2 O 5 ) instead of silicon oxide (SiO 2 ) for the dielectric layer of the capacitor. This means that the dielectric constant of Ta 2 O 5 is 22 ~
28, which is very large compared to 3.9 for SiO2 . This is because even a small cell area can store a large amount of electricity.
従来のTa2O5誘電体層を有する１トランジスタ
型ダイナミツクRAMセルは、例えば、第１図に
示すような構造である。MOSトランジスタは、
Ｐ型半導体基板１内に形成したn+領域（ドレイ
ン領域）２およびn+領域（ソース領域）３と、
ゲート酸化膜４上のポリシリコンゲート５とから
なり、そしてキヤパシタは、n+領域３と電気的
に接続されたポリシリコンの下側電極層６と、そ
の上のTa2O3誘電体層７と、さらにその上の上側
対向電極層８とからなる。下側電極層６はフイー
ルド酸化膜９およびゲート電極５を覆う絶縁膜１
０の上にも延びて、キヤパシタの容量を大きくと
るようになつている。そして、キヤパシタを覆う
絶縁膜１１およびビツト線（例えば、アルミニウ
ム配線）１２が形成されている。 A conventional one-transistor dynamic RAM cell having a Ta 2 O 5 dielectric layer has a structure as shown in FIG. 1, for example. MOS transistor is
An n + region (drain region) 2 and an n + region (source region) 3 formed in a P-type semiconductor substrate 1;
The capacitor consists of a polysilicon gate 5 on a gate oxide film 4, and a polysilicon lower electrode layer 6 electrically connected to the n + region 3, and a Ta 2 O 3 dielectric layer 7 thereon. and an upper counter electrode layer 8 thereon. The lower electrode layer 6 is an insulating film 1 that covers the field oxide film 9 and the gate electrode 5.
It also extends above 0 to increase the capacity of the capacitor. Then, an insulating film 11 and a bit line (for example, aluminum wiring) 12 are formed to cover the capacitor.
上述した構造でのTa2O5誘電体層７は、ポリシ
リコン下側電極層６の上にスパツタリング法又は
電子ビームによる加熱蒸発法でもつてタンタル
（Ta）膜を形成し、このTa膜を酸素雰囲気中で
500℃前後に加熱酸化することによつて形成され
る。しかしながら、Ta膜の形成時および酸化加
熱時にその下のシリコンがTa2O5膜中へ混入（拡
散）して誘電率が低下する問題がある。 The Ta 2 O 5 dielectric layer 7 in the above-described structure is formed by forming a tantalum (Ta) film on the polysilicon lower electrode layer 6 by sputtering or heating evaporation using an electron beam. in the atmosphere
It is formed by heating and oxidizing at around 500℃. However, there is a problem in that during the formation of the Ta film and oxidation heating, the underlying silicon mixes (diffuses) into the Ta 2 O 5 film, resulting in a decrease in the dielectric constant.
(エ) 発明の目的
本発明の目的は、上述したシリコンの酸化タン
タル（Ta2O5）誘電体層への混入をなくすことで
誘電率の低下を廻避することである。(d) Object of the Invention The object of the present invention is to avoid a decrease in the dielectric constant by eliminating the above-mentioned mixing of silicon into the tantalum oxide (Ta 2 O 5 ) dielectric layer.
本発明の別の目的は、酸化タンタルの特性を生
かしたキヤパシタを有する１トランジスタ型メモ
リセルを提供することである。 Another object of the present invention is to provide a one-transistor type memory cell having a capacitor that takes advantage of the characteristics of tantalum oxide.
(オ) 発明の構成
上述の目的およびその他の目的が、シリコン層
上に直接に形成され、シリコンを実質的に含ま
ず、かつシリコンの拡散に対してバリヤメタルと
なる下側電極層と；該下側電極層上に直接に形成
され、シリコンを実質的に含有しない酸化タンタ
ルからなる誘電体層と；該誘電体層上で、該下側
電極層に対向して形成された上側対向電極層と；
を含むキヤパシタを備えることを特徴とする半導
体装置によつて達成される。(E) Structure of the Invention The above object and other objects are achieved by providing a lower electrode layer which is formed directly on a silicon layer, substantially does not contain silicon, and serves as a barrier metal against diffusion of silicon; a dielectric layer formed directly on the side electrode layer and made of tantalum oxide that does not substantially contain silicon; an upper counter electrode layer formed on the dielectric layer and facing the lower electrode layer; ;
This is achieved by a semiconductor device characterized by comprising a capacitor including:
前述の下側電極層（バリヤメタル）には窒化タ
ンタル（TaN）又は窒化チタン（TiN）を用い
るのが好ましい。 It is preferable to use tantalum nitride (TaN) or titanium nitride (TiN) for the aforementioned lower electrode layer (barrier metal).
また、キヤパシタの上側対向電極層にはポリシ
リコン又は高融点金属（例えば、モリブデン又は
タングステン）を用いるのが好ましい。 Further, it is preferable to use polysilicon or a high melting point metal (for example, molybdenum or tungsten) for the upper counter electrode layer of the capacitor.
(カ) 発明の実施態様
以下、本発明の好ましい実施態様例によつて添
付図面を参照しながら本発明をより詳しく説明す
る。(f) Embodiments of the Invention The present invention will be described in more detail below by way of preferred embodiments of the invention with reference to the accompanying drawings.
本発明に係る半導体装置である半導体メモリの
ひとつのセルの構造は第１図に示した従来の半導
体メモリセルと同じであり、相違点は従来キヤパ
シタの下側電極層にポリシリコンを用いているの
を本発明ではそれに代えてバリヤメタル（例え
ば、TaN，TiN）を用いることである。 The structure of one cell of the semiconductor memory, which is a semiconductor device according to the present invention, is the same as that of the conventional semiconductor memory cell shown in FIG. 1, and the difference is that polysilicon is used for the lower electrode layer of the conventional capacitor. However, in the present invention, a barrier metal (eg, TaN, TiN) is used instead.
本発明に係る半導体メモリは次のようにして製
造される。 The semiconductor memory according to the present invention is manufactured as follows.
まず、Ｐ型半導体（シリコン）基板１を選択酸
化して厚いフイールド酸化膜（SiO2膜）９を形
成する。次に、薄いゲート酸化膜（SiO2膜）４
を熱酸化法で半導体基板１上に形成する。ポリシ
リコンを酸化膜９および４上の全面に析出させ、
所定パターンに選択エツチングしてゲート電極
（ワード線）５を形成する。次に、このポリシリ
コンゲート電極５および厚いフイールド酸化膜９
をマスクとしてＮ型不純物（リン、ヒソ）をイオ
ン注入してN+領域（ドレイン領域）２およびN+
領域（ソース領域）３を形成する。ポリシリコン
ゲート電極５を熱酸化してその表面に絶縁膜
（SiO3膜）１０を形成し、この加熱処理時にN+領
域２および３のアニーリングを行なう。次に、
N+領域３上の薄い酸化膜をエツチング除去して
N+領域３を露出させる。 First, a P-type semiconductor (silicon) substrate 1 is selectively oxidized to form a thick field oxide film (SiO 2 film) 9 . Next, a thin gate oxide film (SiO 2 film) 4
is formed on the semiconductor substrate 1 by a thermal oxidation method. Polysilicon is deposited on the entire surface of oxide films 9 and 4,
Gate electrodes (word lines) 5 are formed by selective etching into a predetermined pattern. Next, this polysilicon gate electrode 5 and the thick field oxide film 9 are
Using this as a mask, N-type impurities (phosphorous, hisso) are ion-implanted to form N + region (drain region) 2 and N +
A region (source region) 3 is formed. Polysilicon gate electrode 5 is thermally oxidized to form an insulating film (SiO 3 film) 10 on its surface, and during this heat treatment, N + regions 2 and 3 are annealed. next,
Etching and removing the thin oxide film on N + region 3
Expose N + region 3.
そして、本発明にて用いるバリヤメタル（例え
ば、窒化タンタル）をスパツタリング法によつて
全面に堆積させてN+領域３と電気的に接続され
たバリヤメタル層を厚さ、例えば、20ないし
50nmで形成する。このバリヤメタル層上に従来
と同様にTa層（厚さ：20ないし30nm）をスパツ
タリング法又は電子ビームによる加熱蒸発法で形
成する。次に、ドライ酸素（O2）雰囲気中で加
熱（500℃にて40分間）してTa層をTa2O5層（厚
さ：40ないし60nm）にする。このTa2O5層上に
ポリシリコン層を析出させる。そして、所定パタ
ーンのレジスト膜（図示せず）をマスクとした選
択エツチングによつて、形成したポリシリコン
層、Ta2O5層およびバリヤメタル層を順次エツチ
ング除去して、第１図に示すように、ポリシリコ
ンの上側対向電極層８、Ta2O5誘電体層７および
TaN下側電極層６を形成する。次に、層間絶縁
膜１１をPSG，Si3N4又はSiO2の析出および選択
エツチングで形成する。N+領域２上の薄い酸化
膜をエツチング除去してから、アルミニウム蒸着
層を形成し、所定のビツト線パターンに選択エツ
チングして配線１２を形成することで、第１図に
示した１トランジスタ型メモリセルが得られる。 Then, a barrier metal (for example, tantalum nitride) used in the present invention is deposited on the entire surface by sputtering to form a barrier metal layer electrically connected to the N + region 3 to a thickness of, for example, 20 to 20 mm.
Formed at 50nm. A Ta layer (thickness: 20 to 30 nm) is formed on this barrier metal layer by the sputtering method or the heating evaporation method using an electron beam as in the conventional method. The Ta layer is then heated in a dry oxygen (O 2 ) atmosphere (at 500° C. for 40 minutes) to turn the Ta layer into 5 layers of Ta 2 O (thickness: 40 to 60 nm). A polysilicon layer is deposited on this Ta 2 O 5 layer. Then, by selective etching using a prescribed pattern of resist film (not shown) as a mask, the formed polysilicon layer, Ta 2 O 5 layer, and barrier metal layer were sequentially etched away, as shown in FIG. , an upper counter electrode layer 8 of polysilicon, a Ta 2 O 5 dielectric layer 7 and
A TaN lower electrode layer 6 is formed. Next, an interlayer insulating film 11 is formed by depositing PSG, Si 3 N 4 or SiO 2 and selectively etching. After removing the thin oxide film on the N + region 2 by etching, an aluminum evaporation layer is formed and selectively etched into a predetermined bit line pattern to form the wiring 12. A memory cell is obtained.
(キ) 発明の効果
キヤパシタの下側電極層にバリヤメタルを使用
するのでシリコンの混入拡散によるTaO3誘電体
の誘電率低下の問題は生じない。さらに、N+領
域と下側電極層とのコンタクト抵抗は、従来のポ
リシリコン層では100μΩ―cm程度であつたのが
バリヤメタルでは数十μΩ―cmと大幅に減少する
利点がある。(G) Effects of the Invention Since a barrier metal is used for the lower electrode layer of the capacitor, there is no problem of a decrease in the dielectric constant of the TaO 3 dielectric due to the mixing and diffusion of silicon. Furthermore, the contact resistance between the N + region and the lower electrode layer has the advantage of being significantly reduced from about 100 μΩ-cm in the conventional polysilicon layer to several tens of μΩ-cm in the case of the barrier metal.
第１図は１トランジスタ型RAMセルの概略断
面図である。
１…Ｐ型半導体基板、２，３…N+領域、５…
ポリシリコンゲート電極、６…下側電極層、７…
誘電体層、８…上側対応電極層、９…フイールド
酸化膜、１２…配線。
FIG. 1 is a schematic cross-sectional view of a one-transistor type RAM cell. 1... P-type semiconductor substrate, 2, 3... N + region, 5...
polysilicon gate electrode, 6...lower electrode layer, 7...
Dielectric layer, 8... Upper corresponding electrode layer, 9... Field oxide film, 12... Wiring.
Claims (1)
実質的に含まず、かつシリコンの拡散に対してバ
リヤメタルとなる下側電極層と、 該下側電極層上に直接に形成され、シリコンを
実質的に含有しない酸化タンタルからなる誘電体
層と、 該誘電体層上で、該下側電極層に対向して形成
された上側対向電極層と、 を含むキヤパシタを備えることを特徴とする半導
体装置。 ２ 前記下側電極層が窒化タンタル又は窒化チタ
ンである特許請求の範囲第１項に記載の半導体装
置。[Scope of Claims] 1. A lower electrode layer formed directly on a silicon layer, substantially free of silicon, and serving as a barrier metal against silicon diffusion; and a lower electrode layer formed directly on the lower electrode layer. a dielectric layer made of tantalum oxide that does not substantially contain silicon; and an upper counter electrode layer formed on the dielectric layer to face the lower electrode layer. Characteristic semiconductor devices. 2. The semiconductor device according to claim 1, wherein the lower electrode layer is tantalum nitride or titanium nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58178074A JPS6072261A (en) | 1983-09-28 | 1983-09-28 | Semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58178074A JPS6072261A (en) | 1983-09-28 | 1983-09-28 | Semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6072261A JPS6072261A (en) | 1985-04-24 |
| JPH04598B2 true JPH04598B2 (en) | 1992-01-08 |
Family
ID=16042159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58178074A Granted JPS6072261A (en) | 1983-09-28 | 1983-09-28 | Semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6072261A (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62136035A (en) * | 1985-12-10 | 1987-06-19 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH01225149A (en) * | 1988-03-04 | 1989-09-08 | Toshiba Corp | Capacitor and manufacture thereof |
| US5087951A (en) * | 1988-05-02 | 1992-02-11 | Micron Technology | Semiconductor memory device transistor and cell structure |
| JPH0736438B2 (en) * | 1988-08-25 | 1995-04-19 | 日本電気株式会社 | Semiconductor device |
| KR920004541B1 (en) * | 1989-05-30 | 1992-06-08 | 현대전자산업 주식회사 | Contact forming method using etching barrier |
| JP2673385B2 (en) * | 1989-10-26 | 1997-11-05 | 三菱電機株式会社 | Semiconductor device |
| JP3021800B2 (en) * | 1990-07-24 | 2000-03-15 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof |
| JP2621609B2 (en) * | 1990-07-31 | 1997-06-18 | 日本電気株式会社 | Semiconductor device having charge storage capacitor and method of manufacturing the same |
| JPH0496270A (en) * | 1990-08-03 | 1992-03-27 | Sharp Corp | Manufacture of semiconductor device |
| JPH04177760A (en) * | 1990-11-09 | 1992-06-24 | Matsushita Electric Ind Co Ltd | Semiconductor storage device and its manufacture |
| US5283453A (en) * | 1992-10-02 | 1994-02-01 | International Business Machines Corporation | Trench sidewall structure |
| KR100269278B1 (en) * | 1992-10-14 | 2000-10-16 | 윤종용 | Method for manufacturing capacitor using ferroelectric thin film |
| TW241392B (en) * | 1993-04-22 | 1995-02-21 | Ibm | |
| JPH0797008A (en) * | 1993-09-24 | 1995-04-11 | Murata Mach Ltd | Article transfer device |
| JP2897631B2 (en) * | 1993-12-28 | 1999-05-31 | 日本電気株式会社 | Semiconductor integrated circuit device and manufacturing method |
| KR100215867B1 (en) * | 1996-04-12 | 1999-08-16 | 구본준 | Capacitor of semiconductor device and its fabrication method |
| KR20010008432A (en) * | 1998-12-30 | 2001-02-05 | 김영환 | Method for manufacturing capacitor having high dielectric ta2o5 thin film |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56147470A (en) * | 1980-04-17 | 1981-11-16 | Nec Corp | Semiconductor device |
| JPS57120295A (en) * | 1981-01-17 | 1982-07-27 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPS5810852A (en) * | 1981-07-10 | 1983-01-21 | Fujitsu Ltd | Semiconductor device |
-
1983
- 1983-09-28 JP JP58178074A patent/JPS6072261A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56147470A (en) * | 1980-04-17 | 1981-11-16 | Nec Corp | Semiconductor device |
| JPS57120295A (en) * | 1981-01-17 | 1982-07-27 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPS5810852A (en) * | 1981-07-10 | 1983-01-21 | Fujitsu Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6072261A (en) | 1985-04-24 |
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