JPH0457020B2 - - Google Patents
Info
- Publication number
- JPH0457020B2 JPH0457020B2 JP60154548A JP15454885A JPH0457020B2 JP H0457020 B2 JPH0457020 B2 JP H0457020B2 JP 60154548 A JP60154548 A JP 60154548A JP 15454885 A JP15454885 A JP 15454885A JP H0457020 B2 JPH0457020 B2 JP H0457020B2
- Authority
- JP
- Japan
- Prior art keywords
- carry
- signal line
- transistor
- carry signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000001902 propagating effect Effects 0.000 claims description 3
- 238000007599 discharging Methods 0.000 claims 1
- 230000000644 propagated effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3872—Precharge of output to prevent leakage
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野〕
この発明は、算術論理演算ユニツト（以下
ALUと称す）で演算を行う際に生じるキヤリイ
の伝搬回路に関するものである。[Detailed Description of the Invention] (Industrial Application Field) This invention relates to an arithmetic and logic operation unit (hereinafter referred to as
This relates to the carry propagation circuit that occurs when performing calculations in the ALU (ALU).
第３図は従来のマンチエスター型キヤリイ伝搬
回路の前ビツトのプリチヤージ部と、その次のビ
ツトのキヤリイ伝搬部を示す図であり、図におい
て、１は電源（5V），２はGND（0V），４は前段
のキヤリイ信号，５は次段へのキヤリイ伝搬信
号，６〜８はそれぞれキヤリイ伝搬用トランジス
タのソース，ゲート，ドレイン，９はキヤリイ信
号線，１２はプリチヤージ用PMOS型トランジ
スタ，１３はプリチヤージ用クロツク信号Φp，
１７はインバーターゲート，１８は排他的論理和
ゲート（論理回路）である。
Figure 3 is a diagram showing the precharge section for the previous bit and the carry propagation section for the next bit in a conventional Muntier star type carry propagation circuit. In the figure, 1 is the power supply (5V) and 2 is the GND (0V). , 4 is a carry signal in the previous stage, 5 is a carry propagation signal to the next stage, 6 to 8 are the sources, gates, and drains of carry propagation transistors, 9 is a carry signal line, 12 is a PMOS type transistor for precharge, and 13 is a carry propagation signal. Precharge clock signal Φp,
17 is an inverter gate, and 18 is an exclusive OR gate (logic circuit).
次にこの回路の動作について説明する。この回
路は、ALUの演算で、前段からのキヤリイ信号
をそのまま次段へ伝搬する働きをしている。これ
を詳しく説明すると、キヤリイを伝搬する前に、
まずキヤリイ信号線９はプリチヤージ用クロツク
信号１３に同期してＨレベル（5V）にプリチヤ
ージされており、ここで前ビツトの演算の結果そ
のビツトからキヤリイが発生すると、前段のキヤ
リイ信号４がＨレベルになり、キヤリイ信号線９
はＬレベルに設定される。このとき次段へのキヤ
リイ伝搬信号５がＨレベルになると、キヤリイ信
号線９のキヤリイ信号が次段へ伝搬される。 Next, the operation of this circuit will be explained. This circuit works by propagating the carry signal from the previous stage to the next stage as is during ALU calculations. To explain this in detail, before propagating the carrier,
First, the carry signal line 9 is precharged to H level (5V) in synchronization with the precharge clock signal 13, and when a carry occurs from that bit as a result of the calculation of the previous bit, the carry signal 4 at the previous stage goes to the H level. Then, carry signal line 9
is set to L level. At this time, when the carry propagation signal 5 to the next stage becomes H level, the carry signal on the carry signal line 9 is propagated to the next stage.
また、各ビツトの演算はそれぞれのキヤリイ信
号線９の値が定まつた後に開始され、これはイン
バータゲート１７を経て得られた次段へのキヤリ
イ伝搬信号５の反転信号とキヤリイ信号線９の値
との排他的論理和をとつて行なわれる。 Further, the calculation of each bit is started after the value of each carry signal line 9 is determined, and this is based on the inverted signal of the carry propagation signal 5 to the next stage obtained through the inverter gate 17 and the inverted signal of the carry signal line 9. This is done by exclusive ORing with the value.
従来のマンチエスター型キヤリイ伝搬回路は以
上のように構成されているので、キヤリイ伝搬用
トランジスタのゲート７にＨレベルの信号が加え
られ、これにより上位ビツトへキヤリイ信号線９
のレベルは伝搬される。ここで各ビツトのキヤリ
イ信号線９はプリチヤージ期間にＨレベルになる
のでキヤリイ信号線９のＨレベルを伝搬すること
はなく、キヤリイ信号線９がＬレベルの場合に限
り、そのレベルがそのキヤリイ伝搬用トランジス
タを通して伝搬されている。この場合、キヤリイ
信号線９はプリチヤージ期間にＨレベル（5V）
になつており、この状態で前段のキヤリイ信号４
がＨレベルになると、キヤリイ信号線９はデイス
チヤージし始める。このときキヤリイ伝搬信号５
がＨレベルになつてもキヤリイ信号線９の電圧が
キヤリイ信号伝搬用トランジスタのゲート７電圧
に対して該トランジスタの閾値電圧Vth以上低く
なるまでこの伝搬用トランジスタはオンしない。
このため、キヤリイ伝搬信号５がアクテイブにな
つてからキヤリイ伝搬用トランジスタがオンする
までの時間がむだになり、キヤリイ伝搬信号５が
全ビツト同時に設定されてもキヤリイ信号線９の
レベルが最終的なキヤリイ伝搬出力となるまでに
はかなりの時間が必要となり、その結果演算速度
が遅くなるという問題点があつた。
Since the conventional Muntier star type carry propagation circuit is configured as described above, an H level signal is applied to the gate 7 of the carry propagation transistor, thereby transmitting the carry signal line 9 to the upper bit.
The level of is propagated. Here, since the carry signal line 9 of each bit becomes H level during the precharge period, the H level of the carry signal line 9 is not propagated, and only when the carry signal line 9 is L level, that level is transmitted to the carry signal line 9. is propagated through the transistor. In this case, the carry signal line 9 is at H level (5V) during the precharge period.
In this state, the carry signal 4 of the previous stage is
When the signal becomes H level, the carry signal line 9 starts to discharge. At this time, the carry propagation signal 5
Even if becomes H level, this propagation transistor is not turned on until the voltage of the carry signal line 9 becomes lower than the gate 7 voltage of the carry signal propagation transistor by more than the threshold voltage Vth of the transistor.
For this reason, the time from when the carry propagation signal 5 becomes active until the carry propagation transistor turns on is wasted, and even if all bits of the carry propagation signal 5 are set at the same time, the level of the carry signal line 9 may not reach the final level. A considerable amount of time is required to reach the carry propagation output, resulting in a problem that the calculation speed becomes slow.
この発明では、上記のような問題点を解決する
ためになされたもので、キヤリイ信号線のキヤリ
イ信号を高速に伝搬できるマンチエスター型キヤ
リイ伝搬回路を得ることを目的とする。 The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a Muntier star type carry propagation circuit that can propagate a carry signal on a carry signal line at high speed.
この発明にかかるマンチエスタ型キヤリイ伝搬
回路は、キヤリイ信号線をプリチヤージする回路
を、上記キヤリイ信号線のプリチヤージ電圧が電
源電圧の1/2程度の中間レベルとなるよう構成し
たものである。
The Muntier star type carry propagation circuit according to the present invention has a circuit for precharging the carry signal line so that the precharge voltage of the carry signal line is at an intermediate level of about 1/2 of the power supply voltage.
この発明においては、上記キヤリイ信号線のプ
リチヤージ電圧が電源電圧の1/2程度の中間レベ
ルとなるようにしたから、キヤリイ伝搬の際に
は、キヤリイ伝搬用トランジスタのゲート印加電
圧とソース電圧，つまりキヤリイ信号線のプリチ
ヤージ電位との電位差には該トランジスタのしき
い値電圧分より十分大きな開きが確保されること
となり、このため上記キヤリイ伝搬信号がアクテ
イブになると、キヤリイ伝搬用MOSトランジス
タはそのしきい値のばらつきに関係なく、直ちに
導通することとなり、常にキヤリイ信号を高速で
伝搬することができ、演算速度の高速化を確実に
図ることができる。
In this invention, since the precharge voltage of the carry signal line is set to an intermediate level of about 1/2 of the power supply voltage, during carry propagation, the gate applied voltage and source voltage of the carry propagation transistor, that is, The potential difference between the precharge potential of the carry signal line and the precharge potential is ensured to be sufficiently larger than the threshold voltage of the transistor. Therefore, when the carry propagation signal becomes active, the carry propagation MOS transistor reaches its threshold. Regardless of the variation in values, conduction occurs immediately, and the carry signal can be propagated at high speed at all times, making it possible to reliably increase the calculation speed.
以下、この発明の一実施例を図について説明す
る。
An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例によるマンチエスタ
ー型キヤリイ伝搬回路を示し、図において、１は
電源（5V），２はGND（0V），３はプリチヤージ
用クロツク信号（Φp），４〜９は上記従来装置と
全く同一のものであり、１０はキヤリイ信号線９
のプリチヤージ用のNMOS型トランジスタであ
り、該トランジスタ１０は約1.5Vの程度の高閾
値電圧Vthを持つ。 FIG. 1 shows a Muntier star type carry propagation circuit according to an embodiment of the present invention. In the figure, 1 is a power supply (5V), 2 is a GND (0V), 3 is a precharge clock signal (Φp), and 4 to 9 is exactly the same as the conventional device described above, and 10 is a carry signal line 9.
The transistor 10 is an NMOS type transistor for precharging, and the transistor 10 has a high threshold voltage Vth of about 1.5V.
１５はキヤリイ信号線９の値の反転信号、１６
はキヤリイ信号線９の電圧レベル設定用NMOS
型トランジスタ、１７ａはキヤリイ信号線９の値
を反転するインバーターゲート、１７ｂはキヤリ
イ伝搬信号を反転するインバーターゲート、１８
は排他的論理和ゲートである。また、１４ａ，１
４ｂはそれぞれのゲートにプリチヤージ用クロツ
ク信号３、インバーターゲート１７の出力を接続
されキヤリイ信号線９のレベルを中間レベルから
ＨレベルにプルアツプするPMOS型トランジス
タであり、これらはプルアツプ回路を構成してい
る。 15 is an inverted signal of the value of the carry signal line 9; 16
is NMOS for setting the voltage level of carry signal line 9.
17a is an inverter gate that inverts the value of the carry signal line 9; 17b is an inverter gate that inverts the carry propagation signal; 18
is an exclusive OR gate. Also, 14a, 1
Reference numeral 4b denotes a PMOS transistor whose gate is connected to the precharge clock signal 3 and the output of the inverter gate 17, and which pulls up the level of the carry signal line 9 from the intermediate level to the H level, and these constitute a pull-up circuit. .
次に動作について説明する。 Next, the operation will be explained.
まず閾値電圧Vthが約1.5Vのトランジスタ１０
を用いてキヤリイ信号線９をプリチヤージする
と、該信号線は約3.5V程度の中間レベルの電位
に保たれる。この時前段のキヤリイ信号線４がＨ
レベルになり、キヤリイ信号線９のＬレベル信号
を次段へ伝搬すべくキヤリイ伝搬信号５がＨレベ
ルになると、キヤリイ伝搬用トランジスタのソー
ス６とゲート７間の電位差は、このトランジスタ
のVthより高いためキヤリイ伝搬用トランジスタ
は直ちにオン状態となる。また、該キヤリイ伝搬
信号５は、全ビツト同時に設定されるため、キヤ
リイを伝える必要のあるビツトのキヤリイ伝搬用
トランジスタは同時にオン状態になり、キヤリイ
信号線９のＬレベルの信号が高速に伝搬されるこ
とになる。 First, a transistor 10 with a threshold voltage Vth of about 1.5V
When the carry signal line 9 is precharged using the voltage, the signal line is maintained at an intermediate level potential of about 3.5V. At this time, the carry signal line 4 in the previous stage is H.
When the carry propagation signal 5 becomes H level in order to propagate the L level signal on the carry signal line 9 to the next stage, the potential difference between the source 6 and gate 7 of the carry propagation transistor is higher than the Vth of this transistor. Therefore, the carry propagation transistor immediately turns on. Furthermore, since the carry propagation signal 5 is set at the same time for all bits, the carry propagation transistors of the bits that need to transmit the carry are turned on at the same time, and the L level signal on the carry signal line 9 is propagated at high speed. That will happen.
また、各ビツトの演算は上記の方法で伝搬され
たキヤリイ信号線９の値とキヤリイ信号５の反転
信号の排他的論理和１８を取ることにより行なわ
れる。ここでキヤリイ信号線９の値がＬレベルの
場合はそのままその信号を排他的論理和ゲート１
８への出力信号として使用できるが、キヤリイ信
号線９の値が中間レベルの場合にはその中間レベ
ルの電位をプリチヤージ用クロツク３がＬレベル
の時に電源電圧まで引き上げ、これを排他的論理
和ゲートに出力する。そのため第１図に示すよう
にプルアツプ用のロジツク回路が設けられてい
る。このプルアツプ用のロジツク回路はキヤリイ
信号線９と電源１との間に直列に接続された２個
のPMOS型トランジスタからなり、これらのト
ランジスタの各ゲートには、それぞれプリチヤー
ジ用クロツク信号３、キヤリイ信号線９の値の反
転信号１５が接続されている。また、これらのト
ランジスタ１４ａ，１４ｂはPMOS型トランジ
スタであるため、プリチヤージ用トランジスタ１
０のクロツク信号１３がＬレベルで、かつキヤリ
イ信号線９が中間レベルのときにキヤリイ信号線
９の電位は電源電圧まで引き上げられる。上記の
ような回路を用いることにより、キヤリイ信号線
９の値がＬレベルの場合はそのままＬレベルの信
号を排他的論理和ゲート１８に出力し、キヤリイ
信号線９が中間レベルの場合には上記プルアツプ
用ロジツク回路によりキヤリイ信号線９をＨレベ
ルまでプルアツプし上記ゲート１８に出力する。
この時キヤリイ信号線９は5Vの電源電圧まで引
き上げられているが、次のプリチヤージ期間で該
キヤリイ信号線９はプリチヤージ用高閾値電圧
VthのNMOS型トランジスタ１０とNMOS型ト
ランジスタ１６により中間レベル（約3.5V）に
設定される。また上記NMOS型トランジスタ１
６は、トランジスタ１０とのオン抵抗の比により
キヤリイ信号線９の電位が所望の中間レベルの値
になるようにパラメータが設定されたものであ
る。そして各ビツトの演算は上記のようにして各
ビツトのキヤリイ信号線９の値が定まつた後に始
められ、従来の回路と同様にキヤリイ信号線９の
値と次段へのキヤリイ伝搬信号５の反転信号との
排他的論理和１８がとられ、これにより演算が進
められる。 Further, each bit is calculated by taking the exclusive OR 18 of the value of the carry signal line 9 propagated in the above method and the inverted signal of the carry signal 5. Here, if the value of the carry signal line 9 is at L level, that signal is directly passed to the exclusive OR gate 1.
However, when the value of the carry signal line 9 is at an intermediate level, the intermediate level potential is pulled up to the power supply voltage when the precharge clock 3 is at the L level, and this is applied to the exclusive OR gate. Output to. Therefore, a pull-up logic circuit is provided as shown in FIG. This pull-up logic circuit consists of two PMOS transistors connected in series between the carry signal line 9 and the power supply 1, and the gates of these transistors receive a precharge clock signal 3 and a carry signal, respectively. An inverted signal 15 of the value of line 9 is connected. Furthermore, since these transistors 14a and 14b are PMOS transistors, the precharge transistor 1
When the zero clock signal 13 is at L level and the carry signal line 9 is at an intermediate level, the potential of the carry signal line 9 is raised to the power supply voltage. By using the above circuit, when the value of the carry signal line 9 is at L level, the L level signal is directly output to the exclusive OR gate 18, and when the value of the carry signal line 9 is at the intermediate level, the above The pull-up logic circuit pulls up the carry signal line 9 to H level and outputs it to the gate 18.
At this time, the carry signal line 9 is pulled up to the power supply voltage of 5V, but in the next precharge period, the carry signal line 9 is pulled up to the precharge high threshold voltage.
It is set to an intermediate level (approximately 3.5V) by the Vth NMOS transistor 10 and NMOS transistor 16. In addition, the above NMOS type transistor 1
6, parameters are set so that the potential of the carry signal line 9 becomes a desired intermediate level value depending on the on-resistance ratio with the transistor 10. The calculation of each bit is started after the value of the carry signal line 9 of each bit is determined as described above, and as in the conventional circuit, the value of the carry signal line 9 and the carry propagation signal 5 to the next stage are calculated. Exclusive OR 18 with the inverted signal is taken, and the calculation proceeds accordingly.
このように本実施例では、キヤリイ信号線９の
プリチヤージ電位を3.5V程度としたので、プリ
チヤージ状態では、キヤリイ伝搬用トランジスタ
７のゲート印加電圧（5V）とソース電位，つま
りプリチヤージ電位（3.5V）との電位差には該
トランジスタ７のしきい値電圧分（0.7V）より
十分大きな開き（1.5V）が確保されることとな
り、このためキヤリイ伝搬信号５がアクテイブに
なると、上記キヤリイ伝搬用トランジスタ７は、
そのしきい値のばらつきに関係なく、直ちにオン
することとなる。この結果複数段直列に接続され
たキヤリイ伝搬用トランジスタの動作時間の合計
は直列段数とは無関係に小さな値となり、演算速
度の高速化を確実に図ることができる。 In this embodiment, the precharge potential of the carry signal line 9 is set to about 3.5V, so in the precharge state, the gate applied voltage (5V) and the source potential of the carry propagation transistor 7, that is, the precharge potential (3.5V). A sufficiently larger difference (1.5V) than the threshold voltage (0.7V) of the transistor 7 is secured in the potential difference between the transistor 7 and the carry propagation transistor 7. Therefore, when the carry propagation signal 5 becomes active, the carry propagation transistor 7 teeth,
Regardless of the variation in the threshold value, it will turn on immediately. As a result, the total operating time of the carry propagation transistors connected in series in multiple stages becomes a small value regardless of the number of stages in series, and the calculation speed can be reliably increased.
なお、上記の実施例では、高閾値電圧Vthのト
ランジスタ１０を用いてキヤリイ信号線をプリチ
ヤージすることにより、キヤリイ信号線を3.5V
程度の中間レベル設定するものを示したが、これ
は第２図に示すように0.7V程度のしきい値電圧
Vthを持つ通常のトランジスタ１１を２個直列に
接続しキヤリイ信号線を中間レベルの電位に設定
してもよく、上記実施例と同様な効果が得られ
る。 In the above embodiment, the carry signal line is set to 3.5V by precharging the carry signal line using the transistor 10 having a high threshold voltage Vth.
As shown in Figure 2, this setting has a threshold voltage of about 0.7V.
Two normal transistors 11 having Vth may be connected in series and the carry signal line may be set to an intermediate level potential, and the same effect as in the above embodiment can be obtained.
以上のように本発明にかかるマンチエスタ型キ
ヤリイ伝搬回路によれば、キヤリイ信号線のプリ
チヤージ電圧が電源電圧の1/2程度の中間レベル
となるようにしたので、キヤリイ伝搬の際には、
キヤリイ伝搬用トランジスタのゲート印加電圧と
ソース電圧、つまりキヤリイ信号線のプリチヤー
ジ電圧との電位差には該トランジスタのしきい値
電圧分より十分大きな開きが確保されることとな
り、このため上記キヤリイ伝搬信号がアクテイブ
になると、キヤリイ伝搬用MOSトランジスタは
そのしきい値のばらつきに関係なく、直ちに導通
することとなり、常にキヤリイ信号を高速で伝搬
することができ、演算速度の高速化を確実に大き
く進めることができるという効果がある。
As described above, according to the Muntier star type carry propagation circuit according to the present invention, the precharge voltage of the carry signal line is set to an intermediate level of about 1/2 of the power supply voltage, so that during carry propagation,
The potential difference between the gate applied voltage of the carry propagation transistor and the source voltage, that is, the precharge voltage of the carry signal line, is sufficiently larger than the threshold voltage of the transistor, so that the carry propagation signal is When activated, the carry propagation MOS transistor immediately becomes conductive regardless of variations in its threshold value, allowing the carry signal to be propagated at high speed at all times, thereby ensuring a significant increase in calculation speed. There is an effect that it can be done.
第１図はこの発明の一実施例によるマンチエス
ター型キヤリイ伝搬回路を示す回路図、第２図は
この発明の他の実施例を示す回路図、第３図は従
来のマンチエスター型キヤリイ伝搬回路を示す回
路図である。
図において、３はプリチヤージ用クロツク信
号、４はその前のビツトで発生したキヤリイ信
号、５は次段へのキヤリイ伝搬信号、１０はプリ
チヤージ用高Vthトランジスタ、１１はプリチヤ
ージ用トランジスタ、１４はプルアツプ用
PMOS型トランジスタ、１６はキヤリイ信号線
電圧レベル設定用NMOS型トランジスタ、１７
はインバータゲート、１８は排他的論理和ゲート
である。なお図中同一符号は同一又は相当部分を
示す。
Fig. 1 is a circuit diagram showing a Muntier star type carry propagation circuit according to one embodiment of the present invention, Fig. 2 is a circuit diagram showing another embodiment of the invention, and Fig. 3 is a circuit diagram showing a conventional Muntier star type carry propagation circuit. FIG. In the figure, 3 is a precharge clock signal, 4 is a carry signal generated in the previous bit, 5 is a carry propagation signal to the next stage, 10 is a high Vth transistor for precharge, 11 is a precharge transistor, and 14 is for pull-up.
PMOS type transistor, 16 is NMOS type transistor for setting carry signal line voltage level, 17
is an inverter gate, and 18 is an exclusive OR gate. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
信号線の電圧レベルをキヤリイとして下位ビツト
から上位ビツトへ伝搬するMOSトランジスタと、
上記キヤリイ信号線をプリチヤージする回路と、
下位ビツトでのキヤリイ発生に応じて上記キヤリ
イ信号線をデイスチヤージする回路とを備えたマ
ンチエスタ型キヤリイ伝搬回路において、 上記プリチヤージ回路を、上記キヤリイ信号線
のプリチヤージ電圧が電源電圧の1/2程度の中間
レベルとなるよう構成したことを特徴とするマン
チエスタ型キヤリイ伝搬回路。 ２ 上記プリチヤージ回路は、電源とキヤリイ信
号線との間に設けられプリチヤージ用クロツクを
制御信号とする高しきい値トランジスタまたは直
列接続の２つのトランジスタと、上記キヤリイ信
号線と接地との間に設けられ上記プリチヤージ用
クロツク信号を制御信号とするトランジスタと、
キヤリイ伝搬時における中間レベルのキヤリイ信
号線の値を電源電位レベルにプルアツプして論理
回路に与えるプルアツプ回路とから構成されてい
ることを特徴とする特許請求の範囲第１項記載の
マンチエスタ型キヤリイ伝搬回路。 ３ 上記キヤリイ信号線と接地との間のトランジ
スタは、上記キヤリイ信号線をプルダウンする第
１のMOSトランジスタであり、 上記高しきい値トランジスタは、上記キヤリイ
信号線をプリチヤージする、上記第１のMOSト
ランジスタよりしきい値を大きく設定した第２の
MOSトランジスタから構成されていることを特
徴とする特許請求の範囲第２項記載のマンチエス
タ型キヤリイ伝搬回路。[Scope of Claims] 1. A MOS transistor connected in series to a carry signal line and propagating from a lower bit to an upper bit using the voltage level of the carry signal line as a carry;
A circuit that precharges the carry signal line,
In a munchiesta type carry propagation circuit comprising a circuit for discharging the carry signal line in response to the occurrence of a carry in the lower bit, the precharge circuit is configured such that the precharge voltage of the carry signal line is approximately 1/2 of the power supply voltage. A mantier type carry propagation circuit characterized in that it is configured to have a level. 2. The precharge circuit includes a high threshold transistor or two transistors connected in series, which is provided between the power supply and the carry signal line and uses the precharge clock as a control signal, and the carry signal line and the ground. a transistor whose control signal is the precharge clock signal;
The Manchester type carry propagation according to claim 1, further comprising a pull-up circuit that pulls up the value of the carry signal line at an intermediate level during carry propagation to a power supply potential level and supplies it to a logic circuit. circuit. 3 The transistor between the carry signal line and the ground is the first MOS transistor that pulls down the carry signal line, and the high threshold transistor is the first MOS transistor that precharges the carry signal line. The second transistor has a higher threshold than the transistor.
3. The Muntier star type carry propagation circuit according to claim 2, characterized in that it is composed of MOS transistors.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60154548A JPS62111325A (en) | 1985-07-12 | 1985-07-12 | Manchester type carry transmitting circuit |
| US06/838,302 US4807176A (en) | 1985-07-12 | 1986-03-10 | Manchester type carry propagation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60154548A JPS62111325A (en) | 1985-07-12 | 1985-07-12 | Manchester type carry transmitting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62111325A JPS62111325A (en) | 1987-05-22 |
| JPH0457020B2 true JPH0457020B2 (en) | 1992-09-10 |
Family
ID=15586658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60154548A Granted JPS62111325A (en) | 1985-07-12 | 1985-07-12 | Manchester type carry transmitting circuit |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4807176A (en) |
| JP (1) | JPS62111325A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2211966A (en) * | 1987-11-02 | 1989-07-12 | Philips Nv | Digital integrated circuit |
| JP2885402B2 (en) * | 1988-06-15 | 1999-04-26 | 富士通株式会社 | Carry propagation circuit of parallel type full adder |
| US4899305A (en) * | 1988-06-15 | 1990-02-06 | National Semiconductor Corp. | Manchester carry adder circuit |
| US4885716A (en) * | 1988-08-15 | 1989-12-05 | Dallas Semiconductor Corporation | High speed carry chain |
| US5163019A (en) * | 1990-11-29 | 1992-11-10 | Brooktree Corporation | Binary carry circuitry |
| JP2530070B2 (en) * | 1991-09-11 | 1996-09-04 | 株式会社東芝 | Adder |
| JP3110221B2 (en) * | 1993-10-04 | 2000-11-20 | 株式会社東芝 | Full adder circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61168041A (en) * | 1985-01-22 | 1986-07-29 | Nec Corp | Arithmetic logic circuit |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3919536A (en) * | 1973-09-13 | 1975-11-11 | Texas Instruments Inc | Precharged digital adder and carry circuit |
| US4179746A (en) * | 1976-07-19 | 1979-12-18 | Texas Instruments Incorporated | Digital processor system with conditional carry and status function in arithmetic unit |
| US4357675A (en) * | 1980-08-04 | 1982-11-02 | Bell Telephone Laboratories, Incorporated | Ripple-carry generating circuit with carry regeneration |
| US4408136A (en) * | 1981-12-07 | 1983-10-04 | Mostek Corporation | MOS Bootstrapped buffer for voltage level conversion with fast output rise time |
| US4538239A (en) * | 1982-02-11 | 1985-08-27 | Texas Instruments Incorporated | High-speed multiplier for microcomputer used in digital signal processing system |
| US4523292A (en) * | 1982-09-30 | 1985-06-11 | Rca Corporation | Complementary FET ripple carry binary adder circuit |
| US4584660A (en) * | 1983-06-22 | 1986-04-22 | Harris Corporation | Reduction of series propagation delay and impedance |
| US4677584A (en) * | 1983-11-30 | 1987-06-30 | Texas Instruments Incorporated | Data processing system with an arithmetic logic unit having improved carry look ahead |
| JPS60134932A (en) * | 1983-12-24 | 1985-07-18 | Toshiba Corp | Carry chaining addition circuit of precharge type |
| US4661930A (en) * | 1984-08-02 | 1987-04-28 | Texas Instruments Incorporated | High speed testing of integrated circuit |
-
1985
- 1985-07-12 JP JP60154548A patent/JPS62111325A/en active Granted
-
1986
- 1986-03-10 US US06/838,302 patent/US4807176A/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61168041A (en) * | 1985-01-22 | 1986-07-29 | Nec Corp | Arithmetic logic circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62111325A (en) | 1987-05-22 |
| US4807176A (en) | 1989-02-21 |
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