JPH0447485B2 - - Google Patents
Info
- Publication number
- JPH0447485B2 JPH0447485B2 JP58046165A JP4616583A JPH0447485B2 JP H0447485 B2 JPH0447485 B2 JP H0447485B2 JP 58046165 A JP58046165 A JP 58046165A JP 4616583 A JP4616583 A JP 4616583A JP H0447485 B2 JPH0447485 B2 JP H0447485B2
- Authority
- JP
- Japan
- Prior art keywords
- current
- transistor
- circuit
- voltage
- constant current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003321 amplification Effects 0.000 claims description 14
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 230000007423 decrease Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
- H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
【発明の詳細な説明】
この発明は利得可変増幅器に係り、例えば、ラ
ジオ受信機の中間周波増幅部の自動利得調整回路
（AGC回路）に好適な増幅器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable gain amplifier, and for example, to an amplifier suitable for an automatic gain adjustment circuit (AGC circuit) of an intermediate frequency amplification section of a radio receiver.
一般に、ラジオ受信機の中間周波増幅部には
AGC回路が付加され、検波出力を制御入力とし
てその増幅利得を制御している。 Generally, the intermediate frequency amplification section of a radio receiver has
An AGC circuit is added, and its amplification gain is controlled using the detection output as a control input.
従来、この中間周波増幅部は利得調整のために
定電流段を差動回路で構成しており、通常1.5V
以下の低電圧では安定した動作を得ることができ
ない。特に、電池駆動では消耗によつて端子電圧
が低下した場合、十分なダイナミツクレンジを取
ることができず、出力信号に波形歪を生じる。そ
こで、この発明は、駆動電圧の低圧化を図つた利
得可変増幅器の提供を目的とする。 Conventionally, this intermediate frequency amplification section has a constant current stage configured with a differential circuit for gain adjustment, and the current level is usually 1.5V.
Stable operation cannot be obtained at lower voltages. In particular, when the terminal voltage decreases due to battery consumption when the battery is driven, sufficient dynamic range cannot be achieved, causing waveform distortion in the output signal. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a variable gain amplifier that can reduce the driving voltage.
即ち、この発明の利得可変増幅器は、入力端子
１８，２０を通して入力信号がベースに加えられ
る第１及び第２のトランジスタ８，１０のエミツ
タを共通に接続した差動対を備え、前記第１のト
ランジスタ及び前記第２のトランジスタの各コレ
クタと電源との間に個別に第１の抵抗１４，１６
を接続し、各コレクタ側から出力信号を取り出す
差動増幅器２と、この差動増幅器の前記第１及び
第２のトランジスタのエミツタ側から定電流を引
き込むことにより前記第１及び第２のトランジス
タに基本電流としての動作電流を流し、この動作
電流に応じた増幅利得を前記差動増幅器に設定す
る定電流回路（４、定電流源６６）と、ベースに
利得制御電圧（Vagc）が加えられ、かつエミツ
タと接地点との間に第２の抵抗５２が接続された
第３のトランジスタ５０が設置されて前記利得制
御電圧を利得制御電流に変換する電圧電流変換回
路４６と、この電圧電流変換回路で得られた前記
利得制御電流を前記定電流回路に流し込み又は前
記定電流回路から引き出して前記第１及び第２の
トランジスタのエミツタ側から前記定電流回路に
引き込まれる前記定電流を抑制することにより、
その定電流に応じた動作電流を前記第１及び第２
のトランジスタに流して前記差動増幅器の増幅利
得を可変する電流反転回路（４０，４８，６８、
第３図の電流反転回路２６）とを備えてなること
を特徴とする。 That is, the variable gain amplifier of the present invention includes a differential pair in which the emitters of the first and second transistors 8 and 10 are connected in common to the bases of which input signals are applied through input terminals 18 and 20, and the emitters of the first and second transistors 8 and 10 are connected in common. A first resistor 14, 16 is individually connected between the collector of the transistor and the second transistor and the power supply.
A differential amplifier 2 is connected to take out an output signal from each collector side, and a constant current is drawn from the emitter side of the first and second transistors of this differential amplifier to the first and second transistors. A constant current circuit (4, constant current source 66) that flows an operating current as a basic current and sets an amplification gain in the differential amplifier according to this operating current, and a gain control voltage (Vagc) is applied to the base. and a voltage-current conversion circuit 46 in which a third transistor 50 having a second resistor 52 connected between the emitter and the ground point is installed to convert the gain control voltage into a gain control current, and this voltage-current conversion circuit. By flowing the gain control current obtained in or drawing it out from the constant current circuit and suppressing the constant current drawn into the constant current circuit from the emitter side of the first and second transistors. ,
The operating current corresponding to the constant current is set to the first and second
a current inverting circuit (40, 48, 68,
The current reversing circuit 26) shown in FIG.
以下、この発明を図面に示した実施例を参照し
て詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.
第１図はこの発明の利得可変増幅器の第１実施
例を示している。この実施例の回路はラジオ受信
機の中間周波増幅段として構成したものであり、
この利得可変増幅器には動作電流の増減でその利
得が調整可能にされた差動増幅器２が設置され、
この差動増幅器２の動作電流は定電流回路４で与
えられるとともに、電流制御回路６によつてその
値が制御電圧に基づき調整されるように成つてい
る。 FIG. 1 shows a first embodiment of a variable gain amplifier according to the present invention. The circuit of this example is configured as an intermediate frequency amplification stage of a radio receiver.
This variable gain amplifier is equipped with a differential amplifier 2 whose gain can be adjusted by increasing or decreasing the operating current.
The operating current of this differential amplifier 2 is provided by a constant current circuit 4, and its value is adjusted by a current control circuit 6 based on a control voltage.
差動増幅器２は第１及び第２のトランジスタ
８，１０のエミツタを共通にして成る差動対を備
え、各トランジスタ８，１０のコレクタと電源端
子１２が形成された電源ラインとの間に第１の抵
抗１４，１６を挿入したものである。各トランジ
スタ８，１０のベースには、例えば、中間周波信
号が与えられる入力端子１８，２０が形成され、
各コレクタには増幅出力を取出す出力端子２２，
２４が形成されている。 The differential amplifier 2 includes a differential pair consisting of first and second transistors 8 and 10 whose emitters are common, and a second transistor is connected between the collectors of the transistors 8 and 10 and the power supply line on which the power supply terminal 12 is formed. In this case, two resistors 14 and 16 are inserted. For example, input terminals 18 and 20 to which an intermediate frequency signal is applied are formed at the base of each transistor 8 and 10, and
Each collector has an output terminal 22 for taking out the amplified output,
24 is formed.
トランジスタ８，１０の共通にされたエミツタ
と基準電位点との間には、定電流回路４の電流反
転回路２６を構成するトランジスタ２８が挿入さ
れ、このトランジスタ２８のベースにはダイオー
ド構成のトランジスタ３０のベース・コレクタが
共通に接続され、このトランジスタ３０には定電
流源３２から電流反転回路３４を介して基準定電
流が与えられる。即ち、定電流源３２は、電源ラ
インと基準電位点との間に、ベース・コレクタを
接続してダイオードに構成されたトランジスタ３
６を介して接続され、このトランジスタ３６のベ
ースにはトランジスタ３８のベースが接続され、
このトランジスタ３８は前記トランジスタ３０の
コレクタと電源ラインとの間に、エミツタを電源
側にして挿入されている。 A transistor 28 constituting the current inversion circuit 26 of the constant current circuit 4 is inserted between the common emitters of the transistors 8 and 10 and the reference potential point, and a diode-configured transistor 30 is connected to the base of the transistor 28. The base and collector of the transistor 30 are connected in common, and a reference constant current is applied to this transistor 30 from a constant current source 32 via a current inversion circuit 34. That is, the constant current source 32 includes a transistor 3 configured as a diode with the base and collector connected between the power supply line and the reference potential point.
6, and the base of the transistor 38 is connected to the base of the transistor 36,
This transistor 38 is inserted between the collector of the transistor 30 and the power supply line with its emitter facing the power supply side.
この実施例の場合、差動増幅器２の動作電流
は、トランジスタ３０を流れる電流を電流制御回
路６で増減することによつて調整される。即ち、
トランジスタ３０と電流反転回路４０のトランジ
スタ４２は並列に接続され、このトランジスタ４
２のベースにはトランジスタ４４のベース・コレ
クタが共通に接続されている。トランジスタ４４
はエミツタを基準電位点に接続され、コレクタに
は電圧電流変換回路４６で得られた電流が電流反
転回路４８を介して与えられる。 In this embodiment, the operating current of the differential amplifier 2 is adjusted by increasing or decreasing the current flowing through the transistor 30 with the current control circuit 6. That is,
The transistor 30 and the transistor 42 of the current inversion circuit 40 are connected in parallel.
The base and collector of the transistor 44 are commonly connected to the bases of the transistors 2 and 2. transistor 44
has an emitter connected to a reference potential point, and a current obtained by a voltage-current conversion circuit 46 is applied to the collector via a current inversion circuit 48.
電圧電流変換回路４６はトランジスタ５０のエ
ミツタと基準電位点との間に第２の抵抗５２を挿
入して構成され、トランジスタ５０のベースには
制御電流を与える制御入力端子５４が形成されて
いる。トランジスタ５０のコレクタと電源ライン
との間には電流反転回路４８のトランジスタ５５
が挿入され、トランジスタ５５はベース・コレク
タを共通にしてダイオード構成され、そのエミツ
タを電源ラインに接続し、ベース・コレクタには
トランジスタ５６のベースが共通に接続され、こ
のトランジスタ５６は電源ラインとトランジスタ
４４のベース・コレクタとの間にエミツタを電源
側にして挿入されている。 The voltage-current conversion circuit 46 is constructed by inserting a second resistor 52 between the emitter of a transistor 50 and a reference potential point, and a control input terminal 54 for applying a control current is formed at the base of the transistor 50. A transistor 55 of the current inversion circuit 48 is connected between the collector of the transistor 50 and the power supply line.
is inserted, the transistor 55 has a diode configuration with a common base and collector, and its emitter is connected to the power supply line, and the base of a transistor 56 is commonly connected to the base and collector, and this transistor 56 has a common base and collector. It is inserted between the base and collector of 44 with the emitter facing the power supply side.
以上の回路において、トランジスタ２８は電流
の変化量を大きく取るため、そのエミツタ面積は
他のトランジスタ３０，４２等のそれより大きく
設定されている。 In the above circuit, the emitter area of the transistor 28 is set to be larger than that of the other transistors 30, 42, etc., since the transistor 28 takes a large amount of change in current.
以上の構成に基づき、その動作を説明する。
今、定電流源３２の定電流をＩとすると、この電
流Ｉは電流反転回路３４のカレントミラー効果及
び電流反転回路２６のカレントミラー効果によつ
てトランジスタ２８に流れる。即ち、トランジス
タ２８，３０のエミツタ比をｎとすると、差動増
幅器２の動作電流は電流nIで与えられ、この電流
nIに基づく増幅利得が設定され、入力端子１８，
２０に与えられる入力信号はこの増幅利得に基づ
いて増幅された後、出力端子２２，２４から取出
される。 The operation will be explained based on the above configuration.
Now, assuming that the constant current of the constant current source 32 is I, this current I flows to the transistor 28 due to the current mirror effect of the current inverting circuit 34 and the current mirror effect of the current inverting circuit 26. That is, if the emitter ratio of the transistors 28 and 30 is n, the operating current of the differential amplifier 2 is given by the current nI, and this current
The amplification gain based on nI is set, and the input terminal 18,
The input signal applied to 20 is amplified based on this amplification gain and then taken out from output terminals 22 and 24.
この増幅出力は図示していない検波段に与えら
れ、その検波出力に基づき、利得制御電圧Vagc
が制御入力端子５４に与えられたとき、トランジ
スタ５０に流れる電流を例えば、0.5Iに設定する
と、この電流は電流反転回路４０，４８のカレン
トミラー効果により、トランジスタ４２で吸込ま
れる。この結果、トランジスタ３０には前記電流
Ｉとトランジスタ４２に吸込まれる電流0.5Iの合
成電流0.5Iが流れ、この電流はトランジスタ２８
にｎ倍されて流れる。即ち、差動増幅器２の動作
電流は、電流nIからｎ（１−0.5）Ｉ＝0.5nIに減少
し、この減少に応じてその増幅利得が小さくな
る。即ち、差動増幅器２の動作電流は制御入力端
子５４に与えられる制御電圧Vagcの増減に基づ
き、定電流源３２で設定された基準定電流を増減
して差動増幅器２に流すことができ、制御電圧
Vagcと増幅利得との関係は一定の比例関係を持
つことになり、制御電圧Vagcで増幅利得が制御
される。 This amplified output is given to a detection stage (not shown), and based on the detection output, the gain control voltage Vagc
When is applied to the control input terminal 54, if the current flowing through the transistor 50 is set to, for example, 0.5 I, this current is absorbed by the transistor 42 due to the current mirror effect of the current inverting circuits 40 and 48. As a result, a composite current of 0.5I of the current I and the current 0.5I absorbed by the transistor 42 flows through the transistor 30, and this current flows through the transistor 28.
The flow is multiplied by n. That is, the operating current of the differential amplifier 2 decreases from the current nI to n(1-0.5)I=0.5nI, and its amplification gain decreases in accordance with this decrease. That is, the operating current of the differential amplifier 2 can be increased or decreased based on the increase or decrease of the control voltage Vagc applied to the control input terminal 54, and the reference constant current set by the constant current source 32 can be increased or decreased to flow through the differential amplifier 2. control voltage
The relationship between Vagc and the amplification gain is a constant proportional relationship, and the amplification gain is controlled by the control voltage Vagc.
このような構成によれば、ラジオ受信機の中間
周波増幅段において、検波段からの制御電圧に基
づき安定した自動利得調整回路を構成することが
できる。また、実施例の回路構成から明らかなよ
うに差動増幅器２の利得調整系統が電流系統によ
つて構成されている結果、電源端子１２と基準電
位点との間に印加される動作電圧を低くしても従
来回路と同様の動作特性を得ることができる。従
つて、このような回路によれば、モノリシツク
ICで構成した場合、1.5V以下の低電圧で駆動す
ることができる。実験によれば、モノリシツク
ICで構成した場合、VCC＝0.8V程度まで低下して
も正常な自動利得制御が可能であることが確認さ
れた。 According to such a configuration, a stable automatic gain adjustment circuit can be configured in the intermediate frequency amplification stage of the radio receiver based on the control voltage from the detection stage. Furthermore, as is clear from the circuit configuration of the embodiment, since the gain adjustment system of the differential amplifier 2 is configured by a current system, the operating voltage applied between the power supply terminal 12 and the reference potential point can be lowered. However, the same operating characteristics as the conventional circuit can be obtained. Therefore, according to such a circuit, the monolithic
When configured with an IC, it can be driven at a low voltage of 1.5V or less. According to experiments, monolithic
When configured with an IC, it was confirmed that normal automatic gain control is possible even when V CC drops to about 0.8V.
第２図はこの発明の第２実施例を示し、前記実
施例と同一部分には同一符号を付してある。この
実施例の利得可変増幅器は、前記定電流回路４に
相当する定電流源６６をトランジスタ８，１０の
エミツタと基準電位点との間に挿入し、この定電
流源６６に電流制御回路６Ａから制御電圧を電流
に変換して流し込むように成つている。即ち、電
圧電流変換回路４６で制御電圧Vagcを変換して
得られた電流は、電流反転回路６８を介して定電
流源６６に与えられる。電流反転回路６８はトラ
ンジスタ７０，７２で構成され、第１実施例にお
いて、電流反転回路４８に出力を定電流回路４に
与えることと等価に成つている。このような構成
によつても、前記実施例と同様の効果が期待でき
る。 FIG. 2 shows a second embodiment of the present invention, in which the same parts as in the previous embodiment are given the same reference numerals. In the variable gain amplifier of this embodiment, a constant current source 66 corresponding to the constant current circuit 4 is inserted between the emitters of the transistors 8 and 10 and a reference potential point, and a current control circuit 6A is connected to the constant current source 66. It is designed to convert the control voltage into a current and inject it into the current. That is, the current obtained by converting the control voltage Vagc by the voltage-current conversion circuit 46 is provided to the constant current source 66 via the current inversion circuit 68. The current inversion circuit 68 is composed of transistors 70 and 72, and is equivalent to providing the output to the current inversion circuit 48 to the constant current circuit 4 in the first embodiment. Even with such a configuration, the same effects as in the above embodiment can be expected.
第３図はこの発明の第３実施例を示し、第１実
施例と同一部分には同一符号を付してある。この
実施例では電流制御回路６Ｂは電圧電流変換回路
を構成するトランジスタ７４をトランジスタ３０
に並列に接続して構成したものであり、トランジ
スタ７４のベースに形成した制御入力端子５４に
制御電圧Vagcを与えることにより、同様に差動
増幅器２の利得を制御することができる。このよ
うに構成すれば、電流制御回路６Ｂの構成は第１
実施例に比較して極めて簡単に構成できる。 FIG. 3 shows a third embodiment of the invention, in which the same parts as in the first embodiment are given the same reference numerals. In this embodiment, the current control circuit 6B replaces the transistor 74 constituting the voltage-current conversion circuit with the transistor 30.
By applying a control voltage Vagc to the control input terminal 54 formed at the base of the transistor 74, the gain of the differential amplifier 2 can be similarly controlled. With this configuration, the configuration of the current control circuit 6B is the first one.
The configuration can be extremely simple compared to the embodiment.
第４図はこの発明の第４実施例を示し、第１実
施例と同一部分には同一符号が付してある。この
実施例では電流反転回路４０のトランジスタ４４
のエミツタと基準電位点との間に抵抗７６を挿入
するとともに、電流反転回路４８のトランジスタ
５５のベース・コレクタとトランジスタ４４のエ
ミツタとの間に電圧電流変換回路４６を挿入した
ものであり、この電圧電流変換回路４６はトラン
ジスタ５０及び抵抗５２を直列に接続したもので
ある。この実施例では、トランジスタ５０にはベ
ースに加えられる制御電圧Vagcに応じた電流が
流れ、この電流は電流反転回路４８を通して電流
反転回路６Ｃのトランジスタ４４に流れるので、
この電流に対応した電流が電流反転回路３４側か
らトランジスタ４２に引き込まれる。 FIG. 4 shows a fourth embodiment of the present invention, in which the same parts as in the first embodiment are given the same reference numerals. In this embodiment, the transistor 44 of the current inversion circuit 40
A resistor 76 is inserted between the emitter of the transistor 55 and the reference potential point, and a voltage-current conversion circuit 46 is inserted between the base collector of the transistor 55 of the current inversion circuit 48 and the emitter of the transistor 44. The voltage-current conversion circuit 46 includes a transistor 50 and a resistor 52 connected in series. In this embodiment, a current flows through the transistor 50 according to the control voltage Vagc applied to the base, and this current flows through the current inverting circuit 48 to the transistor 44 of the current inverting circuit 6C.
A current corresponding to this current is drawn into the transistor 42 from the current inversion circuit 34 side.
ところで、この実施例ではトランジスタ４４に
は抵抗７６が接続されており、この抵抗７６には
トランジスタ４４に流れる電流に応じた電圧降下
が生じ、この電圧降下はトランジスタ４４のエミ
ツタ電位を上昇させる。そして、この抵抗７６に
は、トランジスタ５０に流れる電流が抵抗５２を
通して流し込まれているから、抵抗７６にはトラ
ンジスタ５６，４４からの電流とトランジスタ５
０からの電流とが重畳して流れ、これらの電流に
応じた電圧降下を生じることになる。即ち、この
電圧降下がトランジスタ４２の電流吸込みに大き
く影響を与えている。 Incidentally, in this embodiment, a resistor 76 is connected to the transistor 44, and a voltage drop occurs in the resistor 76 in accordance with the current flowing through the transistor 44, and this voltage drop increases the emitter potential of the transistor 44. Since the current flowing to the transistor 50 is passed through the resistor 52 into this resistor 76, the current from the transistors 56 and 44 and the current flowing through the transistor 50 are fed into the resistor 76.
Currents from 0 will flow in a superimposed manner, resulting in a voltage drop corresponding to these currents. That is, this voltage drop greatly affects the current absorption of the transistor 42.
したがつて、このような回路では制御電圧
Vagcの直線的な変化に対してトランジスタ４４
に流れる電流は抵抗７６の値に応じた変化特性、
即ち、特定の電圧範囲で緩やか又は急激な電圧変
化を付与することができ、その変化に応じた利得
制御を実現できる。 Therefore, in such a circuit, the control voltage
Transistor 44 for linear variation of Vagc
The current flowing through has a change characteristic depending on the value of the resistor 76,
That is, a gradual or rapid voltage change can be applied within a specific voltage range, and gain control can be realized in accordance with the change.
以上説明したように、この発明によれば、利得
を制御すべき差動増幅器には基本電流としての動
作電流が定電流回路によつて与えられ、その動作
電流に可変される利得制御電流を加算させて差動
増幅器に対する動作電流が低減されることによ
り、差動増幅器の利得制御を行うので、駆動電圧
の低圧化が実現でき、IC化の容易化とともに低
い駆動電圧を以て信頼性の高い利得調整を行うこ
とができる。 As explained above, according to the present invention, an operating current as a basic current is given to the differential amplifier whose gain is to be controlled by a constant current circuit, and a variable gain control current is added to the operating current. By reducing the operating current for the differential amplifier, the gain of the differential amplifier is controlled, making it possible to lower the drive voltage, making it easier to integrate into an IC, and achieving highly reliable gain adjustment with a low drive voltage. It can be performed.
第１図はこの発明の利得可変増幅器の第１実施
例を示す回路図、第２図はこの発明の利得可変増
幅器の第２実施例を示す回路図、第３図はこの発
明の利得可変増幅器の第３実施例を示す回路図、
第４図はこの発明の利得可変増幅器の第４実施例
を示す回路図である。
２……差動増幅器、４……定電流回路、８……
第１のトランジスタ、１０……第２のトランジス
タ、１４，１６……第１の抵抗、１８，２０……
入力端子、２６，４０，４８，６８……電流反転
回路、４６……電圧電流変換回路、５０……第３
のトランジスタ、５２……第２の抵抗、６６……
定電流源。
FIG. 1 is a circuit diagram showing a first embodiment of a variable gain amplifier according to the invention, FIG. 2 is a circuit diagram showing a second embodiment of a variable gain amplifier according to the invention, and FIG. 3 is a circuit diagram showing a variable gain amplifier according to the invention. A circuit diagram showing a third embodiment of
FIG. 4 is a circuit diagram showing a fourth embodiment of the variable gain amplifier of the present invention. 2... Differential amplifier, 4... Constant current circuit, 8...
First transistor, 10... Second transistor, 14, 16... First resistor, 18, 20...
Input terminal, 26, 40, 48, 68...Current inversion circuit, 46...Voltage-current conversion circuit, 50...Third
transistor, 52... second resistor, 66...
Constant current source.
Claims (1)
れる第１及び第２のトランジスタのエミツタを共
通に接続した差動対を備え、前記第１のトランジ
スタ及び前記第２のトランジスタの各コレクタと
電源との間に個別に第１の抵抗を接続し、各コレ
クタ側から出力信号を取り出す差動増幅器と、 この差動増幅器の前記第１及び第２のトランジ
スタのエミツタ側から定電流を引き込むことによ
り、前記第１及び第２のトランジスタに基本電流
としての動作電流を流し、この動作電流に応じた
増幅利得を前記差動増幅器に設定する定電流回路
と、 ベースに利得制御電圧が加えられ、かつエミツ
タと接地点との間に第２の抵抗が接続された第３
のトランジスタが設置されて前記利得制御電圧を
利得制御電流に変換する電圧電流変換回路と、 この電圧電流変換回路で得られた前記利得制御
電流を前記定電流回路に流し込み又は前記定電流
回路から引き出して前記第１及び第２のトランジ
スタのエミツタ側から前記定電流回路に引き込ま
れる前記定電流を抑制することにより、その定電
流に応じた動作電流を前記第１及び第２のトラン
ジスタに流して前記差動増幅器の増幅利得を可変
する電流反転回路と、 を備えてなることを特徴とする利得可変増幅器。[Claims] 1. A differential pair comprising a differential pair in which the emitters of a first transistor and a second transistor are connected in common, and each of the first transistor and the second transistor has a base to which an input signal is applied through an input terminal. A differential amplifier in which a first resistor is individually connected between the collector and a power supply and output signals are taken out from each collector side, and a constant current is output from the emitter sides of the first and second transistors of this differential amplifier. a constant current circuit that causes an operating current as a basic current to flow through the first and second transistors by drawing the current, and sets an amplification gain of the differential amplifier according to this operating current; and a third resistor connected between the emitter and the ground point.
a voltage-current conversion circuit in which a transistor is installed to convert the gain control voltage into a gain control current; and the gain control current obtained by the voltage-current conversion circuit is supplied to or drawn from the constant current circuit. By suppressing the constant current drawn into the constant current circuit from the emitter side of the first and second transistors, an operating current corresponding to the constant current is caused to flow through the first and second transistors. A variable gain amplifier comprising: a current inversion circuit that varies the amplification gain of a differential amplifier;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4616583A JPS59172819A (en) | 1983-03-19 | 1983-03-19 | Gain variable amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4616583A JPS59172819A (en) | 1983-03-19 | 1983-03-19 | Gain variable amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59172819A JPS59172819A (en) | 1984-09-29 |
| JPH0447485B2 true JPH0447485B2 (en) | 1992-08-04 |
Family
ID=12739397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4616583A Granted JPS59172819A (en) | 1983-03-19 | 1983-03-19 | Gain variable amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59172819A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2911901B2 (en) * | 1988-08-18 | 1999-06-28 | 日本電気アイシーマイコンシステム株式会社 | Damping circuit |
| JPH0638056U (en) * | 1992-10-08 | 1994-05-20 | ティアック株式会社 | Magnetic disk unit |
| JP2740463B2 (en) * | 1995-02-16 | 1998-04-15 | ソニー株式会社 | Disk rotation drive |
| US6317502B1 (en) | 1996-02-29 | 2001-11-13 | Sanyo Electric Co., Ltd. | Electronic volume control circuit with controlled output characteristic |
| JP4997730B2 (en) * | 2005-08-31 | 2012-08-08 | パナソニック株式会社 | Variable gain amplifier and AC power supply apparatus using the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5286041A (en) * | 1976-01-12 | 1977-07-16 | Nippon Gakki Seizo Kk | Voltage control type resistor circuit |
| JPS5623326A (en) * | 1979-07-31 | 1981-03-05 | Anritsu Corp | Punching press machine |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54163851U (en) * | 1978-05-10 | 1979-11-16 |
-
1983
- 1983-03-19 JP JP4616583A patent/JPS59172819A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5286041A (en) * | 1976-01-12 | 1977-07-16 | Nippon Gakki Seizo Kk | Voltage control type resistor circuit |
| JPS5623326A (en) * | 1979-07-31 | 1981-03-05 | Anritsu Corp | Punching press machine |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59172819A (en) | 1984-09-29 |
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