JPH0442942A - Mounting structure of semiconductor - Google Patents
Mounting structure of semiconductorInfo
- Publication number
- JPH0442942A JPH0442942A JP2149036A JP14903690A JPH0442942A JP H0442942 A JPH0442942 A JP H0442942A JP 2149036 A JP2149036 A JP 2149036A JP 14903690 A JP14903690 A JP 14903690A JP H0442942 A JPH0442942 A JP H0442942A
- Authority
- JP
- Japan
- Prior art keywords
- driver lsi
- foil
- ito film
- lsi chip
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000000034 method Methods 0.000 claims abstract description 37
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 18
- 229920002799 BoPET Polymers 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 26
- 239000000758 substrate Substances 0.000 description 16
- 239000004642 Polyimide Substances 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 229920000139 polyethylene terephthalate Polymers 0.000 description 6
- 239000005020 polyethylene terephthalate Substances 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000011888 foil Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 229920006254 polymer film Polymers 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Wire Bonding (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子ユニット等の半導体の実装構造に係り、
例えば、液晶表示素子の［゛ライパーＬ ＳＩの実装に
用いられる半導体の実装構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a mounting structure of a semiconductor such as an electronic unit,
For example, it relates to a semiconductor mounting structure used for mounting a liquid crystal display element [Liper LSI].
［従来の技術］
近時、Ｌ ＣＤ （Ｌｉｑｕｉｄ Ｃｒｙｓｔａｌ Ｄ
ｉｓｐｌａｙ ：液晶表示素子） 、Ｅ Ｌ （Ｅｌｅ
ｃｔｒｏｌｕｍｉｎｅｓｃｅｎｃｅ ：エレクトロ・
ルミネセンス）およびＦ Ｄ Ｐ （Ｐｌａｓ＋＋＋ａ
Ｄｉｓｐｌａｙ Ｐａｎｅｌ ：プラズマディスプレイ
パネル）等のデイスプレィにおいては、ドライバーＬＳ
Ｉを液晶パネル等に直付けするヂンプオンバネル（Ｃｉ
ｐ ｏｎ Ｐａｎｅｌ、以下ｃｏｐとする）方式Ｑこよ
る実装が多用されるようになってきている。なお、ＣＯ
Ｐ方式はチップオングラス方式とも呼ばれている。[Prior art] Recently, L CD (Liquid Crystal D
isplay: liquid crystal display element), E L (Ele
ctroluminescence: electro
Luminescence) and F D P (Plas+++a
For displays such as Display Panel (plasma display panel), the driver LS
Dump-on panel (Ci
P on Panel (hereinafter referred to as COP) implementation based on method Q is becoming increasingly used. In addition, CO
The P method is also called the chip-on-glass method.
一方、ＣＯＰ方式の他の方式として、ドライバー■、Ｓ
Ｉ等を基板に実装して基板を液晶パネルｔご接続する方
式、例えば、ＴＡＢ （Ｔａｐｅ Ａｕｔｏｍａｔｅｄ
Ｂｏｎｄｉｎｇ ：テープキャリア）方式が知られてお
り、第３図のように示される。On the other hand, as other methods of COP method, driver ■, S
For example, TAB (Tape Automated
A bonding (tape carrier) system is known and is shown in FIG.
第３図において、ドライバーＬＳＩチップｌの一方の電
極は、Ｌｉｑｕｉｄ Ｃｒｙｓｔａｌ Ｄｉｓｐｌａｙ
ｕｓｉｎｇＰｏｌｙｍｅｒ Ｆｉｌｍｓ （ポリマー
フィルムを基板とした液晶表示素子、以下ＰＦ−ＬＣＤ
とする）ＰＥＴ（ポリエチレンテレフタレート）基板３
上の透明導電膜、すなわちＩ Ｔ Ｏ（Ｉｎｄｉｕｍ
Ｔｉｎ ０ｘｉｄｅ）膜４にテープ５上のＣｕ箔６を介
して接続され、他方の電極は、電源入力側のフレキシブ
ル配線基板（以下、ＦＰＣとする）、すなわちポリイミ
ド基板７上のＣｕ箔８にテープ５上のＣｕ箔６を介して
接続されている。In FIG. 3, one electrode of the driver LSI chip l is a liquid crystal display.
using Polymer Films (liquid crystal display elements using polymer films as a substrate, hereinafter referred to as PF-LCD)
) PET (polyethylene terephthalate) substrate 3
The upper transparent conductive film, that is, ITO (Indium
The other electrode is connected to the Cu foil 6 on the tape 5 to the Tin Oxide) film 4 via the Cu foil 6 on the tape 5, and the other electrode is connected to the Cu foil 8 on the flexible wiring board (hereinafter referred to as FPC) on the power input side, that is, the polyimide board 7. 5 is connected via a Cu foil 6 on top.
しかしながら、これらの従来の半導体の実装構造にあっ
ては、上述のような理由により、小型化および低コスト
化を図ることができないといった問題点があった。However, these conventional semiconductor mounting structures have a problem in that they cannot be made smaller and lower in cost due to the reasons mentioned above.
すなわち、ＣＯＰ方式の場合、ＬＳＩ用の電源とＧＮＤ
ラインの抵抗値を下げる必要がある。例えば、ＬＣＤの
ＩＴＯ膜は透明度等の関係で１００〜５００人であり、
シート抵抗も高い。また、ＰＦ−ＬＣＤの基板は、ＰＥ
Ｔ基板３から構成され、ガラスを基板としたものに比較
すると、ＩＴＯ膜上に厚い膜厚の導体を形成するのが非
常に困難になるといった不具合が生じる。すなわち、ガ
ラスを基板とするものではＮｉメツキ付けを用いるが、
ＰＥＴを基板とするものにＮｉメツキ付けを用いると、
メツキ液でＩＴＯ膜が剥離する。またスパッタ法を用い
ると、ＩＴＯ膜との密着性が低く、薄膜法を用いると、
低インピーダンスの膜を形成するためのコストが高くな
る等の不具合が生じる。In other words, in the case of the COP method, the LSI power supply and GND
It is necessary to lower the line resistance. For example, the thickness of ITO film for LCD is 100 to 500 due to transparency etc.
Sheet resistance is also high. In addition, the substrate of PF-LCD is made of PE
Compared to a structure made of a T-substrate 3 and using glass as a substrate, a problem arises in that it is extremely difficult to form a thick conductor on an ITO film. In other words, Ni plating is used for those using glass as a substrate, but
When using Ni plating on a PET substrate,
The ITO film is peeled off using the plating solution. In addition, when using the sputtering method, the adhesion with the ITO film is low, and when using the thin film method,
Problems arise, such as increased cost for forming a low impedance film.
一方、ＴＡＢ方式の場合、電極ピッチの狭小化がテープ
５上のＣｕ箔６のエツチング能力に依存しており、１７
μｍのＣｕ箔では８０μｍピッチが限界となり、狭小化
が困難になる。また、テープ化が高くなり、コストが上
昇する。さらに、ＰＥＴ基板３、テープ５およびポリイ
ミド基板７の３つの部材の位置合わせが必要になり、工
程が複雑になる。On the other hand, in the case of the TAB method, the narrowing of the electrode pitch depends on the etching ability of the Cu foil 6 on the tape 5.
With a μm Cu foil, a pitch of 80 μm is the limit, making it difficult to reduce the pitch. Moreover, the cost of making a tape increases. Furthermore, it is necessary to align three members, the PET substrate 3, the tape 5, and the polyimide substrate 7, which complicates the process.
そこで本発明は、電極ピッチの狭小化と電極ラインの低
インピーダンス化を両立させて、低コスト化および小型
化を図ることができる半導体の実装構造を提供すること
を目的としている。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor mounting structure that can achieve both a narrow electrode pitch and a low impedance of an electrode line, thereby reducing cost and size.
本発明による半導体の実装構造は、上記目的を達成する
ため、半導体チ・ンブと、該半導体チップに電気的に接
続される配線を有する接続部材と、を備えた半導体の実
装構造において、前記半導体チップおよび接続部材の配
線が複数の電気的接続方式により接続されることを特徴
とするものであり、
また、前記接続部材が、第１部材および第２部材からな
り、第１部材の配線の低インピーダンス化が第２部材の
配線の低インピーダンス化より困難であり、半導体チッ
プと第１部材の配線との電気的接続方式が、半導体チッ
プを第１部材に固定するとき、同時に半導体チップと第
１部材の配線とを電気的に接続させる接続方式であり、
半導体チップと第２部材の配線との電気的接続方式が、
ワイヤボンディングによる接続方式であるようにしても
よい。In order to achieve the above object, a semiconductor mounting structure according to the present invention includes a semiconductor chip and a connecting member having wiring electrically connected to the semiconductor chip. The wiring of the chip and the connecting member are connected by a plurality of electrical connection methods, and the connecting member is composed of a first member and a second member, and the wiring of the first member is low. It is more difficult to reduce the impedance of the wiring of the second member than to reduce the impedance of the wiring of the second member. It is a connection method that electrically connects the wiring of components.
The electrical connection method between the semiconductor chip and the wiring of the second member is
A connection method using wire bonding may also be used.
以下、本発明を実施例に基づいて具体的に説明する。Hereinafter, the present invention will be specifically explained based on Examples.
第１．２図は本発明に係る半導体の実装構造の一実施例
を示す図であり、ＰＦ−ＬＣＤのドライバーＬＳＩチッ
プの実装構造に適用した例である。FIG. 1.2 is a diagram showing an embodiment of a semiconductor mounting structure according to the present invention, and is an example applied to a mounting structure of a driver LSI chip of a PF-LCD.
まず、構成を説明する。First, the configuration will be explained.
第１図において、１１はドライバーＬＳＩチップであり
、ドライバーＬＳＩチップ１１はＰＥＴフィルム１２上
のＩＴＯ膜１３およびポリイミド基板１４上のＣｕ箔１
５に電気的に接続される。すなわち、ＰＥＴフィルム１
２およびＩＴＯ膜１３、ポリイミド基板１４およびＣｕ
箔１５のそれぞれは本発明による接続部材を構成し、Ｉ
ＴＯ膜１３、Ｃｕ箔１５のそれぞれは本発明による配線
を構成する。ドライバーＬＳＩチップ１１とＩＴＯ膜１
３およびＣｕ箔１５とは後述するように複数の電気的接
続方式により接続されている。なお、ＰＥＴフィルム１
２およびＩＴＯ膜１膜着３ Ｆ−Ｌ ＣＤの一部であり
、ポリイミド基板１４およびＣｉｉ箔１５は電源部に接
続され、Ｃｕ箔１５はＡ ｕ ／ Ｎ ｉメツキされて
いる。In FIG. 1, reference numeral 11 denotes a driver LSI chip, which consists of an ITO film 13 on a PET film 12 and a Cu foil 1 on a polyimide substrate 14.
5. That is, PET film 1
2 and ITO film 13, polyimide substrate 14 and Cu
Each of the foils 15 constitutes a connecting member according to the invention and I
Each of the TO film 13 and the Cu foil 15 constitutes a wiring according to the present invention. Driver LSI chip 11 and ITO film 1
3 and the Cu foil 15 are connected by a plurality of electrical connection methods as described later. In addition, PET film 1
2 and ITO film 1 film deposition 3 F-L This is a part of the CD, the polyimide substrate 14 and the CII foil 15 are connected to the power supply part, and the Cu foil 15 is plated with Au/Ni.
ここに、ＰＥＴフィルム１２およびＩＴＯ膜１膜着３発
明による第１部材を構成し、ポリイミド基板１４および
Ｃｕ箔１５は本発明による第２部材を構成し、ＩＴＯ膜
１膜着３インピーダンス化はＣｕ箔１５の低インピーダ
ンス化より困難である。ドライバーＬＳＩチップ１１と
ＩＴＯ膜１膜着３気的接続方式は、第２図に示すように
、ドライバーＬＳＩチップ１１をＰＥＴフィルム１２に
固定するとき、同時にドライバーＬＳＩチップ１１の出
力ピンｌｌａとＩＴＯ膜１膜着３気的に接続させる接続
方式を採用している。例えば、接着剤を用いて、ＵＶ硬
化や熱圧着によりドライバーＬＳＩチップ１１とＰＥＴ
フィルム１２を接着させる方式や異方性導電膜により接
着させる方式があり、これらは前述のＣＯＰ方式であり
公知であるため、詳細な説明は省略する。Here, the PET film 12 and the ITO film 1 film 3 constitute the first member according to the invention, the polyimide substrate 14 and the Cu foil 15 constitute the second member according to the present invention, and the ITO film 1 film 3 impedance is made of Cu. This is more difficult than reducing the impedance of the foil 15. As shown in FIG. 2, the driver LSI chip 11 and the ITO film 1 film bonding 3 gaseous connection method simultaneously connects the output pin lla of the driver LSI chip 11 and the ITO film when fixing the driver LSI chip 11 to the PET film 12. A connection method is adopted in which three layers are connected in one layer. For example, the driver LSI chip 11 and PET can be bonded using adhesive, UV curing or thermocompression bonding.
There are a method of adhering the film 12 and a method of adhering with an anisotropic conductive film, and these are the above-mentioned COP method and are well known, so a detailed explanation will be omitted.
一方、ドライバーＬＳＩチップ１１とＣｕ箔１５との電
気的接続方式は、ワイヤボンディングによる接続方式を
採用している。すなわち、ポリイミド基板１４はドライ
バーＬＳＩチップ１１の電極端子のない裏面に接着され
、ドライバーＬＳＩチップ１１の入力信号ラインｌｌｂ
とＣｕ箔１５とはワイヤ１６により電気的に接続されて
いる。なお、実装手順は、ドライバーＬ Ｓ Ｉチップ
１１とＩＴＯ膜１膜着３びＰＥＴ基板１２との接続をし
た後、ドライバーＬＳＩチップ１１とＣｕ箔１５および
ポリイミド基板１４との接続をする手順に従う。On the other hand, the driver LSI chip 11 and the Cu foil 15 are electrically connected by wire bonding. That is, the polyimide substrate 14 is adhered to the back surface of the driver LSI chip 11 without electrode terminals, and the input signal line llb of the driver LSI chip 11 is
and the Cu foil 15 are electrically connected by a wire 16. Note that the mounting procedure follows the procedure of connecting the driver LSI chip 11, the ITO film 1 film deposition 3, and the PET substrate 12, and then connecting the driver LSI chip 11, the Cu foil 15, and the polyimide substrate 14.
上述のような構成によれば、同一のドライバーＬＳＩチ
ップ１１に複数の電気的接続方式が混在しているので、
各接続方式の長所を有効に利用することができ、コスト
を低減するとともに、小型化することができる。According to the above configuration, since a plurality of electrical connection methods coexist in the same driver LSI chip 11,
It is possible to effectively utilize the advantages of each connection method, reducing costs and downsizing.
具体的には、ドライバーＬＳＩチップ１１とＩＴＯ膜１
２との接続方式が狭ピッチ化に適したＣＯＰ方式であり
、ＩＴＯ膜１膜着３く、微細化に適している。また、ド
ライバーＬＳＩチップ１１の出力ビン数がチップの電極
の大部分、例えば８０〜９０％を占める。したがって、
ＬＳＸを小型化することができ、さらに低コスト化する
ことができる。Specifically, the driver LSI chip 11 and the ITO film 1
The connection method with 2 is the COP method, which is suitable for narrowing the pitch, and since only one ITO film is deposited, it is suitable for miniaturization. Further, the number of output bins of the driver LSI chip 11 occupies most of the electrodes of the chip, for example, 80 to 90%. therefore,
The LSX can be made smaller and the cost can be further reduced.
一方、ドライバーＬＳＩチップ１１とＣｕ箔１５との接
続方式がワイヤボンディング方式であり、ＣｕＦｉ１５
が低インピーダンス化し易い配線であるので、チ・ノブ
と基板の位置ずれに対して余裕をもだ七”ることかでき
、接続の低インピーダンス化を図りながら、実装工程を
簡単にすることができる。On the other hand, the connection method between the driver LSI chip 11 and the Cu foil 15 is a wire bonding method.
Since the wiring is easy to reduce impedance, it is possible to provide some margin for misalignment between the chip knob and the board, making it possible to simplify the mounting process while reducing the impedance of the connection. .
［効果］ 本発明によれば、同一のドライバーＬＳＩ子。[effect] According to the present invention, the same driver LSI child.
ブ１１に複数の電気的接続方式が混在しているので、各
接続方式の長所を有効に利用することができ、電極ピッ
チの狭小化と電極ラインの低インピーダンス化を両立さ
せることができる。したがって、コストを低減するとと
もに小型化することができる。Since a plurality of electrical connection methods coexist in the bus 11, the advantages of each connection method can be effectively utilized, and it is possible to achieve both a narrow electrode pitch and a low impedance of the electrode line. Therefore, it is possible to reduce costs and downsize.
第１．２図は本発明に係る半導体の実装構造の一実施例
を示す図であり、第１図はその正面図、第２図はそのチ
ップオンパネルによる接続を説明するための正面図、第
３図は従来の半導体の実装構造を示す正面図である。
１１・・・・・・ドライバーＬＳＩチップ（半導体チッ
プ）、
代 理 人 弁理士
有我軍
部1.2 are diagrams showing one embodiment of a semiconductor mounting structure according to the present invention, FIG. 1 is a front view thereof, FIG. 2 is a front view for explaining connection by the chip-on panel, FIG. 3 is a front view showing a conventional semiconductor mounting structure. 11...Driver LSI chip (semiconductor chip), Agent Patent Attorney Arigunbu
Claims (2)
される配線を有する接続部材と、を備えた半導体の実装
構造において、前記半導体チップおよび接続部材の配線
が複数の電気的接続方式により接続されることを特徴と
する半導体の実装構造。(1) In a semiconductor mounting structure comprising a semiconductor chip and a connection member having wiring electrically connected to the semiconductor chip, the semiconductor chip and the wiring of the connection member are connected by a plurality of electrical connection methods. A semiconductor mounting structure characterized by:
り、第１部材の配線の低インピーダンス化が第２部材の
配線の低インピーダンス化より困難であり、半導体チッ
プと第１部材の配線との電気的接続方式が、半導体チッ
プを第１部材に固定するとき、同時に半導体チップと第
１部材の配線とを電気的に接続させる接続方式であり、
半導体チップと第２部材の配線との電気的接続方式が、
ワイヤボンディングによる接続方式であることを特徴と
する請求項１記載の半導体の実装構造。(2) The connection member is composed of a first member and a second member, and it is more difficult to reduce the impedance of the wiring of the first member than that of the second member, and the wiring between the semiconductor chip and the first member is difficult to reduce. The electrical connection method is a connection method in which the semiconductor chip and the wiring of the first member are electrically connected at the same time when the semiconductor chip is fixed to the first member,
The electrical connection method between the semiconductor chip and the wiring of the second member is
2. The semiconductor mounting structure according to claim 1, wherein the connection method is wire bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149036A JPH0442942A (en) | 1990-06-06 | 1990-06-06 | Mounting structure of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149036A JPH0442942A (en) | 1990-06-06 | 1990-06-06 | Mounting structure of semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0442942A true JPH0442942A (en) | 1992-02-13 |
Family
ID=15466260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2149036A Pending JPH0442942A (en) | 1990-06-06 | 1990-06-06 | Mounting structure of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442942A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6649203B1 (en) | 1999-10-21 | 2003-11-18 | Mfi Food Canada, Ltd. | Eggshell processing methods and apparatus |
| US7549072B2 (en) | 2001-03-15 | 2009-06-16 | Robert Bosch Gmbh | Method and device for synchronizing the global time of a plurality of buses and a corresponding bus system |
-
1990
- 1990-06-06 JP JP2149036A patent/JPH0442942A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6649203B1 (en) | 1999-10-21 | 2003-11-18 | Mfi Food Canada, Ltd. | Eggshell processing methods and apparatus |
| US7549072B2 (en) | 2001-03-15 | 2009-06-16 | Robert Bosch Gmbh | Method and device for synchronizing the global time of a plurality of buses and a corresponding bus system |
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