JPH04366886A - Display device - Google Patents

Display device

Info

Publication number
JPH04366886A
JPH04366886A JP3140506A JP14050691A JPH04366886A JP H04366886 A JPH04366886 A JP H04366886A JP 3140506 A JP3140506 A JP 3140506A JP 14050691 A JP14050691 A JP 14050691A JP H04366886 A JPH04366886 A JP H04366886A
Authority
JP
Japan
Prior art keywords
delay
display device
display units
control signal
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3140506A
Other languages
Japanese (ja)
Inventor
Atsuo Kamioka
充生 上岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3140506A priority Critical patent/JPH04366886A/en
Publication of JPH04366886A publication Critical patent/JPH04366886A/en
Pending legal-status Critical Current

Links

Landscapes

  • Controls And Circuits For Display Device (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
  • Digital Computer Display Output (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE:To prevent currents and voltage pulses of respective display units as electromagnetic field radiation sources from being superposed and to decrease the radiation intensity of electromagnetic fields by delaying the control signal from a control circuit by delay circuits and applying their delay outputs to the respectively display units. CONSTITUTION:The control signal 4 is delayed by different times through the delay circuits 2a and 2b and inputted to the display units 1a-1c. When the delay time of the delay circuits 2a and 2b is Td seconds, the display units 1a-1c are controlled with the control signals 4 which have the delay times of 0 second (no delay time), Td and TdX2 seconds. Namely, the display units 1a-1c are operated with time differences by giving the control signals the delay times, so their currents and voltage pulses are prevented from being superposed to decrease the radiation intensity of the electromagnetic fields.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、表示装置に関し、特に
複数の表示器で構成される表示装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device composed of a plurality of displays.

【0002】0002

【従来の技術】従来の表示装置は、図3に示すように文
字及び図形情報を表示する複数の表示器1a,1b,1
cとこれらの表示器1a,1b,1cを制御するための
制御回路3を有し、各々の表示器1a,1b,1cを制
御信号4で制御し所望の表示情報を表示する機能を有し
ている。
2. Description of the Related Art A conventional display device includes a plurality of displays 1a, 1b, 1 for displaying character and graphic information, as shown in FIG.
c and a control circuit 3 for controlling these displays 1a, 1b, 1c, and has a function of controlling each display 1a, 1b, 1c with a control signal 4 to display desired display information. ing.

【0003】次に表示器としてACリフレッシュ形プラ
ズマディスプレイを例にとって以下に従来の表示装置に
ついて説明する。図4に示すように従来の表示装置は、
同期信号に同期し各々のプラズマディスプレイを駆動す
るための交流高電圧ドライブ波形a,b,cが同時にか
つ同期して印加されていた。
Next, a conventional display device will be described below using an AC refresh type plasma display as an example. As shown in FIG. 4, the conventional display device is
AC high voltage drive waveforms a, b, and c for driving each plasma display in synchronization with a synchronization signal were applied simultaneously and synchronously.

【0004】0004

【発明が解決しようとする課題】一般にこの種の表示装
置は、同一の制御回路3を用い制御信号4に複数の表示
器1を同期させ表示のコントロールを実行している。ま
た表示器1を複数個使用するため概して制御信号4の信
号ラインの引きまわしが長くなりかつ電源5からの電源
ラインの引きまわしも長くなりやすい。このため各々の
表示器1が発生する電磁界放射が同期し、かつ同期した
電流及び電圧パルスが電源ライン及び制御信号ラインに
生ずるため、電源磁界放射が大きくなり易いという問題
点があった。
Generally, this type of display device uses the same control circuit 3 to synchronize a plurality of display devices 1 with a control signal 4 to control the display. Furthermore, since a plurality of display devices 1 are used, the signal line for the control signal 4 generally becomes long, and the power supply line from the power source 5 tends to also become long. For this reason, the electromagnetic field radiation generated by each display 1 is synchronized, and synchronized current and voltage pulses are generated in the power supply line and the control signal line, so that there is a problem that the power supply magnetic field radiation tends to become large.

【0005】[0005]

【課題を解決するための手段】本発明の表示装置は、複
数の表示器を有し、この複数の表示器が制御回路から出
力される制御信号に同期し、かつ異なる遅延時間を有し
て動作させる回路手段を有している。
[Means for Solving the Problems] A display device of the present invention has a plurality of display devices, and the plurality of display devices are synchronized with a control signal output from a control circuit and have different delay times. It has circuit means for operating it.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明する
。図1は本発明の一実施例を示す構成図である。図にお
いて、表示器1a,1b,1cは制御信号3から出力さ
れる制御信号4により制御される。但し、制御信号4は
遅延回路2a,2bにより異なる時間遅延されて表示器
1a,1b,1cの各々に入力される。遅延回路2a,
2bにより遅延される時間をTd秒とすると、各々の表
示器1a,1b,1cは0秒(遅延時間無し),Td秒
,Td×2秒の遅延時間を有する制御信号4により制御
されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of the present invention. In the figure, indicators 1a, 1b, and 1c are controlled by a control signal 4 outputted from a control signal 3. However, the control signal 4 is input to each of the display devices 1a, 1b, 1c after being delayed by different times by the delay circuits 2a, 2b. delay circuit 2a,
If the time delayed by 2b is Td seconds, each display 1a, 1b, 1c is controlled by a control signal 4 having a delay time of 0 seconds (no delay time), Td seconds, or Td×2 seconds. .

【0007】この駆動方法をACリフレッシュ形PDP
の例をとって以下に説明する。図2に表示器を制御する
同期信号及び表示器(プラズマディスプレイ)の各々に
印加したドライブ波形a,b,cの例を示す。この図に
示すように各々の表示器は同期信号に同期してドライブ
波形a,b,cにより別々に駆動される。加えて本発明
においては、ドライブ波形bは遅延時間Tdを、ドライ
ブ波形cは遅延時間Td×2をドライブ波形aに対して
有している。
This driving method is applied to AC refresh type PDP.
This will be explained below using an example. FIG. 2 shows an example of a synchronization signal for controlling a display and drive waveforms a, b, and c applied to each of the display (plasma display). As shown in this figure, each display is driven separately by drive waveforms a, b, and c in synchronization with a synchronizing signal. In addition, in the present invention, the drive waveform b has a delay time Td, and the drive waveform c has a delay time Td×2 with respect to the drive waveform a.

【0008】[0008]

【発明の効果】以上説明したように本発明は、表示装置
を構成する複数の表示器を制御信号に遅延時間を持たせ
ることにより時差を持って動作させているので、電磁界
放射源となる各々の表示器の電流及び電圧パネルが重畳
されることを防止でき、電磁界放射強度を弱めることが
できる。
[Effects of the Invention] As explained above, in the present invention, a plurality of display devices constituting a display device are operated with a time difference by giving a delay time to a control signal, so that the display device becomes a source of electromagnetic field radiation. The current and voltage panels of each display can be prevented from being overlapped, and the electromagnetic field radiation intensity can be weakened.

【0009】加えて表示装置の消費電力のリップルが小
さくなり使用電源の小型化を実現することができるとい
う利点も有する。
In addition, there is an advantage that the ripple in the power consumption of the display device is reduced and the power source used can be made smaller.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例の構成図である。FIG. 1 is a configuration diagram of an embodiment of the present invention.

【図2】本発明の一実施例の駆動波形のタイミング図で
ある。
FIG. 2 is a timing diagram of drive waveforms according to an embodiment of the present invention.

【図3】従来例の構成図である。FIG. 3 is a configuration diagram of a conventional example.

【図4】従来の駆動波形タイミング図である。FIG. 4 is a conventional drive waveform timing diagram.

【符号の説明】[Explanation of symbols]

1a,1b,1c    表示器 2a,2b    遅延回路 3    制御回路 4    制御信号 5    電源 6    電源ライン 1a, 1b, 1c   Display device 2a, 2b Delay circuit 3 Control circuit 4 Control signal 5 Power supply 6 Power line

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  異なる種類又は同種の表示器を複数個
組み合せた表示装置において、前記表示装置を構成する
各々の表示器が、制御回路から出力される制御信号に同
期し、かつ異なる遅延時間を有して動作させる回路手段
を有することを特徴とする表示装置。
Claim 1: In a display device in which a plurality of display devices of different types or the same type are combined, each display device constituting the display device is synchronized with a control signal output from a control circuit and has a different delay time. 1. A display device comprising circuit means for operating the display device.
JP3140506A 1991-06-13 1991-06-13 Display device Pending JPH04366886A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3140506A JPH04366886A (en) 1991-06-13 1991-06-13 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3140506A JPH04366886A (en) 1991-06-13 1991-06-13 Display device

Publications (1)

Publication Number Publication Date
JPH04366886A true JPH04366886A (en) 1992-12-18

Family

ID=15270235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3140506A Pending JPH04366886A (en) 1991-06-13 1991-06-13 Display device

Country Status (1)

Country Link
JP (1) JPH04366886A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11288339A (en) * 1998-04-01 1999-10-19 Mitsubishi Electric Corp Control circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5126877B1 (en) * 1969-01-16 1976-08-09
JPS5191631A (en) * 1974-10-29 1976-08-11
JPH02278283A (en) * 1989-04-20 1990-11-14 Fujitsu Ltd Display current supply system for display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5126877B1 (en) * 1969-01-16 1976-08-09
JPS5191631A (en) * 1974-10-29 1976-08-11
JPH02278283A (en) * 1989-04-20 1990-11-14 Fujitsu Ltd Display current supply system for display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11288339A (en) * 1998-04-01 1999-10-19 Mitsubishi Electric Corp Control circuit

Similar Documents

Publication Publication Date Title
TW535138B (en) Liquid crystal displays and method for driving thereof
JPH04366886A (en) Display device
KR920007931Y1 (en) Scan line drive circuit in display device
JPS61272724A (en) Liquid crystal display device
JPH06274134A (en) One-chip microcomputer with incorporated liquid crystal display driver
JP2843231B2 (en) Lighting device for light emitting means
JP3169797B2 (en) Brightness control device
JP2586582B2 (en) Driving method of liquid crystal display device
JPH07287550A (en) Luminance adjustment circuit for display device
JP2002072973A (en) Clock signal generating circuit and display unit
KR980006859A (en) Driving circuit for liquid crystal display panel to display enlarged image without special signal processor
JPH01117585A (en) Field offset subsampling device
JPH0744138A (en) Liquid crystal display device
JP2568014B2 (en) Driving method of liquid crystal display device and device thereof
JPS62262030A (en) Liquid crystal driving controller
JPH05232900A (en) Driving method for plasma display panel
JPH06149187A (en) Method for driving liquid crystal display
JPH0216595A (en) Plasma display device
US5940147A (en) Power supply synchronization
JPH07287556A (en) Driving device for liquid crystal display device
JPH01209495A (en) Display device
JPH08221041A (en) Synchronism control circuit for display device
JPS6221190A (en) Character/graphic signal generator
JPS63103296A (en) Driving of display element
JP3333559B2 (en) Signal synchronization circuit

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19971118