JPH04356963A - Manufacture of semiconductor quantum fine wiring - Google Patents
Manufacture of semiconductor quantum fine wiringInfo
- Publication number
- JPH04356963A JPH04356963A JP15958491A JP15958491A JPH04356963A JP H04356963 A JPH04356963 A JP H04356963A JP 15958491 A JP15958491 A JP 15958491A JP 15958491 A JP15958491 A JP 15958491A JP H04356963 A JPH04356963 A JP H04356963A
- Authority
- JP
- Japan
- Prior art keywords
- growth
- layer
- growing
- wirings
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 230000012010 growth Effects 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 5
- 150000001875 compounds Chemical class 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000001947 vapour-phase growth Methods 0.000 claims 1
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 43
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 30
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 18
- 238000010586 diagram Methods 0.000 description 8
- 238000000927 vapour-phase epitaxy Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 125000002524 organometallic group Chemical group 0.000 description 2
- 101000582320 Homo sapiens Neurogenic differentiation factor 6 Proteins 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 102100030589 Neurogenic differentiation factor 6 Human genes 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000007773 growth pattern Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、超高効率の量子細線レ
ーザ、或いは量子細線トランジスタに適用される半導体
量子細線の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor quantum wire that is applied to an ultra-high efficiency quantum wire laser or a quantum wire transistor.
【０００２】0002
【従来の技術】材料としてＡｌＧａＡｓ／ＧａＡｓを例
にとって従来提案されている量子細線の構造を図５に示
す。これは、ＧａＡｓ基板上にＶ溝を形成し、有機金属
気相成長法固有の成長速度の差を利用してＶ溝底部に量
子細線を実現するものである。2. Description of the Related Art FIG. 5 shows the structure of a conventionally proposed quantum wire using AlGaAs/GaAs as an example. In this method, a V-groove is formed on a GaAs substrate, and a quantum wire is realized at the bottom of the V-groove by utilizing the difference in growth rate inherent in metal organic vapor phase epitaxy.
【０００３】この構造の製造方法を図６乃至図８に示す
。まず、ｎ＋ 型ＧａＡｓ基板上にストライプ状のエッ
チングマスクを下記数式１方向に配し、化学エッチング
によってＶ溝を形成する（図６）。次に、有機金属気相
成長法によって、ノンドープＡｌＧａＡｓ成長層２、ノ
ンドープＧａＡｓ成長層３、ｐ型ＡｌＧａＡｓ成長層４
、及びｐ型ＧａＡｓ成長層５を順次成長する。この時、
ノンドープＧａＡｓ成長層３の成長の際に、Ｖ溝側面に
は、ノンドープＧａＡｓ成長層３は、ほとんど成長せず
、Ｖ溝底部のみ成長し、ＧａＡｓ量子細線６を形成する
（図７）。A method of manufacturing this structure is shown in FIGS. 6 to 8. First, a striped etching mask is placed on an n+ type GaAs substrate in the direction of the following formula 1, and a V-groove is formed by chemical etching (FIG. 6). Next, a non-doped AlGaAs grown layer 2, a non-doped GaAs grown layer 3, a p-type AlGaAs grown layer 4 are formed by metal-organic vapor phase epitaxy.
, and p-type GaAs growth layer 5 are sequentially grown. At this time,
During the growth of the non-doped GaAs growth layer 3, the non-doped GaAs growth layer 3 hardly grows on the side surfaces of the V-groove, and grows only at the bottom of the V-groove, forming a GaAs quantum wire 6 (FIG. 7).
【０００４】0004
【数１】[Math 1]
【０００５】次に、（００１）面上のノンドープＧａＡ
ｓ成長層３からの発光を抑制するためにＨ＋ イオン注
入層７を形成し、量子細線を実現する（図８）。Next, undoped GaA on the (001) plane
In order to suppress light emission from the s-growth layer 3, an H+ ion implantation layer 7 is formed to realize a quantum wire (FIG. 8).
【０００６】しかし、上記で説明した量子細線の製造方
法には、次のような問題点がある。まず、量子細線の高
密度化が技術的に以下の理由で困難なことである。
（１）線幅を正確にコントロールすることが難しいこと
、（２）Ｖ溝を利用するため幾何学的に量子細線間の距
離が長くなること、（３）電子ビーム露光法によりエッ
チングマスクの短周期化を図っても、露光時の近接効果
のため限界があること、（４）ノンドープＧａＡｓ成長
層３の成長の際に（００１）面上にも、成長がおこるた
め、発光を抑制するためイオン注入等の電流狭窄手段が
必要になること、等である。また、化学エッチングによ
るＶ溝底部に量子細線を製造するため、１００ｎｍ以下
の線幅の均一性が悪いことである。However, the method for manufacturing quantum wires described above has the following problems. First, it is technically difficult to increase the density of quantum wires for the following reasons. (1) It is difficult to accurately control the line width, (2) the distance between the quantum wires becomes longer due to the use of V-grooves, and (3) the etching mask can be shortened by the electron beam exposure method. Even if periodization is attempted, there is a limit due to the proximity effect during exposure, and (4) growth also occurs on the (001) plane when the non-doped GaAs growth layer 3 is grown, so in order to suppress light emission. For example, a current confinement means such as ion implantation is required. Furthermore, because the quantum wire is manufactured at the bottom of the V-groove by chemical etching, the uniformity of the line width of 100 nm or less is poor.
【０００７】[0007]
【発明が解決しようとする課題】本発明の目的は、超高
効率の量子細線レーザ、或いは量子細線トランジスタに
適用される半導体量子細線の製造方法を提供することで
ある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor quantum wire which is applied to an ultra-high efficiency quantum wire laser or a quantum wire transistor.
【０００８】更に具体的に、本発明の目的の１つは、量
子細線の高密度化が容易な半導体量子細線の製造方法を
提供することである。[0008] More specifically, one of the objects of the present invention is to provide a method for manufacturing semiconductor quantum wires that facilitates increasing the density of quantum wires.
【０００９】更に具体的に、本発明の目的の１つは、量
子細線の高密度化と線幅の正確な制御による線幅の均一
化が容易な半導体量子細線の製造方法を提供することで
ある。More specifically, one of the objects of the present invention is to provide a method for manufacturing semiconductor quantum wires in which it is easy to increase the density of quantum wires and make the line width uniform by accurately controlling the line width. be.
【００１０】更に具体的に、本発明の目的の１つは、基
板温度等の形成条件により基板結晶面に対して選択的に
膜成長することを利用し、交互に積層した二種類の層の
片方の層に細線を形成し、細線幅、細線の密度を高精度
に制御可能な成長膜厚で決定できる半導体量子細線の製
造方法を提供することである。More specifically, one of the objects of the present invention is to utilize the fact that the film grows selectively to the crystal plane of the substrate depending on the formation conditions such as the substrate temperature, and to form two types of layers stacked alternately. It is an object of the present invention to provide a method for manufacturing a semiconductor quantum wire in which a thin wire is formed in one layer and the width of the thin wire and the density of the thin wire can be determined by the growth film thickness that can be controlled with high precision.
【００１１】[0011]
【課題を解決するための手段】本発明の量子細線の製造
方法は、高密度化と線幅の均一化をねらいとして提案さ
れたものであり、予め選択マスクを配置した基板上に、
有機金属気相成長法を使って矩形状にノンドープＡｌＧ
ａＡｓ成長層２、ノンドープＧａＡｓ成長層３を交互に
多層成長させた後、選択エッチングを用いてノンドープ
ＡｌＧａＡｓ成長層２のみエッチングし、Ｕ溝を多数形
成する。[Means for Solving the Problems] The method for manufacturing quantum wires of the present invention was proposed with the aim of increasing the density and making the line width uniform.
Non-doped AlG in a rectangular shape using organometallic vapor phase epitaxy
After the aAs growth layer 2 and the non-doped GaAs growth layer 3 are grown alternately, only the non-doped AlGaAs growth layer 2 is etched using selective etching to form a large number of U-grooves.
【００１２】次に、再度、有機金属気相成長法により、
Ｕ溝部に量子細線を作ることを主要な特徴とした製造方
法である。[0012] Next, again by the organometallic vapor phase epitaxy method,
This is a manufacturing method whose main feature is to create quantum wires in the U-groove.
【００１３】本発明の構成は下記に示す通りである。即
ち、本発明は、（１１１）Ｂ化合物半導体基板（９）面
上に絶縁膜（１０）を堆積し、｛１１２｝方向のストラ
イプ状の開口部を形成する第１の工程と、該半導体基板
（９）上に有機金属気相成長法を用いて、側壁に（１１
０）面をもつ少なくとも２種類以上の半導体（２，３）
を（１１１）Ｂ面上に多層成長させる第２の工程（図２
）と、多層構造側面を選択的にエッチングする第３の工
程（図３）と、（１１１）Ｂ面上に成長のおこらない成
長条件を用いて少なくとも２種類以上の半導体（２，４
，５，６）を（１１０）側面方向に選択的に順次成長さ
せる第４の工程（図４）とからなることを特徴とする半
導体量子細線の製造方法としての構成を有するものであ
る。The structure of the present invention is as shown below. That is, the present invention includes a first step of depositing an insulating film (10) on the (111)B compound semiconductor substrate (9) surface and forming striped openings in the {112} direction; (9) on the side wall using metal organic vapor phase epitaxy (11
0) at least two types of semiconductors (2, 3) with planes
The second step is to grow multilayers on the (111) B plane (Fig. 2
) and a third step (FIG. 3) of selectively etching the side surfaces of the multilayer structure, and a third step (FIG. 3) of selectively etching the side surfaces of the multilayer structure, and etching at least two or more types of semiconductors (2,4
, 5, 6) selectively and sequentially grown in the (110) side direction (FIG. 4).
【００１４】[0014]
【作用】本発明の製造方法は、選択成長による矩形の成
長膜厚がＵ溝の幅として利用できるから、線幅の均一性
が向上し、かつ高密度の量子細線の製造が可能となる。
本発明の製造方法では、基板温度等の形成条件により基
板結晶面に対して選択的に膜成長することを利用し、交
互に積層した２種類の層の片方の層に細線を形成するた
め、細線幅、細線の密度を高精度に制御可能な成長膜厚
によって決定することができる。[Function] In the manufacturing method of the present invention, since the thickness of the rectangular growth film by selective growth can be used as the width of the U-groove, the uniformity of the line width is improved and it is possible to manufacture quantum wires with high density. In the manufacturing method of the present invention, thin lines are formed in one layer of two types of layers stacked alternately by utilizing selective film growth on the substrate crystal plane depending on formation conditions such as substrate temperature. The width of the thin line and the density of the thin line can be determined by the growth film thickness, which can be controlled with high precision.
【００１５】本発明による半導体量子細線の製造方法は
、成長温度及びＶ族原料とＩＩＩ 族原料の濃度比（Ｖ
／ＩＩＩ 比）によって選択成長の成長様式が変わるこ
とを巧みに利用したものである。連続した１回の成長工
程で一次元電子の蓄積領域を形成するものであるから、
電子の蓄積領域が加工ダメージや汚染から完全に逃れる
ことができるという利点がある。また、横方向の界面の
急峻性も単原子オーダで制御可能であることから、急峻
な界面を持った量子細線構造が実現できる。従って極微
細構造が極めて精度良く実現されている。The method for manufacturing a semiconductor quantum wire according to the present invention is based on the growth temperature and the concentration ratio of the group V raw material and the group III raw material (V
This skillfully takes advantage of the fact that the growth pattern of selective growth changes depending on the ratio (/III ratio). Since a one-dimensional electron accumulation region is formed in one continuous growth process,
This has the advantage that the electron storage region can be completely protected from processing damage and contamination. Furthermore, since the steepness of the lateral interface can be controlled on the order of a single atom, a quantum wire structure with a steep interface can be realized. Therefore, an extremely fine structure is realized with extremely high precision.
【００１６】[0016]
【実施例】以下、材料としてＡｌＧａＡｓ／ＧａＡｓを
例にとって本発明の実施例について詳細に説明する。Embodiments Hereinafter, embodiments of the present invention will be described in detail using AlGaAs/GaAs as an example of the material.
【００１７】図１は本発明の方法によって作られた量子
細線の基本構造であり、ＧａＡｓ量子細線は６の部分で
ある。図２乃至図４は、図１の構造を作製する手順を示
しており、以下順次説明する。FIG. 1 shows the basic structure of a quantum wire made by the method of the present invention, and the GaAs quantum wire is part 6. 2 to 4 show a procedure for manufacturing the structure shown in FIG. 1, which will be explained in sequence below.
【００１８】まず、（１１１）Ｂ面ｎ＋ 型ＧａＡｓ基
板９上にＳｉＯ２ １０をスパッタ法或いは、ＣＶＤ法
で堆積させ、下記数式２方向に沿ったストライプ状の開
口部を作り、この基板上に有機金属気相成長法を使い、
Ｖ族原料とＩＩＩ 族原料の濃度比（Ｖ／ＩＩＩ 比）
４０−１５０、８００℃の成長温度でノンドープＧａＡ
ｓ成長層３、ノンドープＡｌＧａＡｓ成長層２を交互に
５０ｎｍずつ矩形に成長させる（図２）。この時、側面
には、（１１０）ファセット面があらわれる。First, SiO2 10 is deposited on the (111) B-plane n+ type GaAs substrate 9 by sputtering or CVD to form striped openings along the direction of the following formula 2, and an organic layer is deposited on this substrate. Using metal vapor phase epitaxy,
Concentration ratio of group V raw material and group III raw material (V/III ratio)
Non-doped GaA at growth temperature of 40-150, 800℃
The S growth layer 3 and the non-doped AlGaAs growth layer 2 are grown alternately in a rectangular shape of 50 nm each (FIG. 2). At this time, a (110) facet surface appears on the side surface.
【００１９】[0019]
【数２】[Math 2]
【００２０】次に、沸酸系あるいは塩酸／過酸化水素系
の選択エッチング液を用いて、（１１０）側面のノンド
ープＡｌＧａＡｓ成長層２のみを選択的にエッチングし
、Ｕ溝を矩形側面に多数形成する（図３）。Next, using a hydrochloric acid-based or hydrochloric acid/hydrogen peroxide-based selective etching solution, only the non-doped AlGaAs growth layer 2 on the (110) side surface is selectively etched to form a large number of U grooves on the rectangular side surface. (Figure 3).
【００２１】次に、成長温度を６５０℃に下げ、（１１
０）側面方向にのみノンドープＡｌＧａＡｓ成長層２を
３０ｎｍ、ＧａＡｓ層（ＧａＡｓ量子細線）６を８ｎｍ
、ｐ型ＡｌＧａＡｓ成長層４を５０ｎｍ、ｐ型ＧａＡｓ
成長層５を１０ｎｍ順次成長する（図４）。６５０℃以
下の成長温度では（１１１）Ｂ面上には、全く成長がお
こらず（１１０）側面だけが選択的に成長する。また、
側面ではＵ溝の底部の成長速度が、（１１０）面の成長
速度よりも早いためＵ溝部のみにＧａＡｓ量子細線６を
選択的に成長することができる。量子細線の幅は最初の
成長工程である（１１１）Ｂ面上へのノンドープＡｌＧ
ａＡｓ成長層２の厚さとほぼ一致するため、図１のノン
ドープＡｌＧａＡｓ成長層２の成長時間だけで容易に制
御できる。Next, the growth temperature was lowered to 650°C and (11
0) Non-doped AlGaAs growth layer 2 is 30 nm thick and GaAs layer (GaAs quantum wire) 6 is 8 nm thick only in the side direction.
, p-type AlGaAs growth layer 4 of 50 nm, p-type GaAs
Growth layers 5 are sequentially grown to a thickness of 10 nm (FIG. 4). At a growth temperature of 650° C. or lower, no growth occurs on the (111) B plane, and only the (110) side grows selectively. Also,
On the side surfaces, the growth rate at the bottom of the U-groove is faster than the growth rate at the (110) plane, so the GaAs quantum wire 6 can be selectively grown only in the U-groove. The width of the quantum wire is determined by the first growth step of undoped AlG on the (111)B plane.
Since the thickness almost matches the thickness of the aAs growth layer 2, it can be easily controlled only by the growth time of the non-doped AlGaAs growth layer 2 shown in FIG.
【００２２】以上説明したように、本発明による半導体
量子細線の製造方法では、成長膜厚で量子細線の幅を決
定できるため、線幅の制御性と均一性が良好なこと、及
び高密度化を図れることが主要な特徴である。As explained above, in the method for manufacturing a semiconductor quantum wire according to the present invention, since the width of the quantum wire can be determined by the thickness of the grown film, the controllability and uniformity of the line width are good, and the high density can be achieved. The main feature is that it is possible to achieve
【００２３】本発明の実施例では、ＡｌＧａＡｓ／Ｇａ
Ａｓ系材料で説明したが、ＧａＩｎＰ／ＧａＡｓ、Ｇａ
ＩｎＡｓ／ＩｎＰ等のＩＩＩ −Ｖ族半導体及びその混
晶系、ＺｎＳｅ／ＧａＡｓ等のＩＩ−ＶＩ族半導体とそ
の混晶系材料でも実現できる。In an embodiment of the present invention, AlGaAs/Ga
Although the explanation was made using As-based materials, GaInP/GaAs, Ga
It can also be realized with III-V group semiconductors such as InAs/InP and their mixed crystal systems, and II-VI group semiconductors and their mixed crystal materials such as ZnSe/GaAs.
【００２４】また、図２の矩形の成長は、ＧａＡｓ／Ａ
ｌＧａＡｓ多層構造が成長できることと側面の非常にき
れいな（１１０）ファセット面を半導体レーザのミラー
面として利用できることからショートキャビティレーザ
を作製することも可能となる。Furthermore, the rectangular growth shown in FIG.
Since a lGaAs multilayer structure can be grown and a very clean (110) facet on the side surface can be used as a mirror surface of a semiconductor laser, it is also possible to fabricate a short cavity laser.
【００２５】[0025]
【発明の効果】本発明による半導体量子細線の製造方法
は、結晶成長だけで量子細線の幅と密度が決定できるた
めに、量子細線の均一性、高密度化が図れ、低しきい値
、高出力の量子細線レーザあるいは量子細線トランジス
タが得られる。Effects of the Invention The method for manufacturing semiconductor quantum wires according to the present invention allows the width and density of the quantum wires to be determined only by crystal growth, so that uniformity and high density of the quantum wires can be achieved, and low threshold and high An output quantum wire laser or quantum wire transistor is obtained.
【図１】本発明の方法で作成される量子細線構造図であ
る。FIG. 1 is a diagram of a quantum wire structure created by the method of the present invention.
【図２】（１１１）ＢＧａＡｓ基板上に下記数式３方向
に沿ったストライプ状の開口部を作り、この基板上にＧ
ａＡｓ層（３）、ＡｌＧａＡｓ層（２）を交互に５０ｎ
ｍずつ矩形に成長させた工程図である。[Figure 2] Stripe-shaped openings are made on a (111) BGaAs substrate along the three directions of the following formula, and G
The aAs layer (3) and the AlGaAs layer (2) are alternately 50n
It is a process diagram of growing a rectangle by m.
【数３】[Math 3]
【図３】（１１０）側面のＡｌＧａＡｓ層（２）のみを
選択的にエッチングし、Ｕ溝を矩形側面に多数形成する
工程図である。FIG. 3 is a process diagram in which only the AlGaAs layer (2) on the (110) side surface is selectively etched to form a large number of U grooves on the rectangular side surface.
【図４】（１１０）側面方向にのみＡｌＧａＡｓ層（２
）を３０ｎｍ、ＧａＡｓ層（６）を８ｎｍ、ｐ型ＡｌＧ
ａＡｓ層（４）を５０ｎｍ、ＧａＡｓ層（５）を１０ｎ
ｍ順次成長する工程図である。[Fig. 4] (110) AlGaAs layer (2) only in the side direction
) is 30 nm, GaAs layer (6) is 8 nm, p-type AlG
The aAs layer (4) is 50 nm thick, and the GaAs layer (5) is 10 nm thick.
It is a process diagram of growing m sequentially.
【図５】従来提案されている一次元量子細線構造図であ
る。FIG. 5 is a diagram of a conventionally proposed one-dimensional quantum wire structure.
【図６】ｎ＋ 型ＧａＡｓ基板上に化学エッチングによ
ってＶ溝を形成する工程図である。FIG. 6 is a process diagram of forming a V-groove by chemical etching on an n+ type GaAs substrate.
【図７】ＡｌＧａＡｓ層（２）、ＧａＡｓ層（３）、ｐ
型ＡｌＧａＡｓ層（４）及びｐ型ＧａＡｓ層（５）を順
次成長する工程図である。FIG. 7: AlGaAs layer (2), GaAs layer (3), p
It is a process diagram of sequentially growing a type AlGaAs layer (4) and a p-type GaAs layer (5).
【図８】（００１）面上のＧａＡｓ層（３）からの発光
を抑制するためにＨ＋ イオン注入層を形成し、量子細
線を実現する工程図である。FIG. 8 is a process diagram for realizing a quantum wire by forming an H+ ion implantation layer to suppress light emission from the GaAs layer (3) on the (001) plane.
１ （００１）ｎ＋ 型ＧａＡｓ基板２ ノンドー
プＡｌＧａＡｓ成長層
３ ノンドープＧａＡｓ成長層
４ ｐ型ＡｌＧａＡｓ成長層
５ ｐ型ＧａＡｓ成長層
６ ＧａＡｓ量子細線
７ Ｈ＋ イオン注入層
８ エッチングマスク
９ （１１１）Ｂ面ｎ＋ 型ＧａＡｓ基板１０ Ｓ
ｉＯ２ （マスク）1 (001) n+ type GaAs substrate 2 Non-doped AlGaAs growth layer 3 Non-doped GaAs growth layer 4 P-type AlGaAs growth layer 5 P-type GaAs growth layer 6 GaAs quantum wire 7 H+ ion implantation layer 8 Etching mask 9 (111)B surface n+ type GaAs substrate 10S
iO2 (mask)
Claims (1)
絶縁膜を堆積し、｛１１２｝方向のストライプ状の開口
部を形成する第１の工程と、該半導体基板上に有機金属
気相成長法を用いて、側壁に（１１０）面をもつ少なく
とも２種類以上の半導体を（１１１）Ｂ面上に多層成長
させる第２の工程と、多層構造側面を選択的にエッチン
グする第３の工程と、（１１１）Ｂ面上に成長のおこら
ない成長条件を用いて少なくとも２種類以上の半導体を
（１１０）側面方向に選択的に順次成長させる第４の工
程とからなることを特徴とする半導体量子細線の製造方
法。1. A first step of depositing an insulating film on the surface of a (111)B compound semiconductor substrate and forming striped openings in the {112} direction, and metal organic vapor phase growth on the semiconductor substrate. a second step of growing multilayers of at least two types of semiconductors having (110) planes on the sidewalls on the (111)B plane using a method; and a third step of selectively etching the side surfaces of the multilayer structure. , a fourth step of selectively and sequentially growing at least two types of semiconductors in the (110) side direction using growth conditions that do not cause growth on the (111) B plane. Method of manufacturing thin wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15958491A JPH04356963A (en) | 1991-06-03 | 1991-06-03 | Manufacture of semiconductor quantum fine wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15958491A JPH04356963A (en) | 1991-06-03 | 1991-06-03 | Manufacture of semiconductor quantum fine wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04356963A true JPH04356963A (en) | 1992-12-10 |
Family
ID=15696909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15958491A Pending JPH04356963A (en) | 1991-06-03 | 1991-06-03 | Manufacture of semiconductor quantum fine wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04356963A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0537091A (en) * | 1991-08-01 | 1993-02-12 | Tokyo Inst Of Technol | Multi-dimensional quantum well device and its manufacture |
| JP2007531998A (en) * | 2004-04-02 | 2007-11-08 | ヒューレット−パッカード デベロップメント カンパニー エル．ピー． | Production and use of superlattices |
| US7829352B2 (en) | 2003-10-07 | 2010-11-09 | Hewlett-Packard Development Company, L.P. | Fabrication of nano-object array |
-
1991
- 1991-06-03 JP JP15958491A patent/JPH04356963A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0537091A (en) * | 1991-08-01 | 1993-02-12 | Tokyo Inst Of Technol | Multi-dimensional quantum well device and its manufacture |
| US7829352B2 (en) | 2003-10-07 | 2010-11-09 | Hewlett-Packard Development Company, L.P. | Fabrication of nano-object array |
| JP2007531998A (en) * | 2004-04-02 | 2007-11-08 | ヒューレット−パッカード デベロップメント カンパニー エル．ピー． | Production and use of superlattices |
| JP4796569B2 (en) * | 2004-04-02 | 2011-10-19 | サムスン エレクトロニクス カンパニー リミテッド | Production and use of superlattices |
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