JPH04350962A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH04350962A JPH04350962A JP12390291A JP12390291A JPH04350962A JP H04350962 A JPH04350962 A JP H04350962A JP 12390291 A JP12390291 A JP 12390291A JP 12390291 A JP12390291 A JP 12390291A JP H04350962 A JPH04350962 A JP H04350962A
- Authority
- JP
- Japan
- Prior art keywords
- region
- island
- conductivity type
- lower electrode
- capacitive element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000010409 thin film Substances 0.000 claims description 21
- 238000000605 extraction Methods 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 3
- 235000001537 Ribes X gardonianum Nutrition 0.000 abstract 1
- 235000001535 Ribes X utile Nutrition 0.000 abstract 1
- 235000016919 Ribes petraeum Nutrition 0.000 abstract 1
- 244000281247 Ribes rubrum Species 0.000 abstract 1
- 235000002355 Ribes spicatum Nutrition 0.000 abstract 1
- 239000010408 film Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Landscapes
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は複数種類の容量素子を組
み込んだ半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit incorporating a plurality of types of capacitive elements.
【０００２】0002
【従来の技術】バイポーラ型集積回路に組み込まれる容
量素子として、ＰＮ接合を利用するもの、酸化膜（Ｓｉ
Ｏ２）や窒化膜（ＳｉＮ）を利用するものが知られてい
る。前者は構造が簡単である特徴を有し、後者は単位面
積当りの容量値を大きくできる利点を有する。そのため
微細化を押し進めた半導体装置では後者が多用されてい
る。[Prior Art] Capacitive elements incorporated in bipolar integrated circuits include capacitors that utilize PN junctions and oxide films (Si).
There are known devices that utilize O2) and nitride film (SiN). The former has a feature of simple structure, and the latter has the advantage of being able to increase the capacitance value per unit area. For this reason, the latter is often used in semiconductor devices that have been miniaturized.
【０００３】後者の代表的な構造を図３に示す。即ち、
半導体基板（１）上のエピタキシャル層を分離した島領
域（２）内に、Ｎ＋型拡散領域を形成して下部電極（３
）とし、ＳｉＯ２又はＳｉＮから成る誘電体薄膜（４）
上にＡｌ配線で上部電極（５）を形成したものである（
例えば、特公昭６１−２４８２５号公報）。尚、（６）
はＮ＋埋め込み層、（７）はＰ＋分離領域、（８）はＡ
ｌ電極、（９）は酸化膜である。また、前記下部電極（
３）としては、直列抵抗分を下げるため、および工程の
共用化の点でＮＰＮトランジスタのエミッタ拡散が使わ
れている。A typical structure of the latter is shown in FIG. That is,
An N+ type diffusion region is formed in an island region (2) separating an epitaxial layer on a semiconductor substrate (1), and a lower electrode (3) is formed on the semiconductor substrate (1).
) and a dielectric thin film (4) made of SiO2 or SiN.
An upper electrode (5) is formed on top using Al wiring (
For example, Japanese Patent Publication No. 61-24825). Furthermore, (6)
is N+ buried layer, (7) is P+ isolation region, (8) is A
The l electrode (9) is an oxide film. In addition, the lower electrode (
As for 3), emitter diffusion of an NPN transistor is used in order to reduce the series resistance and to share the process.
【０００４】近年、誘電体薄膜（４）を形成するための
熱処理によるエミッタ領域の再拡散とばらつきを避ける
ため、誘電体薄膜（４）を形成した後にエミッタ拡散を
行う試みが成されている。また、バイポーラ素子とＭＯ
Ｓ素子とを混在したＢｉ−ＣＭＯＳ集積回路では、ＭＯ
Ｓ素子と上記容量素子の後者の構造とが近似しているた
め、誘電体薄膜（４）にゲート酸化膜を、上部電極（５
）にゲート電極を利用し、且つＮｃｈＭＯＳのソース・
ドレイン領域をエミッタ拡散で形成する試みが成されて
いる。すると、両者共に誘電体薄膜（４）を形成してか
らエミッタ拡散を行うため、下部電極（３）としてはエ
ミッタ以前の工程、例えばＮＰＮトランジスタのコレク
タ低抵抗領域等を利用することになる。In recent years, attempts have been made to perform emitter diffusion after forming the dielectric thin film (4) in order to avoid rediffusion and variations in the emitter region due to heat treatment for forming the dielectric thin film (4). In addition, bipolar elements and MO
In Bi-CMOS integrated circuits containing S elements, MO
Since the structure of the S element and the latter of the above capacitive elements are similar, a gate oxide film is formed on the dielectric thin film (4), and a gate oxide film is formed on the dielectric thin film (4).
), and the NchMOS source/
Attempts have been made to form the drain region by emitter diffusion. Then, since the emitter diffusion is performed after forming the dielectric thin film (4) in both cases, a process before the emitter, for example, a low resistance region of the collector of an NPN transistor, is used as the lower electrode (3).
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記コ
レクタ低抵抗領域は、いずれも製造工程の前半から中盤
にかけて形成するものであり、エミッタ拡散程表面濃度
を上げることは困難である。そのため容量素子の直列抵
抗が増大し、Ｑの周波数特性が悪化する欠点がある。However, the collector low resistance region described above is formed in the first half to the middle of the manufacturing process, and it is difficult to increase the surface concentration to the extent of emitter diffusion. Therefore, there is a drawback that the series resistance of the capacitive element increases and the frequency characteristics of Q deteriorate.
【０００６】これを改善すべく、容量素子の底部にＮ＋
型埋め込み層（６）を配置するが、今度はＮ＋型埋め込
み層（６）と基板（１）とのＰＮ接合が比較的高不純物
濃度の領域の接合になるので、下部電極（３）と基板（
１）との間で寄生容量を持ち、特に高周波回路に用いる
と基板（１）へのもれ電流が大きくなって寄生効果等を
発生する欠点があった。In order to improve this, N+ is placed at the bottom of the capacitive element.
The type buried layer (6) is placed, but this time the PN junction between the N+ type buried layer (6) and the substrate (1) is a junction in a region with a relatively high impurity concentration, so the lower electrode (3) and the substrate (
1), and especially when used in a high frequency circuit, leakage current to the substrate (1) becomes large, resulting in parasitic effects.
【０００７】[0007]
【課題を解決するための手段】本発明は上記課題に鑑み
成されたもので、同一基板（１３）上にＮＰＮトランジ
スタ（１０）、第１の容量素子（１１）、および第２の
容量素子（１２）とを形成し、第１の容量素子（１１）
は、Ｎ＋型埋め込み層（１８）を形成した島領域（１６
）にＮ＋型下部電極領域（２３）を形成し、下部電極領
域（２３）の上に誘電体薄膜（２４）と上部電極（２５
）とを一様に形成し、第２の容量素子（１２）は、Ｎ＋
型埋め込み層（１８）を形成しない島領域（１７）にＮ
＋型下部電極領域（２７）を形成し、下部電極領域（２
７）の上に誘電体薄膜（２８）と上部電極（２９）を形
成し、且つ取出し電極（３０）を櫛歯状に配置したこと
を特徴とする。[Means for Solving the Problems] The present invention has been made in view of the above problems, and provides an NPN transistor (10), a first capacitive element (11), and a second capacitive element on the same substrate (13). (12) and the first capacitive element (11).
is an island region (16) in which an N+ type buried layer (18) is formed.
), and a dielectric thin film (24) and an upper electrode (25) are formed on the lower electrode region (23).
) are uniformly formed, and the second capacitive element (12) is N+
N is applied to the island region (17) where the mold buried layer (18) is not formed.
A +-type lower electrode region (27) is formed, and a lower electrode region (27) is formed.
A dielectric thin film (28) and an upper electrode (29) are formed on 7), and the extraction electrode (30) is arranged in a comb-like shape.
【０００８】[0008]
【作用】主として低周波回路に用いる第１の容量素子（
１１）は、Ｎ＋型埋め込み層（１８）を設けることによ
り下部電極領域（２３）の取出し抵抗を減じることがで
き、且つ占有面積が小さい。主として高周波回路に用い
る第２の容量素子（１２）は、Ｎ＋型埋め込み層（１８
）を除去したことにより島領域（１７）がエピタキシャ
ル層と基板（１３）との低濃度接合となり、寄生容量を
低減できる。一方、埋め込み層（１８）を除去したこと
による下部電極領域（２７）の取出し抵抗の増大は、取
出し電極（３０）を櫛歯状とすることにより相殺できる
。[Function] The first capacitive element (mainly used in low frequency circuits)
11) can reduce the extraction resistance of the lower electrode region (23) by providing the N+ type buried layer (18), and also has a small occupied area. The second capacitive element (12) mainly used in high frequency circuits has an N+ type buried layer (18
), the island region (17) becomes a low concentration junction between the epitaxial layer and the substrate (13), and parasitic capacitance can be reduced. On the other hand, the increase in the extraction resistance of the lower electrode region (27) due to the removal of the buried layer (18) can be offset by making the extraction electrode (30) comb-shaped.
【０００９】[0009]
【実施例】以下に本発明の一実施例を図面を参照しなが
ら詳細に説明する。図１はＮＰＮトランジスタ（１０）
、第１の容量素子（１１）、および第２の容量素子（１
２）を示す断面図である。同図において、（１３）はＰ
型のシリコン半導体基板、（１４）は基板（１１）上に
形成したＮ型エピタキシャル層を貫通して複数の島領域
（１５）（１６）（１７）を形成するＰ＋型分離領域、
（１８）は基板（１１）と前記エピタキシャル層との間
に埋め込まれたＮ＋型埋め込み層である。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. Figure 1 shows an NPN transistor (10)
, the first capacitive element (11), and the second capacitive element (1
2) is a cross-sectional view showing. In the same figure, (13) is P
type silicon semiconductor substrate, (14) is a P+ type isolation region penetrating the N type epitaxial layer formed on the substrate (11) to form a plurality of island regions (15), (16), and (17);
(18) is an N+ type buried layer buried between the substrate (11) and the epitaxial layer.
【００１０】ＮＰＮトランジスタ（１０）は、島領域（
１５）底部の基板（１３）表面にＮ＋型埋め込み層（１
８）を具備し、島領域（１５）表面に形成したＰ型のベ
ース領域（１９）、ベース領域（１９）の表面に形成し
たＮ＋型エミッタ領域（２０）、および島領域（１５）
の表面に形成した、エミッタ領域（２０）より深いＮ＋
型コレクタ低抵抗領域（２１）から成り、各領域上には
Ａｌ電極（２２）がコンタクトする。コレクタ低抵抗領
域（２１）は、エミッタ形成以前に形成され、拡散時に
エミッタ領域（２０）と同程度の不純物濃度（１０２１
ａｔｏｍｓ．ｃｍ−２）を与えられるが、以降の各種熱
処理によってその最表面濃度はエミッタ領域（２０）の
ものより低下している。望ましくは、コレクタ低抵抗領
域（２１）をＮ＋型埋め込み層（１８）に連結するまで
深く形成する。[0010] The NPN transistor (10) has an island region (
15) N+ type buried layer (1) on the bottom substrate (13) surface
8), a P type base region (19) formed on the surface of the island region (15), an N+ type emitter region (20) formed on the surface of the base region (19), and the island region (15).
formed on the surface of the N+ emitter region (20), which is deeper than the emitter region (20).
It consists of a type collector low resistance region (21), and an Al electrode (22) is in contact with each region. The collector low resistance region (21) is formed before the emitter is formed, and has an impurity concentration (1021
atoms. cm-2), but its outermost surface concentration is lower than that of the emitter region (20) due to subsequent various heat treatments. Desirably, the collector low resistance region (21) is formed deep enough to connect to the N+ type buried layer (18).
【００１１】第１の容量素子（１１）は、島領域（１６
）底部の基板（１３）表面にＮ＋型埋め込み層（１８）
を具備し、島領域（１６）の表面にＮＰＮトランジスタ
（１０）のコレクタ低抵抗領域（２１）と同時形成され
たＮ＋型の下部電極領域（２３）、下部電極領域（２３
）の上に一様に形成したシリコン酸化膜又はシリコン窒
化膜から成る誘電体薄膜（２４）、誘電体薄膜（２４）
上に形成したＡｌ配線から成る上部電極（２５）、およ
び下部電極領域（２３）の一部にコンタクトする取出し
電極（２６）から成る。ＮＰＮトランジスタ（１０）の
Ｎ＋型コレクタ低抵抗領域（２１）と同時形成する下部
電極領域（２３）は、先にも述べたようにＮＰＮトラン
ジスタ（１０）のエミッタ領域（２０）より表面濃度が
やや低く、シート抵抗で４０〜６０Ω／□の値を示す。
そのため、下部にＮ＋型埋め込み層（１８）を設けて下
部電極領域（２３）の取出し抵抗を低減させている。誘
電体薄膜（２４）と上部電極（２５）を矩形の領域に一
様に形成できるので、占有面積は少い。[0011] The first capacitive element (11) has an island region (16
) N+ type buried layer (18) on the bottom substrate (13) surface
N+ type lower electrode region (23) and lower electrode region (23) formed simultaneously with the collector low resistance region (21) of the NPN transistor (10) on the surface of the island region (16).
dielectric thin film (24) made of a silicon oxide film or silicon nitride film uniformly formed on ), dielectric thin film (24)
It consists of an upper electrode (25) made of Al wiring formed above, and an extraction electrode (26) that contacts a part of the lower electrode region (23). As mentioned earlier, the lower electrode region (23) formed simultaneously with the N+ type collector low resistance region (21) of the NPN transistor (10) has a slightly higher surface concentration than the emitter region (20) of the NPN transistor (10). It has a low sheet resistance of 40 to 60Ω/□. Therefore, an N+ type buried layer (18) is provided at the bottom to reduce the extraction resistance of the lower electrode region (23). Since the dielectric thin film (24) and the upper electrode (25) can be uniformly formed in a rectangular area, the occupied area is small.
【００１２】第２の容量素子（１２）は、島領域（１７
）の底部に埋め込み層（１８）を形成せず、全体を基板
（１３）とエピタキシャル層、および分離領域（１４）
とエピタキシャル層との比較的低不純物濃度のＰＮ接合
で囲む。そして、島領域（１７）の表面にＮＰＮトラン
ジスタ（１０）のコレクタ低抵抗領域（２１）と同時形
成されたＮ＋型の下部電極領域（２７）と、下部電極領
域（２７）の上に複数に分離して形成したシリコン酸化
膜またはシリコン窒化膜から成る誘電体薄膜（２８）と
、誘電体薄膜（２８）の上に形成したＡｌ配線から成る
上部電極（２９）と、下部電極領域（２７）の表面にコ
ンタクトするＡｌ取出し電極（３０）から成る。
下部電極領域（２７）の最表面濃度は第１の容量素子（
１１）のものと同一である。[0012] The second capacitive element (12) has an island region (17
) without forming a buried layer (18) at the bottom of the substrate (13), an epitaxial layer, and an isolation region (14).
surrounded by a PN junction with a relatively low impurity concentration and an epitaxial layer. Then, an N+ type lower electrode region (27) is formed simultaneously with the collector low resistance region (21) of the NPN transistor (10) on the surface of the island region (17), and a plurality of N+ type lower electrode regions (27) are formed on the lower electrode region (27). A dielectric thin film (28) made of a silicon oxide film or a silicon nitride film formed separately, an upper electrode (29) made of an Al wiring formed on the dielectric thin film (28), and a lower electrode region (27). It consists of an Al extraction electrode (30) in contact with the surface of. The uppermost surface concentration of the lower electrode region (27) is the same as that of the first capacitive element (
It is the same as that of 11).
【００１３】図２は第２の容量素子（１２）の平面図で
ある。一様に形成された下部電極領域（２７）に対し、
誘電体薄膜（２８）が複数に分割され、分割された誘電
体薄膜（２８）上に上部電極（２９）が櫛歯状に延在す
る。取出し電極（３０）は、上部電極（２９）と相対向
するよう櫛歯状に延在し、その略全長にわたり下部電極
領域（２７）にオーミック接触する。FIG. 2 is a plan view of the second capacitive element (12). For the uniformly formed lower electrode region (27),
The dielectric thin film (28) is divided into a plurality of parts, and an upper electrode (29) extends in a comb-like shape on the divided dielectric thin film (28). The extraction electrode (30) extends in a comb-teeth shape so as to face the upper electrode (29), and is in ohmic contact with the lower electrode region (27) over substantially its entire length.
【００１４】第２の容量素子（１２）は、Ｎ＋型埋め込
み層（１８）を具備しないので基板（１３）とのＰＮ接
合が低濃度接合となり、接合容量（３１）が低減するの
で接地バイアスされた基板（１３）へのもれ電流を小さ
くできる。従って高周波回路に使用できる。一方、埋め
込み層（１８）を除去したことによる下部電極領域（２
７）の取出し抵抗の増大は、取出し電極（３０）を櫛歯
状とすることにより相殺できる。従って、容量のＱの周
波数特性を向上できる。Since the second capacitive element (12) does not have an N+ type buried layer (18), the PN junction with the substrate (13) becomes a low concentration junction, and the junction capacitance (31) is reduced so that it is not ground biased. The leakage current to the substrate (13) can be reduced. Therefore, it can be used in high frequency circuits. On the other hand, the lower electrode region (2) due to the removal of the buried layer (18)
The increase in the extraction resistance in 7) can be offset by making the extraction electrode (30) comb-shaped. Therefore, the frequency characteristics of the capacitance Q can be improved.
【００１５】このように、本発明は、高周波回路に利用
して好適な、基板（１３）へのもれ電流が少く且つ直列
抵抗を小さくできるものである。[0015] As described above, the present invention is suitable for use in high-frequency circuits, and can reduce leakage current to the substrate (13) and reduce series resistance.
【００１６】[0016]
【発明の効果】以上に説明した通り、本発明によれば、
埋め込み層（１８）を除去し且つ取出し電極（３０）を
櫛歯状とすることにより、基板（１３）へのもれ電流を
抑え且つ直列抵抗の増大をも抑制できる容量素子を組み
込むことができる。よって、低周波回路に第１の容量素
子（１１）を、高周波回路に第２の容量素子（１２）を
使用することにより、占有面積の増大を抑えつつ、最適
設計を行うことができる。[Effects of the Invention] As explained above, according to the present invention,
By removing the buried layer (18) and making the extraction electrode (30) comb-shaped, it is possible to incorporate a capacitive element that can suppress leakage current to the substrate (13) and also suppress an increase in series resistance. . Therefore, by using the first capacitive element (11) for the low frequency circuit and the second capacitive element (12) for the high frequency circuit, it is possible to perform an optimal design while suppressing an increase in the occupied area.
【図１】本発明を説明するための断面図である。FIG. 1 is a sectional view for explaining the present invention.
【図２】本発明を説明するための平面図である。FIG. 2 is a plan view for explaining the present invention.
【図３】従来例を説明するための断面図である。FIG. 3 is a sectional view for explaining a conventional example.
Claims (5)
に形成した逆導電型のエピタキシャル層と、前記エピタ
キシャル層を分離する一導電型の分離領域と、前記分離
領域で島状に形成された複数の島領域と、前記複数の島
領域の各々に形成したバイポーラトランジスタ、および
容量素子とを備え、前記バイポーラトランジスタは、前
記基板の表面に埋め込んだ逆導電型の埋め込み層と、前
記島領域の表面に形成した一導電型のベース領域と、前
記ベース領域の表面に形成した逆導電型のエミッタ領域
と、前記島領域の表面に形成した前記エミッタ領域より
深いコレクタ低抵抗領域とを備え、前記容量素子は、前
記島領域の表面に前記バイポーラトランジスタのコレク
タ低抵抗領域と同時形成された逆導電型の下部電極領域
と、前記下部電極領域の表面を被覆する誘電体薄膜と、
前記誘電体薄膜の上に形成した上部電極と、前記下部電
極の表面にコンタクトする櫛歯状の取出し電極とを備え
、且つ、前記第２の容量素子を形成した島領域は、前記
エピタキシャル層と前記分離領域とのＰＮ接合、および
前記エピタキシャル層と前記基板とのＰＮ接合で区画さ
れていることを特徴とする半導体集積回路。1. An island-shaped semiconductor substrate comprising a semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the substrate, an isolation region of one conductivity type separating the epitaxial layer, and the isolation region. a plurality of island regions formed in each of the plurality of island regions, a bipolar transistor formed in each of the plurality of island regions, and a capacitive element; a base region of one conductivity type formed on the surface of the base region, an emitter region of the opposite conductivity type formed on the surface of the base region, and a collector low resistance region deeper than the emitter region formed on the surface of the island region, The capacitive element includes a lower electrode region of an opposite conductivity type formed simultaneously with the collector low resistance region of the bipolar transistor on the surface of the island region, and a dielectric thin film covering the surface of the lower electrode region.
The island region, which includes an upper electrode formed on the dielectric thin film and a comb-like extraction electrode that contacts the surface of the lower electrode, and in which the second capacitive element is formed, is connected to the epitaxial layer. A semiconductor integrated circuit characterized in that it is divided by a PN junction with the isolation region and a PN junction between the epitaxial layer and the substrate.
ていることを特徴とする請求項１に記載の半導体集積回
路。2. The semiconductor integrated circuit according to claim 1, wherein the capacitive element is used in a high frequency circuit.
に形成した逆導電型のエピタキシャル層と、前記エピタ
キシャル層を分離する一導電型の分離領域と、前記分離
領域で島状に形成された複数の島領域と、前記複数の島
領域の各々に形成したバイポーラトランジスタ、第１の
容量素子、および第２の容量素子とを備え、前記バイポ
ーラトランジスタは、前記基板の表面に埋め込んだ逆導
電型の埋め込み層と、前記島領域の表面に形成した一導
電型のベース領域と、前記ベース領域の表面に形成した
逆導電型のエミッタ領域と、前記島領域の表面に形成し
た前記エミッタ領域より深いコレクタ低抵抗領域とを備
え、前記第１の容量素子は、前記基板の表面に埋め込ん
だ逆導電型の埋め込み層と、前記島領域の表面に前記バ
イポーラトランジスタのコレクタ低抵抗領域と同時形成
された逆導電型の下部電極領域と、前記下部電極領域の
表面を一様に被覆する誘電体薄膜と、前記誘電体薄膜の
上に形成した上部電極と、前記下部電極領域の表面にコ
ンタクトする取出し電極とを備え、前記第２の容量素子
は、前記島領域の表面に前記バイポーラトランジスタの
コレクタ低抵抗領域と同時形成された逆導電型の下部電
極領域と、前記下部電極領域の表面を被覆する誘電体薄
膜と、前記誘電体薄膜の上に形成した上部電極と、前記
下部電極の表面にコンタクトする櫛歯状の取出し電極と
を備え、且つ、前記第２の容量素子を形成した島領域は
、前記エピタキシャル層と前記分離領域とのＰＮ接合、
および前記エピタキシャル層と前記基板とのＰＮ接合で
区画されていることを特徴とする半導体集積回路。3. An island-shaped semiconductor substrate formed of a semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the substrate, an isolation region of one conductivity type that separates the epitaxial layer, and the isolation region. a plurality of island regions, a bipolar transistor formed in each of the plurality of island regions, a first capacitor element, and a second capacitor element; a buried layer of the mold, a base region of one conductivity type formed on the surface of the island region, an emitter region of the opposite conductivity type formed on the surface of the base region, and the emitter region formed on the surface of the island region. and a deep collector low resistance region, and the first capacitive element is formed simultaneously with a buried layer of an opposite conductivity type buried in the surface of the substrate and a collector low resistance region of the bipolar transistor on the surface of the island region. a lower electrode region of opposite conductivity type, a dielectric thin film uniformly covering the surface of the lower electrode region, an upper electrode formed on the dielectric thin film, and an extraction contacting the surface of the lower electrode region. the second capacitive element has a lower electrode region of an opposite conductivity type formed simultaneously with the collector low resistance region of the bipolar transistor on the surface of the island region, and covers the surface of the lower electrode region. The island region includes a dielectric thin film, an upper electrode formed on the dielectric thin film, and a comb-like extraction electrode that contacts the surface of the lower electrode, and in which the second capacitive element is formed. , a PN junction between the epitaxial layer and the isolation region,
and a semiconductor integrated circuit, characterized in that the epitaxial layer is divided by a PN junction between the epitaxial layer and the substrate.
前記第２の容量素子は高周波回路に使い分けされている
ことを特徴とする請求項３に記載の半導体集積回路。4. The first capacitive element is connected to a low frequency circuit,
4. The semiconductor integrated circuit according to claim 3, wherein the second capacitive element is used for a high frequency circuit.
ランジスタのエミッタ領域よりシート抵抗が大であるこ
とを特徴とする請求項１又は請求項２に記載の半導体集
積回路。5. The semiconductor integrated circuit according to claim 1, wherein the lower electrode region has a higher sheet resistance than the emitter region of the bipolar transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12390291A JP3157187B2 (en) | 1991-05-28 | 1991-05-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12390291A JP3157187B2 (en) | 1991-05-28 | 1991-05-28 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04350962A true JPH04350962A (en) | 1992-12-04 |
| JP3157187B2 JP3157187B2 (en) | 2001-04-16 |
Family
ID=14872169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12390291A Expired - Lifetime JP3157187B2 (en) | 1991-05-28 | 1991-05-28 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3157187B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010034598A (en) * | 2009-11-12 | 2010-02-12 | Renesas Technology Corp | Semiconductor device |
-
1991
- 1991-05-28 JP JP12390291A patent/JP3157187B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010034598A (en) * | 2009-11-12 | 2010-02-12 | Renesas Technology Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3157187B2 (en) | 2001-04-16 |
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