JPS62165363A - High dielectric strength power integrated circuit - Google Patents
High dielectric strength power integrated circuitInfo
- Publication number
- JPS62165363A JPS62165363A JP61004991A JP499186A JPS62165363A JP S62165363 A JPS62165363 A JP S62165363A JP 61004991 A JP61004991 A JP 61004991A JP 499186 A JP499186 A JP 499186A JP S62165363 A JPS62165363 A JP S62165363A
- Authority
- JP
- Japan
- Prior art keywords
- potential
- layer
- film
- type
- high resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010408 film Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 239000010409 thin film Substances 0.000 claims abstract description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 238000002955 isolation Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 241001428214 Polyides Species 0.000 description 2
- 239000002689 soil Substances 0.000 description 2
- 241000238557 Decapoda Species 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は高耐圧パワー集積回路（ＩＣ）に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to high voltage power integrated circuits (ICs).
従来、５００ Ｖ以上の耐圧をもち、大きなパワーを取
り出せる高耐圧パワーＩＣは非常に難しいとされて来た
。その理由の−っは、単体の素子では生じない配線の問
題が生じることと、一つの表面に大きな電圧差のある端
子が共存することである。Conventionally, it has been considered extremely difficult to create a high-voltage power IC that has a breakdown voltage of 500 V or more and can extract a large amount of power. The reasons for this are that wiring problems occur that would not occur with a single element, and that terminals with large voltage differences coexist on one surface.
ＭＯＳＦＥＴの例の第６図を用いて説明する。第５図で
、１０は高抵抗Ｐ−基板、１１は高抵抗エビ層、１２は
ｎ土塊め込み、１３はｎ層へのコンタクトのためのｎ十
拡散層、１４は素子分離のためのＰ−拡散層、１９はＰ
ベース拡散層、２０はｎ ソース層１８はゲートポリシ
リコン電極、１６．１７はソース、ドレイン電極である
。ここで−っ目の問題は、ソース電極の配線２１がドレ
イン層１３の上を通過したり、ドレイン電極の配線２２
がアイソレーションの拡散層１４の上を通っていること
である。ソース配線の直下のｎ一層１１には反転層や空
乏層が出来やすく、その電位はソース電極の電位と近く
なっている。このため配線２１の直下に高電位となるド
レイン拡散層があると、そのｎｎ＋接合に高電界が生じ
てしまう。一方ドレイン配線層２２の直下は反対に空乏
化しにくくなっているので、この下にアイソレージ目ン
の拡散層１４があるとＰ＋ｎ−の接合に高電圧が印加さ
れた場合空乏層の伸びが抑制されてしまうので高耐圧を
実現できない。このため通常は酸化膜１５を厚くしてこ
れを防いでいたが、この方法では５００Ｖ以上の高耐圧
パワーＩＣの実現は難しい。This will be explained using FIG. 6, which shows an example of a MOSFET. In Fig. 5, 10 is a high-resistance P-substrate, 11 is a high-resistance shrimp layer, 12 is an n soil lump embedded, 13 is an n-diffusion layer for contacting the n layer, and 14 is a P-substrate for element isolation. - Diffusion layer, 19 is P
A base diffusion layer 20, an n source layer 18 a gate polysilicon electrode, and 16 and 17 a source and drain electrode. The second problem here is that the wiring 21 of the source electrode passes over the drain layer 13, or the wiring 21 of the drain electrode
passes over the isolation diffusion layer 14. An inversion layer and a depletion layer are likely to be formed in the n-layer 11 directly under the source wiring, and the potential thereof is close to the potential of the source electrode. Therefore, if there is a drain diffusion layer having a high potential directly under the wiring 21, a high electric field will be generated at the nn+ junction. On the other hand, since the area directly under the drain wiring layer 22 is difficult to deplete, if there is an isolation diffusion layer 14 under this layer, the extension of the depletion layer is suppressed when a high voltage is applied to the P+n- junction. Therefore, high voltage resistance cannot be achieved. For this reason, this is usually prevented by thickening the oxide film 15, but with this method it is difficult to realize a high breakdown voltage power IC of 500V or more.
第２にＰ ＨＩ３とｎ一層１１の作るＰｎ接合の耐圧は
ゲート電極１８がフィールドプレートの役目をしている
が、このようなフィールドプレート構造ではフィールド
プレートの端又はＰｎ接合の曲率の小さい所に電界が集
中してしまい、５０（）７以上のＷＮＪＥＥを出すこと
はきわめてむずかしい。第６図のようにガードリングを
用いれば良いが、これではソースとドレインの間が長く
なり、一つの素子の占める面積が増大してしまい、単位
面積あたりの素子のオン抵抗が増大してしまう欠点があ
る。Second, the breakdown voltage of the Pn junction formed by the PHI3 and the n-layer 11 is determined by the gate electrode 18 acting as a field plate, but in such a field plate structure, the breakdown voltage of the Pn junction formed by the PHI3 and the n-layer 11 is The electric field is concentrated and it is extremely difficult to achieve a WNJEE of 50()7 or higher. A guard ring could be used as shown in Figure 6, but this would lengthen the distance between the source and drain, increasing the area occupied by one element and increasing the on-resistance of the element per unit area. There are drawbacks.
本発明は上記のような困難を解決するためになされたも
ので１００ＯＶ以上のパワーＩＣを可能としたものであ
る。The present invention was made in order to solve the above-mentioned difficulties, and enables a power IC of 100 OV or more.
本発明は高電圧が印加された場合に空乏層が基板表面に
生ずる部分に絶縁膜を介して高抵抗の薄膜をおき、この
膜の一端の電位を空乏層の生じた接合を形成する一導伝
型の領域の電位と等しくし、他端の膜の電位を反対導伝
型と等しくなしたことを特徴とする２つ以上の素子を集
積した高耐圧パワーＩＣである。具体的に第１図を用い
て説明する。第５図と異っている点は、高抵抗膜２３、
絶縁膜２４を形成し、この上に配線２１．２２を設けて
いることである。高抵抗薄膜は両端の電位がアース電位
（ソース電位）とドレイン電位に固定され、ドレインが
高Ｗ！田になった時には、高抵抗膜２３に微小電流が流
れ、を位傾斜ができる。この電位傾斜は上にある配線の
影響をうけないので、下にある基板の表面に配線の影響
が及ぶことはない。更に一般にこのような高抵抗膜を設
けると、接合の耐圧が向上する。これは高抵抗薄膜に電
位傾斜が生じているために第２図に示すように高抵抗膜
によってその下に生じた空乏層の厚みがゆるやかに薄く
なり、電界の集中が軽減されるためである。従ってソー
スとドレインの間隔を狭くすることができ、素子抵抗を
下げられる。In the present invention, a high-resistance thin film is placed via an insulating film in a portion where a depletion layer is formed on the substrate surface when a high voltage is applied, and the potential at one end of this film is applied to a conductor that forms a junction where a depletion layer is formed. This is a high-voltage power IC integrated with two or more elements, characterized in that the potential of the conductive type region is made equal to the potential of the film at the other end, and the potential of the film at the other end is made equal to that of the opposite conductive type. This will be specifically explained using FIG. 1. The difference from FIG. 5 is that the high resistance film 23,
An insulating film 24 is formed, and wirings 21 and 22 are provided on the insulating film 24. The potential at both ends of a high-resistance thin film is fixed to the ground potential (source potential) and drain potential, and the drain has a high W! When the voltage is high, a minute current flows through the high resistance film 23, creating a voltage gradient. Since this potential gradient is not affected by the wiring above, the surface of the underlying substrate is not affected by the wiring. Furthermore, providing such a high resistance film generally improves the breakdown voltage of the junction. This is because the high-resistance thin film has a potential gradient, so as shown in Figure 2, the thickness of the depletion layer formed under the high-resistance film gradually becomes thinner, reducing the concentration of the electric field. . Therefore, the distance between the source and drain can be narrowed, and the element resistance can be lowered.
以上のように本発明は高抵抗膜に微小電流を流すことに
よって基板表面の電位が固定されることを利用して、接
合の高耐圧化と配線の影響をなくすという一石二鳥の役
目をもたせた構造を提供し、５００Ｖ以上の高耐圧パワ
ーＩＣが容易に実現できる０
〔発明の実施例〕
第１図の場合のＭＯＳＦＥＴについて製作プルセスを述
べる。まず高抵抗Ｐ−基板１０にイオン注入法を用いて
ｎ十層１２を形成する。この上、気相成長によって高抵
抗ｎ土層１１を形成し・アイソレーション拡散層１４、
及び埋め込みｎ＋十層、２とコンタクトするｎ＋ドレイ
ン層１３を拡散形成する。この後、全体に厚い酸化膜を
形成し、ゲート酸化膜２５とベース拡散層１９を形成す
る部分だけ厚い酸化膜を取り除く。As described above, the present invention utilizes the fact that the potential on the substrate surface is fixed by passing a minute current through a high-resistance film to create a structure that can kill two birds with one stone by increasing the breakdown voltage of the junction and eliminating the influence of wiring. Embodiments of the Invention The manufacturing process for the MOSFET shown in FIG. 1 will be described. First, an n0 layer 12 is formed on a high resistance P-substrate 10 using an ion implantation method. On top of this, a high resistance n-soil layer 11 is formed by vapor phase growth, an isolation diffusion layer 14,
Then, an n+ drain layer 13 in contact with the buried n+ layer 2 is formed by diffusion. Thereafter, a thick oxide film is formed over the entire surface, and only the portions where the gate oxide film 25 and base diffusion layer 19 are to be formed are removed.
そして、ゲート酸化膜２５を形成した後ポリシリコンを
形成しへ必要な部分だけを残して取り去る。After forming the gate oxide film 25, polysilicon is formed and removed leaving only the necessary portions.
このポリシリコンをマスクとして、Ｐベース拡散１９と
ｎ＋ソース拡散２０を行う。更に全体を絶縁膜でおおい
、１３．１４．１つの各層へのコンタクトホールを形成
し、Ａ７電極１６．１７．２５．２６を形成する。Using this polysilicon as a mask, P base diffusion 19 and n+ source diffusion 20 are performed. Further, the whole is covered with an insulating film, and 13.14. contact holes are formed for each layer, and A7 electrodes 16.17.25.26 are formed.
この上からアモルファスシリコンを形成し、２３を形成
する。次に全体をポリイシド等の絶縁膜でおおい、１６
．１７とコンタクトする配線２１．２２を形成して終了
する。ここでアモルファスシリコンのかわりに５ＩＰＯ
８を用い、ポリイシドのかわりにＣＶＤ酸化膜を用いて
も良い。第３図は別の実施例で、高抵抗膜の電位の片方
をソースではなくゲートに固定したもので、第１図と同
じ付号のものは同じ付号で示している。Amorphous silicon is formed on this to form 23. Next, the whole is covered with an insulating film such as polyide, and 16
．． The process ends by forming wirings 21 and 22 in contact with 17. Here, 5IPO is used instead of amorphous silicon.
8, and a CVD oxide film may be used instead of the polyide. FIG. 3 shows another embodiment in which one of the potentials of the high-resistance film is fixed to the gate instead of the source, and parts with the same numbers as in FIG. 1 are indicated by the same numbers.
また！４図は導電変調型ＭＯ８ＦＥＴの実施例を示す。Also! FIG. 4 shows an example of a conductivity modulation type MO8FET.
導電調型ＦＥＴではドレイン層はｎ＋ではなく、Ｐ土層
であり、ドレインから正孔をｎ土層１１ に注入し、こ
こにキャリアの蓄積をさせ、導電変調を起して素子のオ
ン抵抗が下がる。またこれらの実施例だけでなく、バイ
ポーラトランジスタ等を組み込んだＩＣにも本発明は有
効である。In the conductivity modulation type FET, the drain layer is not an n+ layer but a p layer, and holes are injected from the drain into the n layer 11, where carriers are accumulated, causing conductivity modulation and increasing the on-resistance of the device. Go down. Furthermore, the present invention is effective not only in these embodiments but also in ICs incorporating bipolar transistors and the like.
第１図及び第２図は本発明の詳細な説明するため図、第
３図及び第４図は本発明の詳細な説明するための図、第
５図及び第６図は従来例を説明するための図である。
２３・・高抵抗膜、２４・・・絶縁膜
２１．２２・・・配線。
代理人 弁理士 則 近 憲 佑
同 竹 花 喜久男
１／）ｍ −〜 偽1 and 2 are diagrams for explaining the present invention in detail, Figures 3 and 4 are diagrams for explaining the invention in detail, and Figures 5 and 6 are diagrams for explaining the conventional example. This is a diagram for 23...High resistance film, 24...Insulating film 21.22...Wiring. Agent Patent attorney Nori Chika Ken Yudo Takehana Kikuo 1/)m -~ False
Claims (5)
接合の空乏層が基板表面に生ずる部分に絶縁膜を介して
高抵抗の薄膜を設け、この膜の一端の電位を接合の一導
電型の領域の電位とほぼ等しくおき、かつ他の一端の電
位を反対導電型の領域の電位とほぼ等しくしたことを特
徴とする高耐圧パワー集積回路。(1) When high voltage is applied between the terminals of the IC, Pn
A high-resistance thin film is provided via an insulating film in the area where the depletion layer of the junction occurs on the substrate surface, and the potential at one end of this film is set approximately equal to the potential in one conductivity type region of the junction, and the potential at the other end is A high-voltage power integrated circuit characterized in that the voltage is approximately equal to the potential of a region of opposite conductivity type.
他端の電位をドレイン電極の電位と等しくしたことを特
徴とする特許請求の範囲第１項記載の高耐圧パワー集積
回路。(2) Make one end of the high-resistance film equal to the potential of the gate electrode,
2. The high voltage power integrated circuit according to claim 1, wherein the potential of the other end is equal to the potential of the drain electrode.
とを特徴とする特許請求の範囲第１項又は第２項記載の
高耐圧パワー集積回路。(3) A high-voltage power integrated circuit according to claim 1 or 2, characterized in that an electrode is provided on the high-resistance thin film via an insulating film.
る配線電極であることを特徴とする特許請求の範囲第３
項記載の高耐圧パワー集積回路。(4) Claim 3, characterized in that the electrode provided through the insulating film is a wiring electrode that connects two elements.
High-voltage power integrated circuit described in Section 1.
シリコンで構成したことを特徴とする特許請求の範囲第
１項記載の高耐圧パワー集積回路。(5) The high-voltage power integrated circuit according to claim 1, wherein the high-resistance film is made of amorphous silicon or high-resistance polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61004991A JP2547729B2 (en) | 1986-01-16 | 1986-01-16 | High voltage power integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61004991A JP2547729B2 (en) | 1986-01-16 | 1986-01-16 | High voltage power integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62165363A true JPS62165363A (en) | 1987-07-21 |
| JP2547729B2 JP2547729B2 (en) | 1996-10-23 |
Family
ID=11599073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61004991A Expired - Lifetime JP2547729B2 (en) | 1986-01-16 | 1986-01-16 | High voltage power integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2547729B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02153529A (en) * | 1987-10-19 | 1990-06-13 | American Teleph & Telegr Co <Att> | Resistive electric field shield for high voltage device |
| JPH02283074A (en) * | 1989-04-25 | 1990-11-20 | Fuji Electric Co Ltd | Semiconductor integrated circuit device |
| EP0764988A3 (en) * | 1995-08-31 | 1998-03-04 | Texas Instruments Incorporated | Isolated power transistor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7374795B2 (en) | 2020-02-05 | 2023-11-07 | 株式会社東芝 | semiconductor equipment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5853860A (en) * | 1981-09-26 | 1983-03-30 | Toshiba Corp | High breakdown voltage planar type semiconductor device |
-
1986
- 1986-01-16 JP JP61004991A patent/JP2547729B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5853860A (en) * | 1981-09-26 | 1983-03-30 | Toshiba Corp | High breakdown voltage planar type semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02153529A (en) * | 1987-10-19 | 1990-06-13 | American Teleph & Telegr Co <Att> | Resistive electric field shield for high voltage device |
| JPH02283074A (en) * | 1989-04-25 | 1990-11-20 | Fuji Electric Co Ltd | Semiconductor integrated circuit device |
| EP0764988A3 (en) * | 1995-08-31 | 1998-03-04 | Texas Instruments Incorporated | Isolated power transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2547729B2 (en) | 1996-10-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2585331B2 (en) | High breakdown voltage planar element | |
| US6190948B1 (en) | Method of forming power semiconductor devices having overlapping floating field plates for improving breakdown voltage capability | |
| US6570229B1 (en) | Semiconductor device | |
| JPH08264787A (en) | Edge termination method of power mosfet and its structure | |
| JPH03270273A (en) | Semiconductor device and its manufacture | |
| JPH0457111B2 (en) | ||
| US6914270B2 (en) | IGBT with PN insulation and production method | |
| JP2814079B2 (en) | Semiconductor integrated circuit and manufacturing method thereof | |
| JP3354127B2 (en) | High voltage element and method of manufacturing the same | |
| KR930005509B1 (en) | Mos type integrated circuit | |
| JPS62165363A (en) | High dielectric strength power integrated circuit | |
| KR19990069332A (en) | Trench gate type MOS device and its manufacturing method | |
| KR19980702335A (en) | A method of manufacturing a resurf semiconductor device and a semiconductor device manufactured by such a method | |
| JPH0888290A (en) | Semiconductor device and using method therefor | |
| JPH07142731A (en) | Power device and method for forming it | |
| US5962898A (en) | Field-effect transistor | |
| JPH08116049A (en) | Insulated-gate semiconductor device | |
| JPH0974187A (en) | High withstand voltage lateral type semiconductor device | |
| JP3217552B2 (en) | Horizontal high voltage semiconductor device | |
| JP2004228553A (en) | Insulated gate semiconductor device and its manufacturing method | |
| JPH11307768A (en) | Silicon carbide semiconductor device and manufacture thereof | |
| JPH03171774A (en) | High withstand voltage planar element | |
| JP3435171B2 (en) | High voltage semiconductor device | |
| JP3157187B2 (en) | Semiconductor integrated circuit | |
| JPS6174361A (en) | Buried resistance semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |