JPH04334048A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPH04334048A JPH04334048A JP10297891A JP10297891A JPH04334048A JP H04334048 A JPH04334048 A JP H04334048A JP 10297891 A JP10297891 A JP 10297891A JP 10297891 A JP10297891 A JP 10297891A JP H04334048 A JPH04334048 A JP H04334048A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- lead frame
- lead
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 abstract 1
- 239000000725 suspension Substances 0.000 description 2
- 101100008048 Caenorhabditis elegans cut-4 gene Proteins 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置用パッケージ
に関し、特に外部リードが２方向から出ているフラット
タイプの表面実装型パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for a semiconductor device, and more particularly to a flat type surface mount package having external leads coming out from two directions.
【０００２】0002
【従来の技術】従来の半導体装置用パッケージは、図２
（ａ）に示すように、図２（ｂ）に示すリードフレーム
をパッケージ基体１に収納してあり、外部リード２の出
ていない辺に、リードフレームのつりピン７の切断残り
３が出ていた。[Prior Art] A conventional semiconductor device package is shown in FIG.
As shown in FIG. 2(a), the lead frame shown in FIG. 2(b) is housed in the package base 1, and the cut portions 3 of the suspension pins 7 of the lead frame are exposed on the side where the external leads 2 are not exposed. Ta.
【０００３】0003
【発明が解決しようとする課題】この従来の半導体装置
用パッケージでは、リードフレームとパッケージ基体と
の相対位置精度のばらつき、およびつりピン切断位置精
度のばらつきにより、つりピン切断残りの寸法５１のば
らつきが大きかった。従って、半導体装置用パッケージ
の外部リードの出ていない辺を基準にプリント基板への
実装を行うと、外部リードとプリント基板実装部との位
置精度が悪く、実装しずらいという欠点があった。[Problems to be Solved by the Invention] In this conventional semiconductor device package, due to variations in the relative positional accuracy between the lead frame and the package base and variations in the precision of the cutting position of the hanging pins, the remaining dimension 51 after cutting the hanging pins varies. was big. Therefore, if the semiconductor device package is mounted on a printed circuit board based on the side where the external leads do not extend, there is a drawback that the positional accuracy between the external leads and the printed circuit board mounting portion is poor, making mounting difficult.
【０００４】0004
【課題を解決するための手段】本発明の半導体装置用パ
ッケージは、外部リードの出ていない辺の外部リードか
ら一定の位置に、リードフレームの一部から成る凸部を
有する。SUMMARY OF THE INVENTION A package for a semiconductor device of the present invention has a convex portion made of a part of a lead frame at a certain position from the external lead on the side where the external lead does not extend.
【０００５】[0005]
【実施例】次に図面を参照して説明する。図１（ａ）は
本発明の実施例の半導体装置用パッケージの平面図であ
る。図１（ｂ）に示すリードフレームをパッケージ基体
１に収納した構造で、実装位置決め用凸部４を有してい
る。凸部４と外部リード２とは、同一リードフレームよ
り形成されるため、実装位置決め寸法５の精度は、リー
ドフレーム作成精度に等しく、極めて高い。ただし、凸
部４は、つりピン７の切断残り３よりも常に大きくなる
様に設計されなければならない。[Embodiment] Next, a description will be given with reference to the drawings. FIG. 1(a) is a plan view of a package for a semiconductor device according to an embodiment of the present invention. It has a structure in which a lead frame shown in FIG. 1(b) is housed in a package base 1, and has a convex portion 4 for mounting positioning. Since the convex portion 4 and the external lead 2 are formed from the same lead frame, the accuracy of the mounting positioning dimension 5 is equal to the lead frame production accuracy and is extremely high. However, the convex portion 4 must be designed so that it is always larger than the cut remaining portion 3 of the suspension pin 7.
【０００６】[0006]
【発明の効果】以上説明したように本発明は、パッケー
ジ基体の外部リードの出ていない辺の外部リードから一
定の位置に、リードフレームの一部から成る凸部を設け
ることにより、外部リードの出ていない辺を基準とする
実装方式における実装精度を極めて高くできるという効
果がある。Effects of the Invention As explained above, the present invention provides a convex portion made of a part of the lead frame at a certain position from the external lead on the side of the package base where the external lead does not protrude. This has the effect of making it possible to extremely increase the mounting accuracy in a mounting method that uses the side that does not appear as a reference.
【図１】（ａ）は本発明の一実施例の平面図、（ｂ）は
本発明の半導体装置用パッケージに使用するリードフレ
ームの例の平面図である。FIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a plan view of an example of a lead frame used in a semiconductor device package of the present invention.
【図２】従来の例及びそのリードフレームの平面図であ
る。FIG. 2 is a plan view of a conventional example and its lead frame.
１ パッケージ基体 ２ 外部リード ３ つりピン切断残り ４ 実装位置決め用凸部 ５ 実装位置決め寸法 ７ つりピン 1 Package base 2 External lead 3. Remaining hanging pin cut 4 Convex part for mounting positioning 5 Mounting positioning dimensions 7 Hanging pin
Claims (1)
納して成り、前記リードフレームの外部リードが前記パ
ッケージ基体の２方向から出ている半導体装置用パッケ
ージにおいて、外部リードの出ていない１辺、あるいは
２辺の外部リードから一定の位置に、リードフレームの
一部から成る凸部を有することを特徴とする半導体装置
用パッケージ。1. In a package for a semiconductor device, which comprises a lead frame housed in a package base, and in which external leads of the lead frame protrude from two directions of the package base, one side from which the external leads do not protrude, or two sides. A semiconductor device package characterized by having a protrusion made of a part of a lead frame at a certain position from an external lead on a side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10297891A JPH04334048A (en) | 1991-05-09 | 1991-05-09 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10297891A JPH04334048A (en) | 1991-05-09 | 1991-05-09 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04334048A true JPH04334048A (en) | 1992-11-20 |
Family
ID=14341830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10297891A Pending JPH04334048A (en) | 1991-05-09 | 1991-05-09 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04334048A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04150055A (en) * | 1990-10-15 | 1992-05-22 | Seiko Epson Corp | Semiconductor package |
-
1991
- 1991-05-09 JP JP10297891A patent/JPH04334048A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04150055A (en) * | 1990-10-15 | 1992-05-22 | Seiko Epson Corp | Semiconductor package |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970325 |