JPH04316351A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04316351A JPH04316351A JP8281491A JP8281491A JPH04316351A JP H04316351 A JPH04316351 A JP H04316351A JP 8281491 A JP8281491 A JP 8281491A JP 8281491 A JP8281491 A JP 8281491A JP H04316351 A JPH04316351 A JP H04316351A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- connection hole
- metal wiring
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims 7
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 235000012239 silicon dioxide Nutrition 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- 238000001020 plasma etching Methods 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 4
- 229920001296 polysiloxane Polymers 0.000 claims description 4
- -1 polysiloxane Polymers 0.000 claims description 4
- 229920002050 silicone resin Polymers 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 29
- 239000011229 interlayer Substances 0.000 abstract description 10
- 238000009413 insulation Methods 0.000 abstract 12
- 238000000034 method Methods 0.000 description 12
- 239000010931 gold Substances 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 7
- 229910052593 corundum Inorganic materials 0.000 description 7
- 229910001845 yogo sapphire Inorganic materials 0.000 description 7
- 229920003217 poly(methylsilsesquioxane) Polymers 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- BYFGZMCJNACEKR-UHFFFAOYSA-N aluminium(i) oxide Chemical compound [Al]O[Al] BYFGZMCJNACEKR-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 3
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は，半導体装置の多層配線
の形成方法に関する。近年のコンピュータシステムの高
速化の要求に伴い，半導体集積回路の高集積化，高速化
が益々要求されている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming multilayer wiring in a semiconductor device. With the recent demand for higher speed computer systems, there is an increasing demand for higher integration and higher speed semiconductor integrated circuits.
【０００２】このため，半導体素子の微細化のみならず
，配線の微細化，多層化が益々重要となってきている。
この様な多層配線を実現するには，層間絶縁膜の平坦化
技術と，多層配線の配線層間を接続する微細な接続孔に
配線を形成する技術の開発が特に重要である。For this reason, not only the miniaturization of semiconductor elements, but also the miniaturization and multilayering of interconnections are becoming increasingly important. In order to realize such multilayer wiring, it is particularly important to develop techniques for flattening interlayer insulating films and technology for forming wiring in minute contact holes that connect wiring layers in multilayer wiring.
【０００３】これによって，多層配線の信頼性を高めて
やる必要がある。[0003] Accordingly, it is necessary to improve the reliability of multilayer wiring.
【０００４】0004
【従来の技術】従来の多層配線の形成においては，層間
絶縁膜の平坦化法として，ＳＯＧ塗布法，有機膜塗布法
，エッチバック法等が用いられている。2. Description of the Related Art In the conventional formation of multilayer interconnections, SOG coating, organic film coating, etch-back, and the like are used as methods for planarizing interlayer insulating films.
【０００５】この中で，ポリシロキサン，シリコーン樹
脂等の塗布による平坦化は工程が簡単であり，平坦性に
優れている。配線層間の接続孔の断面形状は，微細化と
共に急峻でアスペクト比（深さに対する直径の比）の大
きなものとなってくる。Among these, flattening by coating polysiloxane, silicone resin, etc. is a simple process and has excellent flatness. The cross-sectional shape of connection holes between wiring layers becomes steeper and has a larger aspect ratio (ratio of diameter to depth) with miniaturization.
【０００６】そのため，従来のスパッタ法で形成した配
線層は，深い接続孔での配線金属膜の被覆性が悪いため
，配線間の接続不良が重大な問題になってきている。
この問題を解決できる多層配線技術には，微細接続孔に
金属を選択的に埋め込む方法が有望である。[0006] For this reason, wiring layers formed by conventional sputtering methods have poor coverage of wiring metal films in deep connection holes, and poor connections between wirings have become a serious problem. A promising multilayer interconnection technology that can solve this problem is the method of selectively embedding metal into microscopic contact holes.
【０００７】現在のこの技術の主流は，原料ガスとして
六弗化タングステン（ＷＦ６）， 還元剤として水素
（Ｈ２）やシラン（ＳｉＨ４）等を使用したタングステ
ン（Ｗ）の選択ＣＶＤ技術である。[0007] The current mainstream of this technology is a tungsten (W) selective CVD technology using tungsten hexafluoride (WF6) as a raw material gas and hydrogen (H2), silane (SiH4), etc. as a reducing agent.
【０００８】ポリシロキサン，シリコーン樹脂等の塗布
による層間絶縁膜の平坦化と，Ｗの選択ＣＶＤ法による
配線接続孔への配線形成を組み合わせた多層配線の形成
は重要である。[0008] It is important to form multilayer wiring by combining flattening of an interlayer insulating film by applying polysiloxane, silicone resin, etc., and forming wiring into wiring connection holes by selective W CVD.
【０００９】[0009]
【発明が解決しようとする課題】塗布法では，下層配線
パターンの粗密，または寸法の大小により，下層配線上
の塗布膜厚が異なるため，弗化炭素系の反応ガスを用い
た反応性イオンエッチング（ＲＩＥ）法で接続孔を開口
した場合，パターン密度が低い領域の接続孔は長時間オ
ーバーエッチングされる。[Problem to be solved by the invention] In the coating method, the thickness of the coating film on the lower wiring pattern varies depending on the density or size of the lower wiring pattern, so reactive ion etching using a carbon fluoride-based reactive gas is required. When connecting holes are opened using the (RIE) method, the connecting holes in areas with low pattern density are over-etched for a long time.
【００１０】そのため接続孔底面に露出した下層配線表
面上に，炭素（Ｃ），水素（Ｈ），弗素（Ｆ）原子等か
らなる残留物が残る。この様な残留物は，通常の酸素（
Ｏ２）プラズマ処理や化学処理では容易に除去できない
。Therefore, residues consisting of carbon (C), hydrogen (H), fluorine (F) atoms, etc. remain on the surface of the lower layer wiring exposed at the bottom of the connection hole. Such residues are produced by normal oxygen (
O2) cannot be easily removed by plasma treatment or chemical treatment.
【００１１】そのため，この後の選択ＣＶＤにより接続
孔へＷを埋め込む工程で前記残留物が残っている配線金
属上の接続孔には，Ｗが安定に成長しないという問題が
あった。[0011] Therefore, in the subsequent step of burying W into the contact hole by selective CVD, W does not grow stably in the contact hole on the wiring metal where the residue remains.
【００１２】さらに，上記残留物の少ない条件でＲＩＥ
を行った場合には，下層配線の金属がスパッタされて接
続孔の側壁部に付着するため，Ｗが側壁部に成長してし
まうという問題があった。Furthermore, RIE is performed under the above-mentioned conditions with less residue.
If this is done, the metal of the lower layer wiring is sputtered and adheres to the side wall of the connection hole, resulting in the problem that W grows on the side wall.
【００１３】本発明は，このような問題点に鑑みてなさ
れたものであって，特に，塗布法による層間絶縁膜の平
坦化と，金属の選択ＣＶＤ法による配線接続孔への金属
埋め込みを確実に行うことにより，配線の信頼性を向上
させることができる多層配線の形成方法を提供すること
を目的としている。[0013] The present invention was made in view of these problems, and in particular, it is possible to flatten an interlayer insulating film by a coating method, and to ensure that metal is filled into wiring connection holes by a metal selective CVD method. The purpose of the present invention is to provide a method for forming multilayer wiring that can improve the reliability of the wiring by performing the following steps.
【００１４】[0014]
【課題を解決するための手段】図１は本発明の原理説明
図である。図において，１は半導体基板，２は第１の金
属配線，３は第１の絶縁膜，４は第２の絶縁膜，５は第
３の絶縁膜，６は接続孔，７は接続用金属，８は第２の
金属配線である。[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a first metal wiring, 3 is a first insulating film, 4 is a second insulating film, 5 is a third insulating film, 6 is a connection hole, and 7 is a connection metal. , 8 are second metal wirings.
【００１５】前記の問題点は，本発明の如く，半導体基
板１上に第１の金属配線２を形成する工程と，該第１の
金属配線を覆って，該半導体基板１上に第１の絶縁膜３
を形成する工程と， 該第１の絶縁膜３の上に， 第２
の絶縁膜４を形成する工程と， 該第２の絶縁膜４の上
に， 第３の絶縁膜５を形成する工程と， 該第３の絶
縁膜５のみを選択的に貫通して，該第１の金属配線２上
に金属配線接続用の接続孔６を形成する工程と， 該接
続孔６底面に露出した該第２の絶縁膜４，および該第３
の絶縁膜５を除去して， 該第１の金属配線２を露出さ
せる工程と， 該接続孔６に該第１の金属配線２に対す
る接続用金属７を選択的に埋め込む工程と， 該接続孔
６を覆って， 該第３の絶縁膜５上に該第２の金属配線
８を形成する工程とを含むことにより解決する。The above-mentioned problems arise in the step of forming the first metal wiring 2 on the semiconductor substrate 1 and the step of forming the first metal wiring 2 on the semiconductor substrate 1, covering the first metal wiring, as in the present invention. Insulating film 3
a step of forming a second insulating film 3 on the first insulating film 3;
a step of forming an insulating film 4 on the second insulating film 4, a step of forming a third insulating film 5 on the second insulating film 4, and a step of selectively penetrating only the third insulating film 5 to A step of forming a contact hole 6 for connecting the metal wire on the first metal wire 2, the second insulating film 4 exposed on the bottom surface of the contact hole 6, and the third
a step of removing the insulating film 5 of the insulating film 5 to expose the first metal wiring 2; a step of selectively embedding a connecting metal 7 for the first metal wiring 2 in the connection hole 6; 6 and forming the second metal wiring 8 on the third insulating film 5.
【００１６】[0016]
【作用】上記のように，本発明によれば，図１に示すよ
うに，金属配線間の層間絶縁膜を三層の絶縁膜で構成し
ている。As described above, according to the present invention, as shown in FIG. 1, the interlayer insulating film between the metal wirings is composed of three layers of insulating films.
【００１７】下層の絶縁膜は，下層金属配線への密着性
の良い絶縁膜である。中間層の絶縁膜は，反応性イオン
エッチング法で上層の絶縁膜を選択的にエッチングして
下層配線上に配線接続孔を開口する際のエッチングの停
止層である。The lower layer insulating film is an insulating film that has good adhesion to the lower layer metal wiring. The intermediate layer insulating film is an etching stop layer when the upper layer insulating film is selectively etched using a reactive ion etching method to open a wiring connection hole on the lower layer wiring.
【００１８】そのため，金属配線間の層間絶縁膜を構成
している上層の絶縁膜の厚さが半導体基板上の金属配線
上で大きく異なっていても，下層配線の金属表面が反応
性イオンに直接曝されることがない。Therefore, even if the thickness of the upper insulating film constituting the interlayer insulating film between metal wirings varies greatly on the metal wiring on the semiconductor substrate, the metal surface of the lower wiring is directly exposed to reactive ions. Not exposed.
【００１９】また，エッチングの停止層である中間層の
絶縁膜の表面にカーボン系の残留物が生じても，中間層
と下層の絶縁膜を除去する際に，容易に除去することが
できる。Furthermore, even if carbon-based residue is generated on the surface of the intermediate layer insulating film, which is an etching stop layer, it can be easily removed when removing the intermediate layer and the lower layer insulating film.
【００２０】さらに，中間層と下層の絶縁膜を除去する
際に，下層配線の金属表面に影響を与えない方法で除去
すれば，反応性イオンエッチング条件に無関係に同一の
金属表面状態が得られるため，開口した配線接続孔に選
択ＣＶＤ法により金属を安定，かつ再現性良く埋め込む
ことができる。Furthermore, when removing the intermediate layer and lower layer insulating film, if the removal is done in a manner that does not affect the metal surface of the lower layer wiring, the same metal surface condition can be obtained regardless of the reactive ion etching conditions. Therefore, it is possible to stably and reproducibly embed metal into the opened wiring connection hole by the selective CVD method.
【００２１】[0021]
【実施例】図２，図３は本発明の一実施例の工程順模式
断面図である。図において，９はＳｉ基板，１０はＳｉ
Ｏ２膜， １１はＴｉＷ／Ａｕ／ＴｉＷ膜， １２はＳ
ｉＯ２膜， １３はＡｌ２Ｏ３ 膜， １４はＰＭＳＳ
樹脂膜， １５はＳｉＯ２膜， １６は接続孔， １７
はＷ膜，１８はＴｉＷ／Ａｕ膜である。Embodiment FIGS. 2 and 3 are schematic sectional views in order of steps of an embodiment of the present invention. In the figure, 9 is a Si substrate, 10 is a Si substrate
O2 film, 11 is TiW/Au/TiW film, 12 is S
iO2 film, 13 is Al2O3 film, 14 is PMSS
Resin film, 15 is SiO2 film, 16 is connection hole, 17
18 is a W film, and 18 is a TiW/Au film.
【００２２】図２により，工程順に本発明の一実施例を
説明する。図２（ａ）に示すように，半導体基板，例え
ば，シリコン（Ｓｉ）基板９上にプラズマＣＶＤ法によ
り，二酸化シリコン（ＳｉＯ２）膜１０を１μｍの厚さ
に被覆し，その上にチタン・タングステン（ＴｉＷ）
を３０ｎｍ， 金（Ａｕ）を７００ｎｍ， ＴｉＷを３
０ｎｍの厚さに連続してスパッタ法により積層し， パ
ターニングして第１層目の金属配線としてのＴｉＷ／Ａ
ｕ／ＴｉＷ膜１１を形成する。An embodiment of the present invention will be explained in order of steps with reference to FIG. As shown in FIG. 2(a), a silicon dioxide (SiO2) film 10 with a thickness of 1 μm is coated on a semiconductor substrate, for example, a silicon (Si) substrate 9, by the plasma CVD method, and titanium and tungsten are coated on the silicon dioxide (SiO2) film 10 to a thickness of 1 μm. (TiW)
30 nm, gold (Au) 700 nm, TiW 3
TiW/A is laminated continuously to a thickness of 0 nm by sputtering and patterned to form the first layer of metal wiring.
A u/TiW film 11 is formed.
【００２３】図２（ｂ）に示すように，例えば，イオン
ビームアシスト蒸着法，またはスパッタ法により，Ｓｉ
Ｏ２膜１２を２０ｎｍ， 酸化アルミニウム（Ａｌ２Ｏ
３） 膜１３を５ｎｍの厚さに連続して積層蒸着する。As shown in FIG. 2(b), for example, Si is deposited by ion beam assisted vapor deposition or sputtering.
The O2 film 12 is 20 nm thick and made of aluminum oxide (Al2O
3) Continuously deposit the film 13 to a thickness of 5 nm.
【００２４】図２（ｃ）に示すように，例えば，シリコ
ーン樹脂の一種である日本ゼオン社製のシリル化ポリメ
チルシルセスキオキサン（ＰＭＳＳ）樹脂膜１４をスピ
ンコート法により １．５μｍの厚さに塗布し， ３５
０℃で１時間加熱して硬化する。As shown in FIG. 2(c), for example, a silylated polymethylsilsesquioxane (PMSS) resin film 14 manufactured by Nippon Zeon Co., Ltd., which is a type of silicone resin, is deposited to a thickness of 1.5 μm by spin coating. 35
It is cured by heating at 0° C. for 1 hour.
【００２５】続いて，例えば，イオンビームアシスト蒸
着法により，ＳｉＯ２膜１５を ２００ｎｍの厚さに形
成する。続いて，図２（ｄ）に示すように，レジストマ
スクを用いて，ＲＩＥ法により，弗化炭素系（ＣＨＦ３
， ＣＦ４， Ｃ２Ｆ６） 或いは六弗化硫黄（ＳＦ６
） のガスとヘリウム（Ｈｅ）の混合ガスを用いて，
ＳｉＯ２膜１５， 及びＰＭＳＳ樹脂膜１４をエッチン
グして，接続孔１６を開口する。Subsequently, the SiO2 film 15 is formed to a thickness of 200 nm by, for example, ion beam assisted vapor deposition. Next, as shown in Figure 2(d), using a resist mask, carbon fluoride (CHF3) was applied by RIE method.
, CF4, C2F6) or sulfur hexafluoride (SF6
) and helium (He),
The SiO2 film 15 and the PMSS resin film 14 are etched to open connection holes 16.
【００２６】この場合， 前記ＲＩＥにより Ａｌ２０
３膜１３は殆どエッチングされないため， ２００％程
度オーバーエッチングしても， Ａｌ２０３膜１３が
露出した状態でエッチングが停止する。[0026] In this case, by the RIE, Al20
Since the Al203 film 13 is hardly etched, even if the Al203 film 13 is over-etched by about 200%, the etching will stop with the Al203 film 13 exposed.
【００２７】図３（ｅ）に示すように，例えば，希釈弗
化水素水溶液，または緩衝弗化水素水溶液により，Ａｌ
２０３膜１３，及びＳｉＯ２膜１２を除去し， 第１層
目の金属配線の ＴｉＷ表面を露出する。As shown in FIG. 3(e), for example, Al
The 203 film 13 and the SiO2 film 12 are removed to expose the TiW surface of the first layer metal wiring.
【００２８】図３（ｆ）に示すように，減圧下の反応容
器中でＳｉ基板９を ２６０℃に加熱して， ＷＦ６
とＳｉＨ４とＨ２の混合ガスを用いて， 接続孔１６内
にＷ１７を選択的に堆積する。その後， 図３（ｇ）に
示すように，ＴｉＷ を３０ｎｍ， Ａｕを ７００ｎ
ｍの厚さにスパッタ法により連続して積層蒸着し， パ
ターニングして第２の金属配線，ＴｉＷ／Ａｕ膜１８を
形成する。As shown in FIG. 3(f), the Si substrate 9 is heated to 260° C. in a reaction vessel under reduced pressure, and then heated to WF6.
W17 is selectively deposited in the connection hole 16 using a mixed gas of SiH4 and H2. After that, as shown in Figure 3(g), TiW was 30nm thick and Au was 700nm thick.
The TiW/Au film 18, which is a second metal wiring, is formed by successively depositing layers to a thickness of m by sputtering and patterning.
【００２９】この工程を繰り返せば，三層以上の多層配
線形成ができる。前記実施例では，絶縁膜１４としてＰ
ＭＳＳ樹脂を用いた場合を例示したが， ポリシロキサ
ンなどのＳＯＧ膜を適用することもできる。By repeating this process, multilayer wiring of three or more layers can be formed. In the above embodiment, P is used as the insulating film 14.
Although the case where MSS resin is used is shown as an example, it is also possible to apply an SOG film such as polysiloxane.
【００３０】絶縁膜１４，１５ として一層の無機膜を
用いた場合にも適用できることはいうまでもない。また
，前記実施例では，ＰＭＳＳ樹脂膜の下の絶縁膜をＳｉ
Ｏ２／Ａｌ２０３膜としたが，ＳｉＯ２／Ａｌ２０３／
ＳｉＯ２膜としても良い。It goes without saying that the invention can also be applied to the case where a single layer of inorganic film is used as the insulating films 14 and 15. Furthermore, in the above embodiment, the insulating film under the PMSS resin film is made of Si.
O2/Al203 film was used, but SiO2/Al203/
It may also be a SiO2 film.
【００３１】[0031]
【発明の効果】以上説明したように， 本発明によれば
， 金属配線間の層間接続孔を開口する際に， 層間絶
縁膜の下層配線付近にエッチングの停止層を設けている
ため， 下層配線上の層間絶縁膜の厚みが半導体基板上
で異なっていても， 配線金属表面に影響を与えない。[Effects of the Invention] As explained above, according to the present invention, when opening an interlayer connection hole between metal wirings, an etching stop layer is provided near the lower wiring of the interlayer insulating film. Even if the thickness of the upper interlayer insulating film differs on the semiconductor substrate, it will not affect the wiring metal surface.
【００３２】従って， 接続孔に露出した金属表面は半
導体基板上に亙って汚染のない同一の表面状態が得られ
るため， 開口した配線接続孔に選択ＣＶＤ 法により
接続用金属を安定， かつ再現性良く形成することがで
き， 多層配線の信頼性の向上に寄与するところが大き
い。[0032] Therefore, since the metal surface exposed in the connection hole can have the same surface condition free of contamination over the entire semiconductor substrate, it is possible to stably and reproduce the connection metal in the opened wiring connection hole by selective CVD. It can be formed with good performance and greatly contributes to improving the reliability of multilayer wiring.
【図１】 本発明の原理説明図[Figure 1] Diagram explaining the principle of the present invention
【図２】 本発明の一実施例の工程順模式断面図（そ
の１）[Fig. 2] Schematic sectional view of the process order of one embodiment of the present invention (Part 1)
【図３】 本発明の一実施例の工程順模式断面図（そ
の２）[Fig. 3] Schematic cross-sectional view of the process order of one embodiment of the present invention (Part 2)
１ 半導体基板 ２ 第１の金属配線 ３ 第１の絶縁膜 ４ 第２の絶縁膜 ５ 第３の絶縁膜 ６ 接続孔 ７ 接続用金属 ８ 第２の金属配線 ９ Ｓｉ基板 １０ ＳｉＯ２膜 １１ ＴｉＷ／Ａｕ／ＴｉＷ膜 １２ ＳｉＯ２膜 １３ Ａｌ２Ｏ３ 膜 １４ ＰＭＳＳ樹脂膜 １５ ＳｉＯ２膜 １６ 接続孔 １７ Ｗ膜 １８ ＴｉＷ／Ａｕ膜 1 Semiconductor substrate 2 First metal wiring 3 First insulating film 4 Second insulating film 5 Third insulating film 6 Connection hole 7 Connection metal 8 Second metal wiring 9 Si substrate 10 SiO2 film 11 TiW/Au/TiW film 12 SiO2 film 13 Al2O3 film 14 PMSS resin film 15 SiO2 film 16 Connection hole 17 W film 18 TiW/Au film
Claims (6)
線（２） を形成する工程と，該第１の金属配線を覆っ
て，該半導体基板（１） 上に第１の絶縁膜（３） を
形成する工程と，該第１の絶縁膜（３） の上に， 第
２の絶縁膜（４） を形成する工程と，該第２の絶縁膜
（４） の上に， 第３の絶縁膜（５） を形成する工
程と，該第３の絶縁膜のみを選択的に貫通して，該第１
の金属配線（２） 上に金属配線接続用の接続孔（６）
を形成する工程と，該接続孔（６） 底面に露出した
該第２の絶縁膜（４），および該第３の絶縁膜（５）
を除去して， 該第１の金属配線（２） を露出させる
工程と，該接続孔（６） に該第１の金属配線（２）
に対する接続用金属（７） を選択的に埋め込む工程と
，該接続孔（６） を覆って， 該第３の絶縁膜（５）
上に該第２の金属配線（８）を形成する工程とを含む
ことを特徴とする半導体装置の製造方法。1. A step of forming a first metal wiring (2) on a semiconductor substrate (1), and forming a first insulating film (2) on the semiconductor substrate (1), covering the first metal wiring. 3) A step of forming a second insulating film (4) on the first insulating film (3), and a step of forming a third insulating film (4) on the second insulating film (4). forming an insulating film (5), and selectively penetrating only the third insulating film to form the first insulating film (5).
Metal wiring (2) Connection hole for connecting metal wiring (6) on top
the second insulating film (4) exposed at the bottom of the connection hole (6), and the third insulating film (5);
removing the first metal wiring (2) to expose the first metal wiring (2), and inserting the first metal wiring (2) into the connection hole (6).
a step of selectively embedding a connection metal (7) into the connection hole (6); and a step of selectively filling the connection hole (6) with the third insulating film (5).
A method of manufacturing a semiconductor device, comprising the step of forming the second metal wiring (8) thereon.
リコン膜， 酸化窒化シリコン膜， 窒化シリコン膜の
何れかであることを特徴とする請求項１記載の半導体装
置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film (3) is one of a silicon dioxide film, a silicon oxynitride film, and a silicon nitride film.
ミニウムからなることを特徴とする請求項１記載の半導
体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film (4) is made of aluminum oxide.
に耐酸素プラズマ性の無機膜， 下層に平坦性の良い有
機膜からなる， 少なくとも二層以上の異なる絶縁膜か
らなることを特徴とする請求項１記載の半導体装置の製
造方法。4. The third insulating film (5) is composed of at least two different insulating films, the upper layer being an oxygen plasma-resistant inorganic film and the lower layer being an organic film with good flatness. 2. The method of manufacturing a semiconductor device according to claim 1.
少なくともポリシロキサン膜， 或いはシリコーン樹
脂膜が含まれることを特徴とする請求項１記載の半導体
装置の製造方法。5. In a lower layer of the third insulating film (5),
2. The method of manufacturing a semiconductor device according to claim 1, wherein at least a polysiloxane film or a silicone resin film is included.
的に貫通するに際し，弗化物系のガスを用いた反応性イ
オンエッチングを用いることを特徴とする請求項１記載
の半導体装置の製造方法。6. The semiconductor device according to claim 1, wherein reactive ion etching using a fluoride gas is used to selectively penetrate only the third insulating film (5). Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8281491A JPH04316351A (en) | 1991-04-16 | 1991-04-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8281491A JPH04316351A (en) | 1991-04-16 | 1991-04-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04316351A true JPH04316351A (en) | 1992-11-06 |
Family
ID=13784876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8281491A Withdrawn JPH04316351A (en) | 1991-04-16 | 1991-04-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04316351A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001308182A (en) * | 2000-04-27 | 2001-11-02 | Nec Corp | Method for forming contact with chromium film |
| US6383916B1 (en) * | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
| US7294871B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7405149B1 (en) | 1998-12-21 | 2008-07-29 | Megica Corporation | Post passivation method for semiconductor chip or wafer |
| US8546947B2 (en) | 2001-12-13 | 2013-10-01 | Megica Corporation | Chip structure and process for forming the same |
-
1991
- 1991-04-16 JP JP8281491A patent/JPH04316351A/en not_active Withdrawn
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7372085B2 (en) | 1998-12-21 | 2008-05-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US6383916B1 (en) * | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
| US7294871B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7294870B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7329954B2 (en) | 1998-12-21 | 2008-02-12 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7368376B2 (en) | 1998-12-21 | 2008-05-06 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7372155B2 (en) | 1998-12-21 | 2008-05-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7384864B2 (en) | 1998-12-21 | 2008-06-10 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7405149B1 (en) | 1998-12-21 | 2008-07-29 | Megica Corporation | Post passivation method for semiconductor chip or wafer |
| US7420276B2 (en) | 1998-12-21 | 2008-09-02 | Megica Corporation | Post passivation structure for semiconductor chip or wafer |
| US7422976B2 (en) | 1998-12-21 | 2008-09-09 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| JP2001308182A (en) * | 2000-04-27 | 2001-11-02 | Nec Corp | Method for forming contact with chromium film |
| US8546947B2 (en) | 2001-12-13 | 2013-10-01 | Megica Corporation | Chip structure and process for forming the same |
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