JPH04312933A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04312933A
JPH04312933A JP6577491A JP6577491A JPH04312933A JP H04312933 A JPH04312933 A JP H04312933A JP 6577491 A JP6577491 A JP 6577491A JP 6577491 A JP6577491 A JP 6577491A JP H04312933 A JPH04312933 A JP H04312933A
Authority
JP
Japan
Prior art keywords
semiconductor element
adhesive
semiconductor device
die pad
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6577491A
Other languages
Japanese (ja)
Inventor
Hiroshi Kawashita
川下　浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6577491A priority Critical patent/JPH04312933A/en
Publication of JPH04312933A publication Critical patent/JPH04312933A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To increase an adhesive area between a semiconductor element and an adhesive agent to reinforce an adhesive force and prevent from generating an interface separation by a method wherein recesses and protrusions are formed on an adhesive surface of the semiconductor element in order to adhere and fix the semiconductor element onto a die pad. CONSTITUTION:A plurality of recessed and protrusions 22 are formed on an adhesive surface 21a of a semiconductor element 21. The semiconductor element 21 is adhered and fixed onto an upper surface of a die pad 23 by an adhesive agent 24 to constitute a semiconductor device 25. This increases the bonding area between the semiconductor element and the adhesive agent to enhance the bonding force thus preventing generation of interface separation, resulting in improvement of reliability.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】この発明は、ダイパッド上に半導
体素子を接着により固定した半導体装置に係り、特に半
導体素子の接着面の構造の改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element is fixed on a die pad by adhesive, and more particularly to an improvement in the structure of the bonding surface of the semiconductor element.

【０００２】0002

【従来の技術】図６はこの種従来の半導体装置の構成を
示す断面図である。図に示すように、従来の半導体装置
はダイパッド１上に接着剤２により半導体素子３が接着
されている。2. Description of the Related Art FIG. 6 is a sectional view showing the structure of a conventional semiconductor device of this type. As shown in the figure, in the conventional semiconductor device, a semiconductor element 3 is bonded onto a die pad 1 with an adhesive 2. As shown in FIG.

【０００３】0003

【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、半導体素子３と接着剤
２とは平面的に接触しているのみであるため、接着力が
弱く界面剥離が発生して信頼性が低下するという問題点
があった。この発明は上記のような問題点を解消するた
めになされたもので、半導体素子と接着剤との接着面積
を増大することにより接着力を強化し、界面剥離の発生
を防止して信頼性の向上が可能な半導体装置を提供する
ことを目的とするものである。[Problems to be Solved by the Invention] Since the conventional semiconductor device is constructed as described above, the semiconductor element 3 and the adhesive 2 are in only two-dimensional contact, so the adhesive force is weak and the interface There was a problem in that peeling occurred and reliability decreased. This invention was made to solve the above-mentioned problems, and by increasing the adhesive area between the semiconductor element and the adhesive, it strengthens the adhesive force, prevents interfacial peeling, and improves reliability. The purpose is to provide a semiconductor device that can be improved.

【０００４】0004

【課題を解決するための手段】この発明に係る半導体装
置は、半導体素子の接着面に凹凸を形成し、ダイパッド
上に接着により固定したものである。SUMMARY OF THE INVENTION In a semiconductor device according to the present invention, irregularities are formed on the adhesive surface of a semiconductor element, and the semiconductor element is fixed onto a die pad by adhesive.

【０００５】[0005]

【作用】この発明における半導体装置の半導体素子の接
着面に形成された凹凸は、接着剤と半導体素子との接着
面積を増大し、接着力を強化する。[Operation] The unevenness formed on the adhesive surface of the semiconductor element of the semiconductor device of the present invention increases the adhesive area between the adhesive and the semiconductor element and strengthens the adhesive force.

【０００６】[0006]

【実施例】実施例１．図１（Ａ），（Ｂ）はこの発明の
実施例１における半導体装置に適用される半導体素子の
構成をそれぞれ示す断面図および斜視図である。図にお
いて、２１は半導体素子で、接着面２１ａには半球状の
凹部２２が複数個所形成されている。そして、図２に示
すようにこの半導体素子２１はダイパッド２３の上面に
、接着剤２４により接着固定され半導体装置２５が構成
される。[Example] Example 1. 1A and 1B are a cross-sectional view and a perspective view, respectively, showing the structure of a semiconductor element applied to a semiconductor device according to a first embodiment of the present invention. In the figure, 21 is a semiconductor element, and a plurality of hemispherical recesses 22 are formed on the adhesive surface 21a. Then, as shown in FIG. 2, this semiconductor element 21 is adhesively fixed to the upper surface of the die pad 23 using an adhesive 24 to form a semiconductor device 25.

【０００７】実施例２．図３（Ａ），（Ｂ）はこの発明
の実施例２における半導体装置に適用される半導体素子
の構成をそれぞれ示す断面図および斜視図である。３１
は半導体素子で、接着面３１ａは格子状の溝３２が形成
されている。そして、図４に示すように、この半導体素
子３１はダイパッド３３の上面に、接着剤３４により接
着固定され半導体装置３５が構成される。Example 2. 3A and 3B are a cross-sectional view and a perspective view, respectively, showing the structure of a semiconductor element applied to a semiconductor device according to a second embodiment of the present invention. 31
is a semiconductor element, and a bonding surface 31a has a grid-like groove 32 formed therein. Then, as shown in FIG. 4, this semiconductor element 31 is adhesively fixed to the upper surface of the die pad 33 with an adhesive 34 to form a semiconductor device 35.

【０００８】実施例３．図５はこの発明の実施例３にお
ける半導体装置の構成を示す断面図である。図に示すよ
うに、半導体素子４１の接着面４１ａには半球状の凸部
４２が複数個所突設され、この半導体素子４１はダイパ
ッド４３の上面に、接着剤４４により接着固定され半導
体装置４５が構成される。上記したように、各実施例に
おける各半導体素子２１，３１，４１の各接着面２１ａ
，３１ａ，４１ａにはそれぞれ半球状の凹部２２、格子
状の溝３２、半球状の凸部４２、すなわち凹凸が形成さ
れているため、接着面積が図６における従来装置と比較
して大幅に増大され接着力は強化されている。Example 3. FIG. 5 is a cross-sectional view showing the structure of a semiconductor device in Example 3 of the present invention. As shown in the figure, a plurality of hemispherical convex portions 42 are protruded from an adhesive surface 41a of a semiconductor element 41, and this semiconductor element 41 is adhesively fixed to the upper surface of a die pad 43 with an adhesive 44, and a semiconductor device 45 is attached. configured. As described above, each adhesive surface 21a of each semiconductor element 21, 31, 41 in each embodiment
, 31a, and 41a are each formed with hemispherical recesses 22, lattice-like grooves 32, and hemispherical protrusions 42, that is, unevenness, so that the bonding area is significantly increased compared to the conventional device shown in FIG. The adhesive strength has been strengthened.

【０００９】尚、上記実施例２における格子状の溝３２
は、いずれか一方向に形成された複数本の溝でも良く、
又、実施例１，３における凹部２２および凸部４２は、
例えば円錐状、角錐状に形成された凹部および凸部でも
良く、半球状に限定されるものではない。Note that the lattice-shaped grooves 32 in the second embodiment
may be multiple grooves formed in any one direction,
Moreover, the recessed portion 22 and the convex portion 42 in Examples 1 and 3 are as follows:
For example, concave portions and convex portions formed in the shape of a cone or pyramid may be used, and the shape is not limited to a hemispherical shape.

【００１０】0010

【発明の効果】以上のように、この発明によれば半導体
素子の接着面に凹凸を形成し、ダイパッド上に接着によ
り固定することにより、半導体素子と接着剤との接着面
積を増大して接着力を強化し、界面剥離の発生を防止し
て信頼性の向上を図ることが可能な半導体装置を提供す
ることができる。As described above, according to the present invention, by forming irregularities on the adhesive surface of a semiconductor element and fixing it onto a die pad by adhesive, the adhesive area between the semiconductor element and the adhesive is increased and the adhesive is improved. It is possible to provide a semiconductor device that can strengthen the force, prevent interfacial peeling, and improve reliability.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】この発明の実施例１における半導体装置に適用
される半導体素子の構成を示すもので、（Ａ）は断面図
および（Ｂ）は斜視図である。FIG. 1 shows the configuration of a semiconductor element applied to a semiconductor device according to a first embodiment of the present invention, in which (A) is a cross-sectional view and (B) is a perspective view.

【図２】この発明の実施例１における半導体装置の構成
を示す断面図である。FIG. 2 is a cross-sectional view showing the configuration of a semiconductor device in Example 1 of the present invention.

【図３】この発明の実施例２における半導体装置に適用
される半導体素子の構成を示すもので、（Ａ）は断面図
および（Ｂ）は斜視図である。FIG. 3 shows the structure of a semiconductor element applied to a semiconductor device according to a second embodiment of the present invention, in which (A) is a cross-sectional view and (B) is a perspective view.

【図４】この発明の実施例２における半導体装置の構成
を示す断面図である。FIG. 4 is a cross-sectional view showing the configuration of a semiconductor device in Example 2 of the present invention.

【図５】この発明の実施例３における半導体装置の構成
を示す断面図である。FIG. 5 is a cross-sectional view showing the configuration of a semiconductor device in Example 3 of the present invention.

【図６】従来の半導体装置の構成を示す断面図である。FIG. 6 is a cross-sectional view showing the configuration of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

２１，３１，４１　　半導体素子 ２１ａ，３１ａ，４１ａ　　接着面 ２２　　半球状の凹部 ２３，３３，４３　　ダイパッド ２４，３４，４４　　接着剤 ３２　　格子状の溝 ４２　　半球状の凸部 21, 31, 41 Semiconductor element 21a, 31a, 41a Adhesive surface 22 Hemispherical recess 23, 33, 43 Die pad 24, 34, 44 Adhesive 32 Lattice groove 42　Semispherical convex part

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　ダイパッド上に半導体素子を接着剤に
より接着した半導体装置において、上記半導体素子の接
着面に凹凸を形成したことを特徴とする半導体装置。1. A semiconductor device in which a semiconductor element is bonded onto a die pad with an adhesive, characterized in that an unevenness is formed on the bonding surface of the semiconductor element.
JP6577491A 1991-03-29 1991-03-29 Semiconductor device Pending JPH04312933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6577491A JPH04312933A (en) 1991-03-29 1991-03-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6577491A JPH04312933A (en) 1991-03-29 1991-03-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04312933A true JPH04312933A (en) 1992-11-04

Family

ID=13296717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6577491A Pending JPH04312933A (en) 1991-03-29 1991-03-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04312933A (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5347162A (en) * 1989-08-28 1994-09-13 Lsi Logic Corporation Preformed planar structures employing embedded conductors
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US5789820A (en) * 1996-02-28 1998-08-04 Nec Corporation Method for manufacturing heat radiating resin-molded semiconductor device
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
KR20030047688A (en) * 2001-12-03 2003-06-18 미쓰비시덴키 가부시키가이샤 Semiconductor package
JP2005203970A (en) * 2004-01-14 2005-07-28 Murata Mfg Co Ltd Piezoelectric resonance component
JP2006108993A (en) * 2004-10-04 2006-04-20 Hitachi Media Electoronics Co Ltd Surface acoustic wave device and manufacturing method thereof
JP2007103996A (en) * 2005-09-30 2007-04-19 Kyocera Kinseki Corp Package for piezoelectric device
JP2008011311A (en) * 2006-06-30 2008-01-17 Kyocera Kinseki Corp Piezoelectric device
JP2008252061A (en) * 2007-03-08 2008-10-16 Nissan Motor Co Ltd Semiconductor device and method of manufacturing the same
JP2011097060A (en) * 2009-10-28 2011-05-12 Samsung Electro-Mechanics Co Ltd Flip-chip package and method of manufacturing the same
US8575726B2 (en) 2007-03-08 2013-11-05 Nissan Motor Co., Ltd. Semiconductor device and method of manufacturing the same
JP2014203861A (en) * 2013-04-02 2014-10-27 三菱電機株式会社 Semiconductor device and semiconductor module
US20170323844A1 (en) * 2016-08-03 2017-11-09 Soliduv, Inc. Strain-Tolerant Die Attach with Improved Thermal Conductivity, and Method of Fabrication
US10475717B2 (en) 2017-02-21 2019-11-12 Murata Manufacturing Co., Ltd. Semiconductor chip, method for mounting semiconductor chip, and module in which semiconductor chip is packaged
KR20210006410A (en) * 2018-05-31 2021-01-18 인스티튜트 오브 플렉서블 일렉트로닉스 테크놀로지 오브 투, 저장 Transient device of flexible element, manufacturing method and manufacturing method of flexible element

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US5410805A (en) * 1989-08-28 1995-05-02 Lsi Logic Corporation Method and apparatus for isolation of flux materials in "flip-chip" manufacturing
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5347162A (en) * 1989-08-28 1994-09-13 Lsi Logic Corporation Preformed planar structures employing embedded conductors
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US5789820A (en) * 1996-02-28 1998-08-04 Nec Corporation Method for manufacturing heat radiating resin-molded semiconductor device
KR20030047688A (en) * 2001-12-03 2003-06-18 미쓰비시덴키 가부시키가이샤 Semiconductor package
JP4513327B2 (en) * 2004-01-14 2010-07-28 株式会社村田製作所 Piezoelectric resonance component
JP2005203970A (en) * 2004-01-14 2005-07-28 Murata Mfg Co Ltd Piezoelectric resonance component
JP2006108993A (en) * 2004-10-04 2006-04-20 Hitachi Media Electoronics Co Ltd Surface acoustic wave device and manufacturing method thereof
JP2007103996A (en) * 2005-09-30 2007-04-19 Kyocera Kinseki Corp Package for piezoelectric device
JP2008011311A (en) * 2006-06-30 2008-01-17 Kyocera Kinseki Corp Piezoelectric device
JP2008252061A (en) * 2007-03-08 2008-10-16 Nissan Motor Co Ltd Semiconductor device and method of manufacturing the same
US8575726B2 (en) 2007-03-08 2013-11-05 Nissan Motor Co., Ltd. Semiconductor device and method of manufacturing the same
JP2011097060A (en) * 2009-10-28 2011-05-12 Samsung Electro-Mechanics Co Ltd Flip-chip package and method of manufacturing the same
US8558360B2 (en) 2009-10-28 2013-10-15 Samsung Electro-Mechanics Co., Ltd. Flip chip package and method of manufacturing the same
US8809122B2 (en) 2009-10-28 2014-08-19 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing flip chip package
JP2014203861A (en) * 2013-04-02 2014-10-27 三菱電機株式会社 Semiconductor device and semiconductor module
US9613888B2 (en) 2013-04-02 2017-04-04 Mitsubishi Electric Corporation Semiconductor device and semiconductor module
US20170323844A1 (en) * 2016-08-03 2017-11-09 Soliduv, Inc. Strain-Tolerant Die Attach with Improved Thermal Conductivity, and Method of Fabrication
US10410958B2 (en) * 2016-08-03 2019-09-10 Soliduv, Inc. Strain-tolerant die attach with improved thermal conductivity, and method of fabrication
US10475717B2 (en) 2017-02-21 2019-11-12 Murata Manufacturing Co., Ltd. Semiconductor chip, method for mounting semiconductor chip, and module in which semiconductor chip is packaged
US10665519B2 (en) 2017-02-21 2020-05-26 Murata Manufacturing Co., Ltd. Semiconductor chip, method for mounting semiconductor chip, and module in which semiconductor chip is packaged
KR20210006410A (en) * 2018-05-31 2021-01-18 인스티튜트 오브 플렉서블 일렉트로닉스 테크놀로지 오브 투, 저장 Transient device of flexible element, manufacturing method and manufacturing method of flexible element

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